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eukrea-tlv320: fix platform_name
[deliverable/linux.git] / sound / soc / codecs / wm9081.c
CommitLineData
86ed3669
MB		 1/*
2 * wm9081.c -- WM9081 ALSA SoC Audio driver
3 *
4 * Author: Mark Brown
5 *
6 * Copyright 2009 Wolfson Microelectronics plc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
5a0e3ad6 21#include <linux/slab.h>
86ed3669
MB		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
86ed3669
MB		 26#include <sound/initval.h>
27#include <sound/tlv.h>
28
29#include <sound/wm9081.h>
30#include "wm9081.h"
31
32static u16 wm9081_reg_defaults[] = {
33 0x0000, /* R0 - Software Reset */
34 0x0000, /* R1 */
35 0x00B9, /* R2 - Analogue Lineout */
36 0x00B9, /* R3 - Analogue Speaker PGA */
37 0x0001, /* R4 - VMID Control */
38 0x0068, /* R5 - Bias Control 1 */
39 0x0000, /* R6 */
40 0x0000, /* R7 - Analogue Mixer */
41 0x0000, /* R8 - Anti Pop Control */
42 0x01DB, /* R9 - Analogue Speaker 1 */
43 0x0018, /* R10 - Analogue Speaker 2 */
44 0x0180, /* R11 - Power Management */
45 0x0000, /* R12 - Clock Control 1 */
46 0x0038, /* R13 - Clock Control 2 */
47 0x4000, /* R14 - Clock Control 3 */
48 0x0000, /* R15 */
49 0x0000, /* R16 - FLL Control 1 */
50 0x0200, /* R17 - FLL Control 2 */
51 0x0000, /* R18 - FLL Control 3 */
52 0x0204, /* R19 - FLL Control 4 */
53 0x0000, /* R20 - FLL Control 5 */
54 0x0000, /* R21 */
55 0x0000, /* R22 - Audio Interface 1 */
56 0x0002, /* R23 - Audio Interface 2 */
57 0x0008, /* R24 - Audio Interface 3 */
58 0x0022, /* R25 - Audio Interface 4 */
59 0x0000, /* R26 - Interrupt Status */
60 0x0006, /* R27 - Interrupt Status Mask */
61 0x0000, /* R28 - Interrupt Polarity */
62 0x0000, /* R29 - Interrupt Control */
63 0x00C0, /* R30 - DAC Digital 1 */
64 0x0008, /* R31 - DAC Digital 2 */
65 0x09AF, /* R32 - DRC 1 */
66 0x4201, /* R33 - DRC 2 */
67 0x0000, /* R34 - DRC 3 */
68 0x0000, /* R35 - DRC 4 */
69 0x0000, /* R36 */
70 0x0000, /* R37 */
71 0x0000, /* R38 - Write Sequencer 1 */
72 0x0000, /* R39 - Write Sequencer 2 */
73 0x0002, /* R40 - MW Slave 1 */
74 0x0000, /* R41 */
75 0x0000, /* R42 - EQ 1 */
76 0x0000, /* R43 - EQ 2 */
77 0x0FCA, /* R44 - EQ 3 */
78 0x0400, /* R45 - EQ 4 */
79 0x00B8, /* R46 - EQ 5 */
80 0x1EB5, /* R47 - EQ 6 */
81 0xF145, /* R48 - EQ 7 */
82 0x0B75, /* R49 - EQ 8 */
83 0x01C5, /* R50 - EQ 9 */
84 0x169E, /* R51 - EQ 10 */
85 0xF829, /* R52 - EQ 11 */
86 0x07AD, /* R53 - EQ 12 */
87 0x1103, /* R54 - EQ 13 */
88 0x1C58, /* R55 - EQ 14 */
89 0xF373, /* R56 - EQ 15 */
90 0x0A54, /* R57 - EQ 16 */
91 0x0558, /* R58 - EQ 17 */
92 0x0564, /* R59 - EQ 18 */
93 0x0559, /* R60 - EQ 19 */
94 0x4000, /* R61 - EQ 20 */
95};
96
97static struct {
98 int ratio;
99 int clk_sys_rate;
100} clk_sys_rates[] = {
101 { 64, 0 },
102 { 128, 1 },
103 { 192, 2 },
104 { 256, 3 },
105 { 384, 4 },
106 { 512, 5 },
107 { 768, 6 },
108 { 1024, 7 },
109 { 1408, 8 },
110 { 1536, 9 },
111};
112
113static struct {
114 int rate;
115 int sample_rate;
116} sample_rates[] = {
117 { 8000, 0 },
118 { 11025, 1 },
119 { 12000, 2 },
120 { 16000, 3 },
121 { 22050, 4 },
122 { 24000, 5 },
123 { 32000, 6 },
124 { 44100, 7 },
125 { 48000, 8 },
126 { 88200, 9 },
127 { 96000, 10 },
128};
129
130static struct {
131 int div; /* *10 due to .5s */
132 int bclk_div;
133} bclk_divs[] = {
134 { 10, 0 },
135 { 15, 1 },
136 { 20, 2 },
137 { 30, 3 },
138 { 40, 4 },
139 { 50, 5 },
140 { 55, 6 },
141 { 60, 7 },
142 { 80, 8 },
143 { 100, 9 },
144 { 110, 10 },
145 { 120, 11 },
146 { 160, 12 },
147 { 200, 13 },
148 { 220, 14 },
149 { 240, 15 },
150 { 250, 16 },
151 { 300, 17 },
152 { 320, 18 },
153 { 440, 19 },
154 { 480, 20 },
155};
156
157struct wm9081_priv {
f0fba2ad
LG		 158 enum snd_soc_control_type control_type;
159 void *control_data;
86ed3669
MB		 160 int sysclk_source;
161 int mclk_rate;
162 int sysclk_rate;
163 int fs;
164 int bclk;
165 int master;
166 int fll_fref;
167 int fll_fout;
e0026bea 168 int tdm_width;
86ed3669
MB		 169 struct wm9081_retune_mobile_config *retune;
170};
171
8d50e447 172static int wm9081_volatile_register(unsigned int reg)
86ed3669
MB		 173{
174 switch (reg) {
8d50e447
MB		 175 case WM9081_SOFTWARE_RESET:
176 return 1;
86ed3669
MB		 177 default:
178 return 0;
179 }
180}
181
86ed3669
MB		 182static int wm9081_reset(struct snd_soc_codec *codec)
183{
8d50e447 184 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
86ed3669
MB		 185}
186
187static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
188static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
189static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
190static unsigned int drc_max_tlv[] = {
191 TLV_DB_RANGE_HEAD(4),
192 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
193 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
194 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
195 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
196};
197static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
198static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
199
200static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
201
202static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
203static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
204static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
205
206static const char *drc_high_text[] = {
207 "1",
208 "1/2",
209 "1/4",
210 "1/8",
211 "1/16",
212 "0",
213};
214
215static const struct soc_enum drc_high =
216 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
217
218static const char *drc_low_text[] = {
219 "1",
220 "1/2",
221 "1/4",
222 "1/8",
223 "0",
224};
225
226static const struct soc_enum drc_low =
227 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
228
229static const char *drc_atk_text[] = {
230 "181us",
231 "181us",
232 "363us",
233 "726us",
234 "1.45ms",
235 "2.9ms",
236 "5.8ms",
237 "11.6ms",
238 "23.2ms",
239 "46.4ms",
240 "92.8ms",
241 "185.6ms",
242};
243
244static const struct soc_enum drc_atk =
245 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
246
247static const char *drc_dcy_text[] = {
248 "186ms",
249 "372ms",
250 "743ms",
251 "1.49s",
252 "2.97s",
253 "5.94s",
254 "11.89s",
255 "23.78s",
256 "47.56s",
257};
258
259static const struct soc_enum drc_dcy =
260 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
261
262static const char *drc_qr_dcy_text[] = {
263 "0.725ms",
264 "1.45ms",
265 "5.8ms",
266};
267
268static const struct soc_enum drc_qr_dcy =
269 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
270
271static const char *dac_deemph_text[] = {
272 "None",
273 "32kHz",
274 "44.1kHz",
275 "48kHz",
276};
277
278static const struct soc_enum dac_deemph =
279 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
280
281static const char *speaker_mode_text[] = {
282 "Class D",
283 "Class AB",
284};
285
286static const struct soc_enum speaker_mode =
287 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
288
289static int speaker_mode_get(struct snd_kcontrol *kcontrol,
290 struct snd_ctl_elem_value *ucontrol)
291{
292 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
293 unsigned int reg;
294
8d50e447 295 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 296 if (reg & WM9081_SPK_MODE)
297 ucontrol->value.integer.value[0] = 1;
298 else
299 ucontrol->value.integer.value[0] = 0;
300
301 return 0;
302}
303
304/*
305 * Stop any attempts to change speaker mode while the speaker is enabled.
306 *
307 * We also have some special anti-pop controls dependant on speaker
308 * mode which must be changed along with the mode.
309 */
310static int speaker_mode_put(struct snd_kcontrol *kcontrol,
311 struct snd_ctl_elem_value *ucontrol)
312{
313 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
8d50e447
MB		 314 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
315 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 316
317 /* Are we changing anything? */
318 if (ucontrol->value.integer.value[0] ==
319 ((reg2 & WM9081_SPK_MODE) != 0))
320 return 0;
321
322 /* Don't try to change modes while enabled */
323 if (reg_pwr & WM9081_SPK_ENA)
324 return -EINVAL;
325
326 if (ucontrol->value.integer.value[0]) {
327 /* Class AB */
328 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
329 reg2 |= WM9081_SPK_MODE;
330 } else {
331 /* Class D */
332 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
333 reg2 &= ~WM9081_SPK_MODE;
334 }
335
8d50e447 336 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
86ed3669
MB		 337
338 return 0;
339}
340
341static const struct snd_kcontrol_new wm9081_snd_controls[] = {
342SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
343SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
344
345SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
346
347SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
348SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
349SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
350
351SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
352SOC_ENUM("DRC High Slope", drc_high),
353SOC_ENUM("DRC Low Slope", drc_low),
354SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
355SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
356SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
357SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
358SOC_ENUM("DRC Attack", drc_atk),
359SOC_ENUM("DRC Decay", drc_dcy),
360SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
361SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
362SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
363SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
364
365SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
366
367SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
368SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
369SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
370SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
371SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
372 out_tlv),
373SOC_ENUM("DAC Deemphasis", dac_deemph),
374SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
375};
376
377static const struct snd_kcontrol_new wm9081_eq_controls[] = {
378SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
379SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
380SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
381SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
382SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
383};
384
385static const struct snd_kcontrol_new mixer[] = {
386SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
387SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
388SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
389};
390
391static int speaker_event(struct snd_soc_dapm_widget *w,
392 struct snd_kcontrol *kcontrol, int event)
393{
394 struct snd_soc_codec *codec = w->codec;
8d50e447 395 unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
86ed3669
MB		 396
397 switch (event) {
398 case SND_SOC_DAPM_POST_PMU:
399 reg |= WM9081_SPK_ENA;
400 break;
401
402 case SND_SOC_DAPM_PRE_PMD:
403 reg &= ~WM9081_SPK_ENA;
404 break;
405 }
406
8d50e447 407 snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
86ed3669
MB		 408
409 return 0;
410}
411
412struct _fll_div {
413 u16 fll_fratio;
414 u16 fll_outdiv;
415 u16 fll_clk_ref_div;
416 u16 n;
417 u16 k;
418};
419
420/* The size in bits of the FLL divide multiplied by 10
421 * to allow rounding later */
422#define FIXED_FLL_SIZE ((1 << 16) * 10)
423
424static struct {
425 unsigned int min;
426 unsigned int max;
427 u16 fll_fratio;
428 int ratio;
429} fll_fratios[] = {
430 { 0, 64000, 4, 16 },
431 { 64000, 128000, 3, 8 },
432 { 128000, 256000, 2, 4 },
433 { 256000, 1000000, 1, 2 },
434 { 1000000, 13500000, 0, 1 },
435};
436
437static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
438 unsigned int Fout)
439{
440 u64 Kpart;
441 unsigned int K, Ndiv, Nmod, target;
442 unsigned int div;
443 int i;
444
445 /* Fref must be <=13.5MHz */
446 div = 1;
447 while ((Fref / div) > 13500000) {
448 div *= 2;
449
450 if (div > 8) {
451 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
452 Fref);
453 return -EINVAL;
454 }
455 }
456 fll_div->fll_clk_ref_div = div / 2;
457
458 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
459
460 /* Apply the division for our remaining calculations */
461 Fref /= div;
462
463 /* Fvco should be 90-100MHz; don't check the upper bound */
464 div = 0;
465 target = Fout * 2;
466 while (target < 90000000) {
467 div++;
468 target *= 2;
469 if (div > 7) {
470 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
471 Fout);
472 return -EINVAL;
473 }
474 }
475 fll_div->fll_outdiv = div;
476
477 pr_debug("Fvco=%dHz\n", target);
478
479 /* Find an appropraite FLL_FRATIO and factor it out of the target */
480 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
481 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
482 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
483 target /= fll_fratios[i].ratio;
484 break;
485 }
486 }
487 if (i == ARRAY_SIZE(fll_fratios)) {
488 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
489 return -EINVAL;
490 }
491
492 /* Now, calculate N.K */
493 Ndiv = target / Fref;
494
495 fll_div->n = Ndiv;
496 Nmod = target % Fref;
497 pr_debug("Nmod=%d\n", Nmod);
498
499 /* Calculate fractional part - scale up so we can round. */
500 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
501
502 do_div(Kpart, Fref);
503
504 K = Kpart & 0xFFFFFFFF;
505
506 if ((K % 10) >= 5)
507 K += 5;
508
509 /* Move down to proper range now rounding is done */
510 fll_div->k = K / 10;
511
512 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
513 fll_div->n, fll_div->k,
514 fll_div->fll_fratio, fll_div->fll_outdiv,
515 fll_div->fll_clk_ref_div);
516
517 return 0;
518}
519
520static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
521 unsigned int Fref, unsigned int Fout)
522{
b2c812e2 523 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 524 u16 reg1, reg4, reg5;
525 struct _fll_div fll_div;
526 int ret;
527 int clk_sys_reg;
528
529 /* Any change? */
530 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
531 return 0;
532
533 /* Disable the FLL */
534 if (Fout == 0) {
535 dev_dbg(codec->dev, "FLL disabled\n");
536 wm9081->fll_fref = 0;
537 wm9081->fll_fout = 0;
538
539 return 0;
540 }
541
542 ret = fll_factors(&fll_div, Fref, Fout);
543 if (ret != 0)
544 return ret;
545
8d50e447 546 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
86ed3669
MB		 547 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
548
549 switch (fll_id) {
550 case WM9081_SYSCLK_FLL_MCLK:
551 reg5 |= 0x1;
552 break;
553
554 default:
555 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
556 return -EINVAL;
557 }
558
559 /* Disable CLK_SYS while we reconfigure */
8d50e447 560 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669 561 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 562 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
86ed3669
MB		 563 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
564
565 /* Any FLL configuration change requires that the FLL be
566 * disabled first. */
8d50e447 567 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
86ed3669 568 reg1 &= ~WM9081_FLL_ENA;
8d50e447 569 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669
MB		 570
571 /* Apply the configuration */
572 if (fll_div.k)
573 reg1 |= WM9081_FLL_FRAC_MASK;
574 else
575 reg1 &= ~WM9081_FLL_FRAC_MASK;
8d50e447 576 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669 577
8d50e447 578 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
86ed3669
MB		 579 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
580 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
8d50e447 581 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
86ed3669 582
8d50e447 583 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
86ed3669
MB		 584 reg4 &= ~WM9081_FLL_N_MASK;
585 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
8d50e447 586 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
86ed3669
MB		 587
588 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
589 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
8d50e447 590 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
86ed3669 591
249c5156
MB		 592 /* Set gain to the recommended value */
593 snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
594 WM9081_FLL_GAIN_MASK, 0);
595
86ed3669 596 /* Enable the FLL */
8d50e447 597 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
86ed3669
MB		 598
599 /* Then bring CLK_SYS up again if it was disabled */
600 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 601 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
86ed3669
MB		 602
603 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
604
605 wm9081->fll_fref = Fref;
606 wm9081->fll_fout = Fout;
607
608 return 0;
609}
610
611static int configure_clock(struct snd_soc_codec *codec)
612{
b2c812e2 613 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 614 int new_sysclk, i, target;
615 unsigned int reg;
616 int ret = 0;
617 int mclkdiv = 0;
618 int fll = 0;
619
620 switch (wm9081->sysclk_source) {
621 case WM9081_SYSCLK_MCLK:
622 if (wm9081->mclk_rate > 12225000) {
623 mclkdiv = 1;
624 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
625 } else {
626 wm9081->sysclk_rate = wm9081->mclk_rate;
627 }
628 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
629 break;
630
631 case WM9081_SYSCLK_FLL_MCLK:
632 /* If we have a sample rate calculate a CLK_SYS that
633 * gives us a suitable DAC configuration, plus BCLK.
634 * Ideally we would check to see if we can clock
635 * directly from MCLK and only use the FLL if this is
636 * not the case, though care must be taken with free
637 * running mode.
638 */
639 if (wm9081->master && wm9081->bclk) {
640 /* Make sure we can generate CLK_SYS and BCLK
641 * and that we've got 3MHz for optimal
642 * performance. */
643 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
644 target = wm9081->fs * clk_sys_rates[i].ratio;
0154724d 645 new_sysclk = target;
86ed3669
MB		 646 if (target >= wm9081->bclk &&
647 target > 3000000)
0154724d 648 break;
86ed3669 649 }
4b75e947
MB		 650
651 if (i == ARRAY_SIZE(clk_sys_rates))
652 return -EINVAL;
653
86ed3669
MB		 654 } else if (wm9081->fs) {
655 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
656 new_sysclk = clk_sys_rates[i].ratio
657 * wm9081->fs;
658 if (new_sysclk > 3000000)
659 break;
660 }
4b75e947
MB		 661
662 if (i == ARRAY_SIZE(clk_sys_rates))
663 return -EINVAL;
664
86ed3669
MB		 665 } else {
666 new_sysclk = 12288000;
667 }
668
669 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
670 wm9081->mclk_rate, new_sysclk);
671 if (ret == 0) {
672 wm9081->sysclk_rate = new_sysclk;
673
674 /* Switch SYSCLK over to FLL */
675 fll = 1;
676 } else {
677 wm9081->sysclk_rate = wm9081->mclk_rate;
678 }
679 break;
680
681 default:
682 return -EINVAL;
683 }
684
8d50e447 685 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
86ed3669
MB		 686 if (mclkdiv)
687 reg |= WM9081_MCLKDIV2;
688 else
689 reg &= ~WM9081_MCLKDIV2;
8d50e447 690 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
86ed3669 691
8d50e447 692 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669
MB		 693 if (fll)
694 reg |= WM9081_CLK_SRC_SEL;
695 else
696 reg &= ~WM9081_CLK_SRC_SEL;
8d50e447 697 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
86ed3669
MB		 698
699 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
700
701 return ret;
702}
703
704static int clk_sys_event(struct snd_soc_dapm_widget *w,
705 struct snd_kcontrol *kcontrol, int event)
706{
707 struct snd_soc_codec *codec = w->codec;
b2c812e2 708 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 709
710 /* This should be done on init() for bypass paths */
711 switch (wm9081->sysclk_source) {
712 case WM9081_SYSCLK_MCLK:
713 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
714 break;
715 case WM9081_SYSCLK_FLL_MCLK:
716 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
717 wm9081->mclk_rate);
718 break;
719 default:
720 dev_err(codec->dev, "System clock not configured\n");
721 return -EINVAL;
722 }
723
724 switch (event) {
725 case SND_SOC_DAPM_PRE_PMU:
726 configure_clock(codec);
727 break;
728
729 case SND_SOC_DAPM_POST_PMD:
730 /* Disable the FLL if it's running */
731 wm9081_set_fll(codec, 0, 0, 0);
732 break;
733 }
734
735 return 0;
736}
737
738static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
739SND_SOC_DAPM_INPUT("IN1"),
740SND_SOC_DAPM_INPUT("IN2"),
741
742SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
743
744SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
745 mixer, ARRAY_SIZE(mixer)),
746
747SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
748
749SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0,
750 speaker_event,
751 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
752
753SND_SOC_DAPM_OUTPUT("LINEOUT"),
754SND_SOC_DAPM_OUTPUT("SPKN"),
755SND_SOC_DAPM_OUTPUT("SPKP"),
756
757SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
758 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
759SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
760SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
761};
762
763
764static const struct snd_soc_dapm_route audio_paths[] = {
765 { "DAC", NULL, "CLK_SYS" },
766 { "DAC", NULL, "CLK_DSP" },
767
768 { "Mixer", "IN1 Switch", "IN1" },
769 { "Mixer", "IN2 Switch", "IN2" },
770 { "Mixer", "Playback Switch", "DAC" },
771
772 { "LINEOUT PGA", NULL, "Mixer" },
773 { "LINEOUT PGA", NULL, "TOCLK" },
774 { "LINEOUT PGA", NULL, "CLK_SYS" },
775
776 { "LINEOUT", NULL, "LINEOUT PGA" },
777
778 { "Speaker PGA", NULL, "Mixer" },
779 { "Speaker PGA", NULL, "TOCLK" },
780 { "Speaker PGA", NULL, "CLK_SYS" },
781
782 { "SPKN", NULL, "Speaker PGA" },
783 { "SPKP", NULL, "Speaker PGA" },
784};
785
786static int wm9081_set_bias_level(struct snd_soc_codec *codec,
787 enum snd_soc_bias_level level)
788{
789 u16 reg;
790
791 switch (level) {
792 case SND_SOC_BIAS_ON:
793 break;
794
795 case SND_SOC_BIAS_PREPARE:
796 /* VMID=2*40k */
8d50e447 797 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669
MB		 798 reg &= ~WM9081_VMID_SEL_MASK;
799 reg |= 0x2;
8d50e447 800 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 801
802 /* Normal bias current */
8d50e447 803 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 804 reg &= ~WM9081_STBY_BIAS_ENA;
8d50e447 805 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 806 break;
807
808 case SND_SOC_BIAS_STANDBY:
809 /* Initial cold start */
ce6120cc 810 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
86ed3669 811 /* Disable LINEOUT discharge */
8d50e447 812 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
86ed3669 813 reg &= ~WM9081_LINEOUT_DISCH;
8d50e447 814 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
86ed3669
MB		 815
816 /* Select startup bias source */
8d50e447 817 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 818 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
8d50e447 819 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 820
821 /* VMID 2*4k; Soft VMID ramp enable */
8d50e447 822 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669 823 reg |= WM9081_VMID_RAMP | 0x6;
8d50e447 824 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 825
826 mdelay(100);
827
828 /* Normal bias enable & soft start off */
829 reg |= WM9081_BIAS_ENA;
830 reg &= ~WM9081_VMID_RAMP;
8d50e447 831 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 832
833 /* Standard bias source */
8d50e447 834 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 835 reg &= ~WM9081_BIAS_SRC;
8d50e447 836 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 837 }
838
839 /* VMID 2*240k */
8d50e447 840 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669
MB		 841 reg &= ~WM9081_VMID_SEL_MASK;
842 reg |= 0x40;
8d50e447 843 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 844
845 /* Standby bias current on */
8d50e447 846 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 847 reg |= WM9081_STBY_BIAS_ENA;
8d50e447 848 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 849 break;
850
851 case SND_SOC_BIAS_OFF:
852 /* Startup bias source */
8d50e447 853 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 854 reg |= WM9081_BIAS_SRC;
8d50e447 855 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 856
857 /* Disable VMID and biases with soft ramping */
8d50e447 858 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669
MB		 859 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
860 reg |= WM9081_VMID_RAMP;
8d50e447 861 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 862
863 /* Actively discharge LINEOUT */
8d50e447 864 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
86ed3669 865 reg |= WM9081_LINEOUT_DISCH;
8d50e447 866 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
86ed3669
MB		 867 break;
868 }
869
ce6120cc 870 codec->dapm.bias_level = level;
86ed3669
MB		 871
872 return 0;
873}
874
875static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
876 unsigned int fmt)
877{
878 struct snd_soc_codec *codec = dai->codec;
b2c812e2 879 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 880 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 881
882 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
883 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
884
885 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
886 case SND_SOC_DAIFMT_CBS_CFS:
887 wm9081->master = 0;
888 break;
889 case SND_SOC_DAIFMT_CBS_CFM:
890 aif2 |= WM9081_LRCLK_DIR;
891 wm9081->master = 1;
892 break;
893 case SND_SOC_DAIFMT_CBM_CFS:
894 aif2 |= WM9081_BCLK_DIR;
895 wm9081->master = 1;
896 break;
897 case SND_SOC_DAIFMT_CBM_CFM:
898 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
899 wm9081->master = 1;
900 break;
901 default:
902 return -EINVAL;
903 }
904
905 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
906 case SND_SOC_DAIFMT_DSP_B:
907 aif2 |= WM9081_AIF_LRCLK_INV;
908 case SND_SOC_DAIFMT_DSP_A:
909 aif2 |= 0x3;
910 break;
911 case SND_SOC_DAIFMT_I2S:
912 aif2 |= 0x2;
913 break;
914 case SND_SOC_DAIFMT_RIGHT_J:
915 break;
916 case SND_SOC_DAIFMT_LEFT_J:
917 aif2 |= 0x1;
918 break;
919 default:
920 return -EINVAL;
921 }
922
923 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
924 case SND_SOC_DAIFMT_DSP_A:
925 case SND_SOC_DAIFMT_DSP_B:
926 /* frame inversion not valid for DSP modes */
927 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
928 case SND_SOC_DAIFMT_NB_NF:
929 break;
930 case SND_SOC_DAIFMT_IB_NF:
931 aif2 |= WM9081_AIF_BCLK_INV;
932 break;
933 default:
934 return -EINVAL;
935 }
936 break;
937
938 case SND_SOC_DAIFMT_I2S:
939 case SND_SOC_DAIFMT_RIGHT_J:
940 case SND_SOC_DAIFMT_LEFT_J:
941 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
942 case SND_SOC_DAIFMT_NB_NF:
943 break;
944 case SND_SOC_DAIFMT_IB_IF:
945 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
946 break;
947 case SND_SOC_DAIFMT_IB_NF:
948 aif2 |= WM9081_AIF_BCLK_INV;
949 break;
950 case SND_SOC_DAIFMT_NB_IF:
951 aif2 |= WM9081_AIF_LRCLK_INV;
952 break;
953 default:
954 return -EINVAL;
955 }
956 break;
957 default:
958 return -EINVAL;
959 }
960
8d50e447 961 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
86ed3669
MB		 962
963 return 0;
964}
965
966static int wm9081_hw_params(struct snd_pcm_substream *substream,
967 struct snd_pcm_hw_params *params,
968 struct snd_soc_dai *dai)
969{
970 struct snd_soc_codec *codec = dai->codec;
b2c812e2 971 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 972 int ret, i, best, best_val, cur_val;
973 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
974
8d50e447 975 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
86ed3669
MB		 976 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
977
8d50e447 978 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669 979
8d50e447 980 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 981 aif2 &= ~WM9081_AIF_WL_MASK;
982
8d50e447 983 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
86ed3669
MB		 984 aif3 &= ~WM9081_BCLK_DIV_MASK;
985
8d50e447 986 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
86ed3669
MB		 987 aif4 &= ~WM9081_LRCLK_RATE_MASK;
988
86ed3669 989 wm9081->fs = params_rate(params);
86ed3669 990
e0026bea
MB		 991 if (wm9081->tdm_width) {
992 /* If TDM is set up then that fixes our BCLK. */
86ed3669
MB		 993 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
994 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
e0026bea
MB		 995
996 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
997 } else {
998 /* Otherwise work out a BCLK from the sample size */
999 wm9081->bclk = 2 * wm9081->fs;
1000
1001 switch (params_format(params)) {
1002 case SNDRV_PCM_FORMAT_S16_LE:
1003 wm9081->bclk *= 16;
1004 break;
1005 case SNDRV_PCM_FORMAT_S20_3LE:
1006 wm9081->bclk *= 20;
1007 aif2 |= 0x4;
1008 break;
1009 case SNDRV_PCM_FORMAT_S24_LE:
1010 wm9081->bclk *= 24;
1011 aif2 |= 0x8;
1012 break;
1013 case SNDRV_PCM_FORMAT_S32_LE:
1014 wm9081->bclk *= 32;
1015 aif2 |= 0xc;
1016 break;
1017 default:
1018 return -EINVAL;
1019 }
86ed3669
MB		 1020 }
1021
1022 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1023
1024 ret = configure_clock(codec);
1025 if (ret != 0)
1026 return ret;
1027
1028 /* Select nearest CLK_SYS_RATE */
1029 best = 0;
1030 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1031 - wm9081->fs);
1032 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1033 cur_val = abs((wm9081->sysclk_rate /
a419aef8 1034 clk_sys_rates[i].ratio) - wm9081->fs);
86ed3669
MB		 1035 if (cur_val < best_val) {
1036 best = i;
1037 best_val = cur_val;
1038 }
1039 }
1040 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1041 clk_sys_rates[best].ratio);
1042 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1043 << WM9081_CLK_SYS_RATE_SHIFT);
1044
1045 /* SAMPLE_RATE */
1046 best = 0;
1047 best_val = abs(wm9081->fs - sample_rates[0].rate);
1048 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1049 /* Closest match */
1050 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1051 if (cur_val < best_val) {
1052 best = i;
1053 best_val = cur_val;
1054 }
1055 }
1056 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1057 sample_rates[best].rate);
0154724d
MB		 1058 clk_ctrl2 |= (sample_rates[best].sample_rate
1059 << WM9081_SAMPLE_RATE_SHIFT);
86ed3669
MB		 1060
1061 /* BCLK_DIV */
1062 best = 0;
1063 best_val = INT_MAX;
1064 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1065 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1066 - wm9081->bclk;
1067 if (cur_val < 0) /* Table is sorted */
1068 break;
1069 if (cur_val < best_val) {
1070 best = i;
1071 best_val = cur_val;
1072 }
1073 }
1074 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1075 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1076 bclk_divs[best].div, wm9081->bclk);
1077 aif3 |= bclk_divs[best].bclk_div;
1078
1079 /* LRCLK is a simple fraction of BCLK */
1080 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1081 aif4 |= wm9081->bclk / wm9081->fs;
1082
1083 /* Apply a ReTune Mobile configuration if it's in use */
1084 if (wm9081->retune) {
1085 struct wm9081_retune_mobile_config *retune = wm9081->retune;
1086 struct wm9081_retune_mobile_setting *s;
1087 int eq1;
1088
1089 best = 0;
1090 best_val = abs(retune->configs[0].rate - wm9081->fs);
1091 for (i = 0; i < retune->num_configs; i++) {
1092 cur_val = abs(retune->configs[i].rate - wm9081->fs);
1093 if (cur_val < best_val) {
1094 best_val = cur_val;
1095 best = i;
1096 }
1097 }
1098 s = &retune->configs[best];
1099
1100 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1101 s->name, s->rate);
1102
1103 /* If the EQ is enabled then disable it while we write out */
8d50e447 1104 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
86ed3669 1105 if (eq1 & WM9081_EQ_ENA)
8d50e447 1106 snd_soc_write(codec, WM9081_EQ_1, 0);
86ed3669
MB		 1107
1108 /* Write out the other values */
1109 for (i = 1; i < ARRAY_SIZE(s->config); i++)
8d50e447 1110 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
86ed3669
MB		 1111
1112 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
8d50e447 1113 snd_soc_write(codec, WM9081_EQ_1, eq1);
86ed3669
MB		 1114 }
1115
8d50e447
MB		 1116 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1117 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1118 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1119 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
86ed3669
MB		 1120
1121 return 0;
1122}
1123
1124static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1125{
1126 struct snd_soc_codec *codec = codec_dai->codec;
1127 unsigned int reg;
1128
8d50e447 1129 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
86ed3669
MB		 1130
1131 if (mute)
1132 reg |= WM9081_DAC_MUTE;
1133 else
1134 reg &= ~WM9081_DAC_MUTE;
1135
8d50e447 1136 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
86ed3669
MB		 1137
1138 return 0;
1139}
1140
1141static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai,
1142 int clk_id, unsigned int freq, int dir)
1143{
1144 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1145 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 1146
1147 switch (clk_id) {
1148 case WM9081_SYSCLK_MCLK:
1149 case WM9081_SYSCLK_FLL_MCLK:
1150 wm9081->sysclk_source = clk_id;
1151 wm9081->mclk_rate = freq;
1152 break;
1153
1154 default:
1155 return -EINVAL;
1156 }
1157
1158 return 0;
1159}
1160
1161static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
a5479e38 1162 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
86ed3669
MB		 1163{
1164 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1165 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 1166 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669
MB		 1167
1168 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1169
e0026bea 1170 if (slots < 0 || slots > 4)
86ed3669
MB		 1171 return -EINVAL;
1172
e0026bea
MB		 1173 wm9081->tdm_width = slot_width;
1174
1175 if (slots == 0)
1176 slots = 1;
1177
86ed3669
MB		 1178 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1179
a5479e38 1180 switch (rx_mask) {
86ed3669
MB		 1181 case 1:
1182 break;
1183 case 2:
1184 aif1 |= 0x10;
1185 break;
1186 case 4:
1187 aif1 |= 0x20;
1188 break;
1189 case 8:
1190 aif1 |= 0x30;
1191 break;
1192 default:
1193 return -EINVAL;
1194 }
1195
8d50e447 1196 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
86ed3669
MB		 1197
1198 return 0;
1199}
1200
1201#define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1202
1203#define WM9081_FORMATS \
1204 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1205 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1206
1207static struct snd_soc_dai_ops wm9081_dai_ops = {
1208 .hw_params = wm9081_hw_params,
1209 .set_sysclk = wm9081_set_sysclk,
1210 .set_fmt = wm9081_set_dai_fmt,
1211 .digital_mute = wm9081_digital_mute,
1212 .set_tdm_slot = wm9081_set_tdm_slot,
1213};
1214
1215/* We report two channels because the CODEC processes a stereo signal, even
1216 * though it is only capable of handling a mono output.
1217 */
f0fba2ad
LG		 1218static struct snd_soc_dai_driver wm9081_dai = {
1219 .name = "wm9081-hifi",
86ed3669
MB		 1220 .playback = {
1221 .stream_name = "HiFi Playback",
1222 .channels_min = 1,
1223 .channels_max = 2,
1224 .rates = WM9081_RATES,
1225 .formats = WM9081_FORMATS,
1226 },
1227 .ops = &wm9081_dai_ops,
1228};
86ed3669 1229
f0fba2ad 1230static int wm9081_probe(struct snd_soc_codec *codec)
86ed3669 1231{
f0fba2ad 1232 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
ce6120cc 1233 struct snd_soc_dapm_context *dapm = &codec->dapm;
f0fba2ad
LG		 1234 int ret;
1235 u16 reg;
86ed3669 1236
f0fba2ad
LG		 1237 codec->control_data = wm9081->control_data;
1238 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm9081->control_type);
1239 if (ret != 0) {
1240 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1241 return ret;
86ed3669
MB		 1242 }
1243
f0fba2ad
LG		 1244 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1245 if (reg != 0x9081) {
1246 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1247 ret = -EINVAL;
1248 return ret;
1249 }
86ed3669 1250
f0fba2ad 1251 ret = wm9081_reset(codec);
86ed3669 1252 if (ret < 0) {
f0fba2ad
LG		 1253 dev_err(codec->dev, "Failed to issue reset\n");
1254 return ret;
86ed3669
MB		 1255 }
1256
f0fba2ad
LG		 1257 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1258
1259 /* Enable zero cross by default */
1260 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1261 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1262 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1263 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1264 reg | WM9081_SPKPGAZC);
1265
86ed3669
MB		 1266 snd_soc_add_controls(codec, wm9081_snd_controls,
1267 ARRAY_SIZE(wm9081_snd_controls));
1268 if (!wm9081->retune) {
1269 dev_dbg(codec->dev,
1270 "No ReTune Mobile data, using normal EQ\n");
1271 snd_soc_add_controls(codec, wm9081_eq_controls,
1272 ARRAY_SIZE(wm9081_eq_controls));
1273 }
1274
ce6120cc 1275 snd_soc_dapm_new_controls(dapm, wm9081_dapm_widgets,
86ed3669 1276 ARRAY_SIZE(wm9081_dapm_widgets));
ce6120cc 1277 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
86ed3669 1278
86ed3669 1279 return ret;
86ed3669
MB		 1280}
1281
f0fba2ad 1282static int wm9081_remove(struct snd_soc_codec *codec)
86ed3669 1283{
f0fba2ad 1284 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
86ed3669
MB		 1285 return 0;
1286}
1287
1288#ifdef CONFIG_PM
f0fba2ad 1289static int wm9081_suspend(struct snd_soc_codec *codec, pm_message_t state)
86ed3669 1290{
86ed3669
MB		 1291 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1292
1293 return 0;
1294}
1295
f0fba2ad 1296static int wm9081_resume(struct snd_soc_codec *codec)
86ed3669 1297{
86ed3669
MB		 1298 u16 *reg_cache = codec->reg_cache;
1299 int i;
1300
f0fba2ad 1301 for (i = 0; i < codec->driver->reg_cache_size; i++) {
86ed3669
MB		 1302 if (i == WM9081_SOFTWARE_RESET)
1303 continue;
1304
8d50e447 1305 snd_soc_write(codec, i, reg_cache[i]);
86ed3669
MB		 1306 }
1307
1308 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1309
1310 return 0;
1311}
1312#else
1313#define wm9081_suspend NULL
1314#define wm9081_resume NULL
1315#endif
1316
f0fba2ad 1317static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
86ed3669
MB		 1318 .probe = wm9081_probe,
1319 .remove = wm9081_remove,
1320 .suspend = wm9081_suspend,
1321 .resume = wm9081_resume,
f0fba2ad 1322 .set_bias_level = wm9081_set_bias_level,
e5eec34c 1323 .reg_cache_size = ARRAY_SIZE(wm9081_reg_defaults),
f0fba2ad
LG		 1324 .reg_word_size = sizeof(u16),
1325 .reg_cache_default = wm9081_reg_defaults,
1326 .volatile_register = wm9081_volatile_register,
86ed3669 1327};
86ed3669 1328
f0fba2ad 1329#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669
MB		 1330static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1331 const struct i2c_device_id *id)
1332{
1333 struct wm9081_priv *wm9081;
f0fba2ad 1334 int ret;
86ed3669
MB		 1335
1336 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1337 if (wm9081 == NULL)
1338 return -ENOMEM;
1339
86ed3669 1340 i2c_set_clientdata(i2c, wm9081);
7f984b55 1341 wm9081->control_type = SND_SOC_I2C;
f0fba2ad 1342 wm9081->control_data = i2c;
86ed3669 1343
f0fba2ad
LG		 1344 ret = snd_soc_register_codec(&i2c->dev,
1345 &soc_codec_dev_wm9081, &wm9081_dai, 1);
1346 if (ret < 0)
1347 kfree(wm9081);
1348 return ret;
86ed3669
MB		 1349}
1350
1351static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1352{
f0fba2ad
LG		 1353 snd_soc_unregister_codec(&client->dev);
1354 kfree(i2c_get_clientdata(client));
86ed3669
MB		 1355 return 0;
1356}
1357
1358static const struct i2c_device_id wm9081_i2c_id[] = {
1359 { "wm9081", 0 },
1360 { }
1361};
1362MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1363
1364static struct i2c_driver wm9081_i2c_driver = {
1365 .driver = {
f0fba2ad 1366 .name = "wm9081-codec",
86ed3669
MB		 1367 .owner = THIS_MODULE,
1368 },
1369 .probe = wm9081_i2c_probe,
1370 .remove = __devexit_p(wm9081_i2c_remove),
1371 .id_table = wm9081_i2c_id,
1372};
f0fba2ad 1373#endif
86ed3669
MB		 1374
1375static int __init wm9081_modinit(void)
1376{
f0fba2ad
LG		 1377 int ret = 0;
1378#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669
MB		 1379 ret = i2c_add_driver(&wm9081_i2c_driver);
1380 if (ret != 0) {
1381 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1382 ret);
1383 }
f0fba2ad 1384#endif
86ed3669
MB		 1385 return ret;
1386}
1387module_init(wm9081_modinit);
1388
1389static void __exit wm9081_exit(void)
1390{
f0fba2ad 1391#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669 1392 i2c_del_driver(&wm9081_i2c_driver);
f0fba2ad 1393#endif
86ed3669
MB		 1394}
1395module_exit(wm9081_exit);
1396
1397
1398MODULE_DESCRIPTION("ASoC WM9081 driver");
1399MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1400MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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