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ASoC: Remove module probe announcements from CODEC drivers
[deliverable/linux.git] / sound / soc / codecs / wm9081.c
CommitLineData
86ed3669
MB		 1/*
2 * wm9081.c -- WM9081 ALSA SoC Audio driver
3 *
4 * Author: Mark Brown
5 *
6 * Copyright 2009 Wolfson Microelectronics plc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
3ee845ac 18#include <linux/device.h>
86ed3669
MB		 19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
5a0e3ad6 22#include <linux/slab.h>
86ed3669
MB		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
86ed3669
MB		 27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include <sound/wm9081.h>
31#include "wm9081.h"
32
33static u16 wm9081_reg_defaults[] = {
34 0x0000, /* R0 - Software Reset */
35 0x0000, /* R1 */
36 0x00B9, /* R2 - Analogue Lineout */
37 0x00B9, /* R3 - Analogue Speaker PGA */
38 0x0001, /* R4 - VMID Control */
39 0x0068, /* R5 - Bias Control 1 */
40 0x0000, /* R6 */
41 0x0000, /* R7 - Analogue Mixer */
42 0x0000, /* R8 - Anti Pop Control */
43 0x01DB, /* R9 - Analogue Speaker 1 */
44 0x0018, /* R10 - Analogue Speaker 2 */
45 0x0180, /* R11 - Power Management */
46 0x0000, /* R12 - Clock Control 1 */
47 0x0038, /* R13 - Clock Control 2 */
48 0x4000, /* R14 - Clock Control 3 */
49 0x0000, /* R15 */
50 0x0000, /* R16 - FLL Control 1 */
51 0x0200, /* R17 - FLL Control 2 */
52 0x0000, /* R18 - FLL Control 3 */
53 0x0204, /* R19 - FLL Control 4 */
54 0x0000, /* R20 - FLL Control 5 */
55 0x0000, /* R21 */
56 0x0000, /* R22 - Audio Interface 1 */
57 0x0002, /* R23 - Audio Interface 2 */
58 0x0008, /* R24 - Audio Interface 3 */
59 0x0022, /* R25 - Audio Interface 4 */
60 0x0000, /* R26 - Interrupt Status */
61 0x0006, /* R27 - Interrupt Status Mask */
62 0x0000, /* R28 - Interrupt Polarity */
63 0x0000, /* R29 - Interrupt Control */
64 0x00C0, /* R30 - DAC Digital 1 */
65 0x0008, /* R31 - DAC Digital 2 */
66 0x09AF, /* R32 - DRC 1 */
67 0x4201, /* R33 - DRC 2 */
68 0x0000, /* R34 - DRC 3 */
69 0x0000, /* R35 - DRC 4 */
70 0x0000, /* R36 */
71 0x0000, /* R37 */
72 0x0000, /* R38 - Write Sequencer 1 */
73 0x0000, /* R39 - Write Sequencer 2 */
74 0x0002, /* R40 - MW Slave 1 */
75 0x0000, /* R41 */
76 0x0000, /* R42 - EQ 1 */
77 0x0000, /* R43 - EQ 2 */
78 0x0FCA, /* R44 - EQ 3 */
79 0x0400, /* R45 - EQ 4 */
80 0x00B8, /* R46 - EQ 5 */
81 0x1EB5, /* R47 - EQ 6 */
82 0xF145, /* R48 - EQ 7 */
83 0x0B75, /* R49 - EQ 8 */
84 0x01C5, /* R50 - EQ 9 */
85 0x169E, /* R51 - EQ 10 */
86 0xF829, /* R52 - EQ 11 */
87 0x07AD, /* R53 - EQ 12 */
88 0x1103, /* R54 - EQ 13 */
89 0x1C58, /* R55 - EQ 14 */
90 0xF373, /* R56 - EQ 15 */
91 0x0A54, /* R57 - EQ 16 */
92 0x0558, /* R58 - EQ 17 */
93 0x0564, /* R59 - EQ 18 */
94 0x0559, /* R60 - EQ 19 */
95 0x4000, /* R61 - EQ 20 */
96};
97
98static struct {
99 int ratio;
100 int clk_sys_rate;
101} clk_sys_rates[] = {
102 { 64, 0 },
103 { 128, 1 },
104 { 192, 2 },
105 { 256, 3 },
106 { 384, 4 },
107 { 512, 5 },
108 { 768, 6 },
109 { 1024, 7 },
110 { 1408, 8 },
111 { 1536, 9 },
112};
113
114static struct {
115 int rate;
116 int sample_rate;
117} sample_rates[] = {
118 { 8000, 0 },
119 { 11025, 1 },
120 { 12000, 2 },
121 { 16000, 3 },
122 { 22050, 4 },
123 { 24000, 5 },
124 { 32000, 6 },
125 { 44100, 7 },
126 { 48000, 8 },
127 { 88200, 9 },
128 { 96000, 10 },
129};
130
131static struct {
132 int div; /* *10 due to .5s */
133 int bclk_div;
134} bclk_divs[] = {
135 { 10, 0 },
136 { 15, 1 },
137 { 20, 2 },
138 { 30, 3 },
139 { 40, 4 },
140 { 50, 5 },
141 { 55, 6 },
142 { 60, 7 },
143 { 80, 8 },
144 { 100, 9 },
145 { 110, 10 },
146 { 120, 11 },
147 { 160, 12 },
148 { 200, 13 },
149 { 220, 14 },
150 { 240, 15 },
151 { 250, 16 },
152 { 300, 17 },
153 { 320, 18 },
154 { 440, 19 },
155 { 480, 20 },
156};
157
158struct wm9081_priv {
f0fba2ad
LG		 159 enum snd_soc_control_type control_type;
160 void *control_data;
86ed3669
MB		 161 int sysclk_source;
162 int mclk_rate;
163 int sysclk_rate;
164 int fs;
165 int bclk;
166 int master;
167 int fll_fref;
168 int fll_fout;
e0026bea 169 int tdm_width;
86ed3669
MB		 170 struct wm9081_retune_mobile_config *retune;
171};
172
d4754ec9 173static int wm9081_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
86ed3669
MB		 174{
175 switch (reg) {
8d50e447
MB		 176 case WM9081_SOFTWARE_RESET:
177 return 1;
86ed3669
MB		 178 default:
179 return 0;
180 }
181}
182
86ed3669
MB		 183static int wm9081_reset(struct snd_soc_codec *codec)
184{
8d50e447 185 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
86ed3669
MB		 186}
187
188static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
189static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
190static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
191static unsigned int drc_max_tlv[] = {
192 TLV_DB_RANGE_HEAD(4),
193 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
194 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
195 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
196 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
197};
198static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
199static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
200
201static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
202
203static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
204static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
205static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
206
207static const char *drc_high_text[] = {
208 "1",
209 "1/2",
210 "1/4",
211 "1/8",
212 "1/16",
213 "0",
214};
215
216static const struct soc_enum drc_high =
217 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
218
219static const char *drc_low_text[] = {
220 "1",
221 "1/2",
222 "1/4",
223 "1/8",
224 "0",
225};
226
227static const struct soc_enum drc_low =
228 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
229
230static const char *drc_atk_text[] = {
231 "181us",
232 "181us",
233 "363us",
234 "726us",
235 "1.45ms",
236 "2.9ms",
237 "5.8ms",
238 "11.6ms",
239 "23.2ms",
240 "46.4ms",
241 "92.8ms",
242 "185.6ms",
243};
244
245static const struct soc_enum drc_atk =
246 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
247
248static const char *drc_dcy_text[] = {
249 "186ms",
250 "372ms",
251 "743ms",
252 "1.49s",
253 "2.97s",
254 "5.94s",
255 "11.89s",
256 "23.78s",
257 "47.56s",
258};
259
260static const struct soc_enum drc_dcy =
261 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
262
263static const char *drc_qr_dcy_text[] = {
264 "0.725ms",
265 "1.45ms",
266 "5.8ms",
267};
268
269static const struct soc_enum drc_qr_dcy =
270 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
271
272static const char *dac_deemph_text[] = {
273 "None",
274 "32kHz",
275 "44.1kHz",
276 "48kHz",
277};
278
279static const struct soc_enum dac_deemph =
280 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
281
282static const char *speaker_mode_text[] = {
283 "Class D",
284 "Class AB",
285};
286
287static const struct soc_enum speaker_mode =
288 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
289
290static int speaker_mode_get(struct snd_kcontrol *kcontrol,
291 struct snd_ctl_elem_value *ucontrol)
292{
293 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
294 unsigned int reg;
295
8d50e447 296 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 297 if (reg & WM9081_SPK_MODE)
298 ucontrol->value.integer.value[0] = 1;
299 else
300 ucontrol->value.integer.value[0] = 0;
301
302 return 0;
303}
304
305/*
306 * Stop any attempts to change speaker mode while the speaker is enabled.
307 *
308 * We also have some special anti-pop controls dependant on speaker
309 * mode which must be changed along with the mode.
310 */
311static int speaker_mode_put(struct snd_kcontrol *kcontrol,
312 struct snd_ctl_elem_value *ucontrol)
313{
314 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
8d50e447
MB		 315 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
316 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 317
318 /* Are we changing anything? */
319 if (ucontrol->value.integer.value[0] ==
320 ((reg2 & WM9081_SPK_MODE) != 0))
321 return 0;
322
323 /* Don't try to change modes while enabled */
324 if (reg_pwr & WM9081_SPK_ENA)
325 return -EINVAL;
326
327 if (ucontrol->value.integer.value[0]) {
328 /* Class AB */
329 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
330 reg2 |= WM9081_SPK_MODE;
331 } else {
332 /* Class D */
333 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
334 reg2 &= ~WM9081_SPK_MODE;
335 }
336
8d50e447 337 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
86ed3669
MB		 338
339 return 0;
340}
341
342static const struct snd_kcontrol_new wm9081_snd_controls[] = {
343SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
344SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
345
346SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
347
348SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
349SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
350SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
351
352SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
353SOC_ENUM("DRC High Slope", drc_high),
354SOC_ENUM("DRC Low Slope", drc_low),
355SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
356SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
357SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
358SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
359SOC_ENUM("DRC Attack", drc_atk),
360SOC_ENUM("DRC Decay", drc_dcy),
361SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
362SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
363SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
364SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
365
366SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
367
368SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
369SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
370SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
371SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
372SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
373 out_tlv),
374SOC_ENUM("DAC Deemphasis", dac_deemph),
375SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
376};
377
378static const struct snd_kcontrol_new wm9081_eq_controls[] = {
379SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
380SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
381SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
382SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
383SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
384};
385
386static const struct snd_kcontrol_new mixer[] = {
387SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
388SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
389SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
390};
391
392static int speaker_event(struct snd_soc_dapm_widget *w,
393 struct snd_kcontrol *kcontrol, int event)
394{
395 struct snd_soc_codec *codec = w->codec;
8d50e447 396 unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
86ed3669
MB		 397
398 switch (event) {
399 case SND_SOC_DAPM_POST_PMU:
400 reg |= WM9081_SPK_ENA;
401 break;
402
403 case SND_SOC_DAPM_PRE_PMD:
404 reg &= ~WM9081_SPK_ENA;
405 break;
406 }
407
8d50e447 408 snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
86ed3669
MB		 409
410 return 0;
411}
412
413struct _fll_div {
414 u16 fll_fratio;
415 u16 fll_outdiv;
416 u16 fll_clk_ref_div;
417 u16 n;
418 u16 k;
419};
420
421/* The size in bits of the FLL divide multiplied by 10
422 * to allow rounding later */
423#define FIXED_FLL_SIZE ((1 << 16) * 10)
424
425static struct {
426 unsigned int min;
427 unsigned int max;
428 u16 fll_fratio;
429 int ratio;
430} fll_fratios[] = {
431 { 0, 64000, 4, 16 },
432 { 64000, 128000, 3, 8 },
433 { 128000, 256000, 2, 4 },
434 { 256000, 1000000, 1, 2 },
435 { 1000000, 13500000, 0, 1 },
436};
437
438static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
439 unsigned int Fout)
440{
441 u64 Kpart;
442 unsigned int K, Ndiv, Nmod, target;
443 unsigned int div;
444 int i;
445
446 /* Fref must be <=13.5MHz */
447 div = 1;
448 while ((Fref / div) > 13500000) {
449 div *= 2;
450
451 if (div > 8) {
452 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
453 Fref);
454 return -EINVAL;
455 }
456 }
457 fll_div->fll_clk_ref_div = div / 2;
458
459 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
460
461 /* Apply the division for our remaining calculations */
462 Fref /= div;
463
464 /* Fvco should be 90-100MHz; don't check the upper bound */
465 div = 0;
466 target = Fout * 2;
467 while (target < 90000000) {
468 div++;
469 target *= 2;
470 if (div > 7) {
471 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
472 Fout);
473 return -EINVAL;
474 }
475 }
476 fll_div->fll_outdiv = div;
477
478 pr_debug("Fvco=%dHz\n", target);
479
480 /* Find an appropraite FLL_FRATIO and factor it out of the target */
481 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
482 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
483 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
484 target /= fll_fratios[i].ratio;
485 break;
486 }
487 }
488 if (i == ARRAY_SIZE(fll_fratios)) {
489 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
490 return -EINVAL;
491 }
492
493 /* Now, calculate N.K */
494 Ndiv = target / Fref;
495
496 fll_div->n = Ndiv;
497 Nmod = target % Fref;
498 pr_debug("Nmod=%d\n", Nmod);
499
500 /* Calculate fractional part - scale up so we can round. */
501 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
502
503 do_div(Kpart, Fref);
504
505 K = Kpart & 0xFFFFFFFF;
506
507 if ((K % 10) >= 5)
508 K += 5;
509
510 /* Move down to proper range now rounding is done */
511 fll_div->k = K / 10;
512
513 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
514 fll_div->n, fll_div->k,
515 fll_div->fll_fratio, fll_div->fll_outdiv,
516 fll_div->fll_clk_ref_div);
517
518 return 0;
519}
520
521static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
522 unsigned int Fref, unsigned int Fout)
523{
b2c812e2 524 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 525 u16 reg1, reg4, reg5;
526 struct _fll_div fll_div;
527 int ret;
528 int clk_sys_reg;
529
530 /* Any change? */
531 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
532 return 0;
533
534 /* Disable the FLL */
535 if (Fout == 0) {
536 dev_dbg(codec->dev, "FLL disabled\n");
537 wm9081->fll_fref = 0;
538 wm9081->fll_fout = 0;
539
540 return 0;
541 }
542
543 ret = fll_factors(&fll_div, Fref, Fout);
544 if (ret != 0)
545 return ret;
546
8d50e447 547 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
86ed3669
MB		 548 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
549
550 switch (fll_id) {
551 case WM9081_SYSCLK_FLL_MCLK:
552 reg5 |= 0x1;
553 break;
554
555 default:
556 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
557 return -EINVAL;
558 }
559
560 /* Disable CLK_SYS while we reconfigure */
8d50e447 561 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669 562 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 563 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
86ed3669
MB		 564 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
565
566 /* Any FLL configuration change requires that the FLL be
567 * disabled first. */
8d50e447 568 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
86ed3669 569 reg1 &= ~WM9081_FLL_ENA;
8d50e447 570 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669
MB		 571
572 /* Apply the configuration */
573 if (fll_div.k)
574 reg1 |= WM9081_FLL_FRAC_MASK;
575 else
576 reg1 &= ~WM9081_FLL_FRAC_MASK;
8d50e447 577 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669 578
8d50e447 579 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
86ed3669
MB		 580 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
581 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
8d50e447 582 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
86ed3669 583
8d50e447 584 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
86ed3669
MB		 585 reg4 &= ~WM9081_FLL_N_MASK;
586 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
8d50e447 587 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
86ed3669
MB		 588
589 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
590 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
8d50e447 591 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
86ed3669 592
249c5156
MB		 593 /* Set gain to the recommended value */
594 snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
595 WM9081_FLL_GAIN_MASK, 0);
596
86ed3669 597 /* Enable the FLL */
8d50e447 598 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
86ed3669
MB		 599
600 /* Then bring CLK_SYS up again if it was disabled */
601 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 602 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
86ed3669
MB		 603
604 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
605
606 wm9081->fll_fref = Fref;
607 wm9081->fll_fout = Fout;
608
609 return 0;
610}
611
612static int configure_clock(struct snd_soc_codec *codec)
613{
b2c812e2 614 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 615 int new_sysclk, i, target;
616 unsigned int reg;
617 int ret = 0;
618 int mclkdiv = 0;
619 int fll = 0;
620
621 switch (wm9081->sysclk_source) {
622 case WM9081_SYSCLK_MCLK:
623 if (wm9081->mclk_rate > 12225000) {
624 mclkdiv = 1;
625 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
626 } else {
627 wm9081->sysclk_rate = wm9081->mclk_rate;
628 }
629 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
630 break;
631
632 case WM9081_SYSCLK_FLL_MCLK:
633 /* If we have a sample rate calculate a CLK_SYS that
634 * gives us a suitable DAC configuration, plus BCLK.
635 * Ideally we would check to see if we can clock
636 * directly from MCLK and only use the FLL if this is
637 * not the case, though care must be taken with free
638 * running mode.
639 */
640 if (wm9081->master && wm9081->bclk) {
641 /* Make sure we can generate CLK_SYS and BCLK
642 * and that we've got 3MHz for optimal
643 * performance. */
644 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
645 target = wm9081->fs * clk_sys_rates[i].ratio;
0154724d 646 new_sysclk = target;
86ed3669
MB		 647 if (target >= wm9081->bclk &&
648 target > 3000000)
0154724d 649 break;
86ed3669 650 }
4b75e947
MB		 651
652 if (i == ARRAY_SIZE(clk_sys_rates))
653 return -EINVAL;
654
86ed3669
MB		 655 } else if (wm9081->fs) {
656 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
657 new_sysclk = clk_sys_rates[i].ratio
658 * wm9081->fs;
659 if (new_sysclk > 3000000)
660 break;
661 }
4b75e947
MB		 662
663 if (i == ARRAY_SIZE(clk_sys_rates))
664 return -EINVAL;
665
86ed3669
MB		 666 } else {
667 new_sysclk = 12288000;
668 }
669
670 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
671 wm9081->mclk_rate, new_sysclk);
672 if (ret == 0) {
673 wm9081->sysclk_rate = new_sysclk;
674
675 /* Switch SYSCLK over to FLL */
676 fll = 1;
677 } else {
678 wm9081->sysclk_rate = wm9081->mclk_rate;
679 }
680 break;
681
682 default:
683 return -EINVAL;
684 }
685
8d50e447 686 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
86ed3669
MB		 687 if (mclkdiv)
688 reg |= WM9081_MCLKDIV2;
689 else
690 reg &= ~WM9081_MCLKDIV2;
8d50e447 691 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
86ed3669 692
8d50e447 693 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669
MB		 694 if (fll)
695 reg |= WM9081_CLK_SRC_SEL;
696 else
697 reg &= ~WM9081_CLK_SRC_SEL;
8d50e447 698 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
86ed3669
MB		 699
700 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
701
702 return ret;
703}
704
705static int clk_sys_event(struct snd_soc_dapm_widget *w,
706 struct snd_kcontrol *kcontrol, int event)
707{
708 struct snd_soc_codec *codec = w->codec;
b2c812e2 709 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 710
711 /* This should be done on init() for bypass paths */
712 switch (wm9081->sysclk_source) {
713 case WM9081_SYSCLK_MCLK:
714 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
715 break;
716 case WM9081_SYSCLK_FLL_MCLK:
717 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
718 wm9081->mclk_rate);
719 break;
720 default:
721 dev_err(codec->dev, "System clock not configured\n");
722 return -EINVAL;
723 }
724
725 switch (event) {
726 case SND_SOC_DAPM_PRE_PMU:
727 configure_clock(codec);
728 break;
729
730 case SND_SOC_DAPM_POST_PMD:
731 /* Disable the FLL if it's running */
732 wm9081_set_fll(codec, 0, 0, 0);
733 break;
734 }
735
736 return 0;
737}
738
739static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
740SND_SOC_DAPM_INPUT("IN1"),
741SND_SOC_DAPM_INPUT("IN2"),
742
743SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
744
745SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
746 mixer, ARRAY_SIZE(mixer)),
747
748SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
749
750SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0,
751 speaker_event,
752 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
753
754SND_SOC_DAPM_OUTPUT("LINEOUT"),
755SND_SOC_DAPM_OUTPUT("SPKN"),
756SND_SOC_DAPM_OUTPUT("SPKP"),
757
758SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
760SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
761SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
762};
763
764
765static const struct snd_soc_dapm_route audio_paths[] = {
766 { "DAC", NULL, "CLK_SYS" },
767 { "DAC", NULL, "CLK_DSP" },
768
769 { "Mixer", "IN1 Switch", "IN1" },
770 { "Mixer", "IN2 Switch", "IN2" },
771 { "Mixer", "Playback Switch", "DAC" },
772
773 { "LINEOUT PGA", NULL, "Mixer" },
774 { "LINEOUT PGA", NULL, "TOCLK" },
775 { "LINEOUT PGA", NULL, "CLK_SYS" },
776
777 { "LINEOUT", NULL, "LINEOUT PGA" },
778
779 { "Speaker PGA", NULL, "Mixer" },
780 { "Speaker PGA", NULL, "TOCLK" },
781 { "Speaker PGA", NULL, "CLK_SYS" },
782
783 { "SPKN", NULL, "Speaker PGA" },
784 { "SPKP", NULL, "Speaker PGA" },
785};
786
787static int wm9081_set_bias_level(struct snd_soc_codec *codec,
788 enum snd_soc_bias_level level)
789{
790 u16 reg;
791
792 switch (level) {
793 case SND_SOC_BIAS_ON:
794 break;
795
796 case SND_SOC_BIAS_PREPARE:
797 /* VMID=2*40k */
8d50e447 798 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669
MB		 799 reg &= ~WM9081_VMID_SEL_MASK;
800 reg |= 0x2;
8d50e447 801 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 802
803 /* Normal bias current */
8d50e447 804 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 805 reg &= ~WM9081_STBY_BIAS_ENA;
8d50e447 806 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 807 break;
808
809 case SND_SOC_BIAS_STANDBY:
810 /* Initial cold start */
ce6120cc 811 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
86ed3669 812 /* Disable LINEOUT discharge */
8d50e447 813 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
86ed3669 814 reg &= ~WM9081_LINEOUT_DISCH;
8d50e447 815 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
86ed3669
MB		 816
817 /* Select startup bias source */
8d50e447 818 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 819 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
8d50e447 820 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 821
822 /* VMID 2*4k; Soft VMID ramp enable */
8d50e447 823 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669 824 reg |= WM9081_VMID_RAMP | 0x6;
8d50e447 825 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 826
827 mdelay(100);
828
829 /* Normal bias enable & soft start off */
830 reg |= WM9081_BIAS_ENA;
831 reg &= ~WM9081_VMID_RAMP;
8d50e447 832 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 833
834 /* Standard bias source */
8d50e447 835 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 836 reg &= ~WM9081_BIAS_SRC;
8d50e447 837 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 838 }
839
840 /* VMID 2*240k */
8d50e447 841 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669
MB		 842 reg &= ~WM9081_VMID_SEL_MASK;
843 reg |= 0x40;
8d50e447 844 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 845
846 /* Standby bias current on */
8d50e447 847 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 848 reg |= WM9081_STBY_BIAS_ENA;
8d50e447 849 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 850 break;
851
852 case SND_SOC_BIAS_OFF:
853 /* Startup bias source */
8d50e447 854 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 855 reg |= WM9081_BIAS_SRC;
8d50e447 856 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 857
858 /* Disable VMID and biases with soft ramping */
8d50e447 859 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669
MB		 860 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
861 reg |= WM9081_VMID_RAMP;
8d50e447 862 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 863
864 /* Actively discharge LINEOUT */
8d50e447 865 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
86ed3669 866 reg |= WM9081_LINEOUT_DISCH;
8d50e447 867 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
86ed3669
MB		 868 break;
869 }
870
ce6120cc 871 codec->dapm.bias_level = level;
86ed3669
MB		 872
873 return 0;
874}
875
876static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
877 unsigned int fmt)
878{
879 struct snd_soc_codec *codec = dai->codec;
b2c812e2 880 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 881 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 882
883 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
884 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
885
886 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
887 case SND_SOC_DAIFMT_CBS_CFS:
888 wm9081->master = 0;
889 break;
890 case SND_SOC_DAIFMT_CBS_CFM:
891 aif2 |= WM9081_LRCLK_DIR;
892 wm9081->master = 1;
893 break;
894 case SND_SOC_DAIFMT_CBM_CFS:
895 aif2 |= WM9081_BCLK_DIR;
896 wm9081->master = 1;
897 break;
898 case SND_SOC_DAIFMT_CBM_CFM:
899 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
900 wm9081->master = 1;
901 break;
902 default:
903 return -EINVAL;
904 }
905
906 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
907 case SND_SOC_DAIFMT_DSP_B:
908 aif2 |= WM9081_AIF_LRCLK_INV;
909 case SND_SOC_DAIFMT_DSP_A:
910 aif2 |= 0x3;
911 break;
912 case SND_SOC_DAIFMT_I2S:
913 aif2 |= 0x2;
914 break;
915 case SND_SOC_DAIFMT_RIGHT_J:
916 break;
917 case SND_SOC_DAIFMT_LEFT_J:
918 aif2 |= 0x1;
919 break;
920 default:
921 return -EINVAL;
922 }
923
924 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
925 case SND_SOC_DAIFMT_DSP_A:
926 case SND_SOC_DAIFMT_DSP_B:
927 /* frame inversion not valid for DSP modes */
928 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
929 case SND_SOC_DAIFMT_NB_NF:
930 break;
931 case SND_SOC_DAIFMT_IB_NF:
932 aif2 |= WM9081_AIF_BCLK_INV;
933 break;
934 default:
935 return -EINVAL;
936 }
937 break;
938
939 case SND_SOC_DAIFMT_I2S:
940 case SND_SOC_DAIFMT_RIGHT_J:
941 case SND_SOC_DAIFMT_LEFT_J:
942 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
943 case SND_SOC_DAIFMT_NB_NF:
944 break;
945 case SND_SOC_DAIFMT_IB_IF:
946 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
947 break;
948 case SND_SOC_DAIFMT_IB_NF:
949 aif2 |= WM9081_AIF_BCLK_INV;
950 break;
951 case SND_SOC_DAIFMT_NB_IF:
952 aif2 |= WM9081_AIF_LRCLK_INV;
953 break;
954 default:
955 return -EINVAL;
956 }
957 break;
958 default:
959 return -EINVAL;
960 }
961
8d50e447 962 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
86ed3669
MB		 963
964 return 0;
965}
966
967static int wm9081_hw_params(struct snd_pcm_substream *substream,
968 struct snd_pcm_hw_params *params,
969 struct snd_soc_dai *dai)
970{
971 struct snd_soc_codec *codec = dai->codec;
b2c812e2 972 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 973 int ret, i, best, best_val, cur_val;
974 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
975
8d50e447 976 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
86ed3669
MB		 977 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
978
8d50e447 979 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669 980
8d50e447 981 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 982 aif2 &= ~WM9081_AIF_WL_MASK;
983
8d50e447 984 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
86ed3669
MB		 985 aif3 &= ~WM9081_BCLK_DIV_MASK;
986
8d50e447 987 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
86ed3669
MB		 988 aif4 &= ~WM9081_LRCLK_RATE_MASK;
989
86ed3669 990 wm9081->fs = params_rate(params);
86ed3669 991
e0026bea
MB		 992 if (wm9081->tdm_width) {
993 /* If TDM is set up then that fixes our BCLK. */
86ed3669
MB		 994 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
995 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
e0026bea
MB		 996
997 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
998 } else {
999 /* Otherwise work out a BCLK from the sample size */
1000 wm9081->bclk = 2 * wm9081->fs;
1001
1002 switch (params_format(params)) {
1003 case SNDRV_PCM_FORMAT_S16_LE:
1004 wm9081->bclk *= 16;
1005 break;
1006 case SNDRV_PCM_FORMAT_S20_3LE:
1007 wm9081->bclk *= 20;
1008 aif2 |= 0x4;
1009 break;
1010 case SNDRV_PCM_FORMAT_S24_LE:
1011 wm9081->bclk *= 24;
1012 aif2 |= 0x8;
1013 break;
1014 case SNDRV_PCM_FORMAT_S32_LE:
1015 wm9081->bclk *= 32;
1016 aif2 |= 0xc;
1017 break;
1018 default:
1019 return -EINVAL;
1020 }
86ed3669
MB		 1021 }
1022
1023 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1024
1025 ret = configure_clock(codec);
1026 if (ret != 0)
1027 return ret;
1028
1029 /* Select nearest CLK_SYS_RATE */
1030 best = 0;
1031 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1032 - wm9081->fs);
1033 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1034 cur_val = abs((wm9081->sysclk_rate /
a419aef8 1035 clk_sys_rates[i].ratio) - wm9081->fs);
86ed3669
MB		 1036 if (cur_val < best_val) {
1037 best = i;
1038 best_val = cur_val;
1039 }
1040 }
1041 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1042 clk_sys_rates[best].ratio);
1043 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1044 << WM9081_CLK_SYS_RATE_SHIFT);
1045
1046 /* SAMPLE_RATE */
1047 best = 0;
1048 best_val = abs(wm9081->fs - sample_rates[0].rate);
1049 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1050 /* Closest match */
1051 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1052 if (cur_val < best_val) {
1053 best = i;
1054 best_val = cur_val;
1055 }
1056 }
1057 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1058 sample_rates[best].rate);
0154724d
MB		 1059 clk_ctrl2 |= (sample_rates[best].sample_rate
1060 << WM9081_SAMPLE_RATE_SHIFT);
86ed3669
MB		 1061
1062 /* BCLK_DIV */
1063 best = 0;
1064 best_val = INT_MAX;
1065 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1066 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1067 - wm9081->bclk;
1068 if (cur_val < 0) /* Table is sorted */
1069 break;
1070 if (cur_val < best_val) {
1071 best = i;
1072 best_val = cur_val;
1073 }
1074 }
1075 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1076 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1077 bclk_divs[best].div, wm9081->bclk);
1078 aif3 |= bclk_divs[best].bclk_div;
1079
1080 /* LRCLK is a simple fraction of BCLK */
1081 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1082 aif4 |= wm9081->bclk / wm9081->fs;
1083
1084 /* Apply a ReTune Mobile configuration if it's in use */
1085 if (wm9081->retune) {
1086 struct wm9081_retune_mobile_config *retune = wm9081->retune;
1087 struct wm9081_retune_mobile_setting *s;
1088 int eq1;
1089
1090 best = 0;
1091 best_val = abs(retune->configs[0].rate - wm9081->fs);
1092 for (i = 0; i < retune->num_configs; i++) {
1093 cur_val = abs(retune->configs[i].rate - wm9081->fs);
1094 if (cur_val < best_val) {
1095 best_val = cur_val;
1096 best = i;
1097 }
1098 }
1099 s = &retune->configs[best];
1100
1101 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1102 s->name, s->rate);
1103
1104 /* If the EQ is enabled then disable it while we write out */
8d50e447 1105 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
86ed3669 1106 if (eq1 & WM9081_EQ_ENA)
8d50e447 1107 snd_soc_write(codec, WM9081_EQ_1, 0);
86ed3669
MB		 1108
1109 /* Write out the other values */
1110 for (i = 1; i < ARRAY_SIZE(s->config); i++)
8d50e447 1111 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
86ed3669
MB		 1112
1113 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
8d50e447 1114 snd_soc_write(codec, WM9081_EQ_1, eq1);
86ed3669
MB		 1115 }
1116
8d50e447
MB		 1117 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1118 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1119 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1120 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
86ed3669
MB		 1121
1122 return 0;
1123}
1124
1125static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1126{
1127 struct snd_soc_codec *codec = codec_dai->codec;
1128 unsigned int reg;
1129
8d50e447 1130 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
86ed3669
MB		 1131
1132 if (mute)
1133 reg |= WM9081_DAC_MUTE;
1134 else
1135 reg &= ~WM9081_DAC_MUTE;
1136
8d50e447 1137 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
86ed3669
MB		 1138
1139 return 0;
1140}
1141
1142static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai,
1143 int clk_id, unsigned int freq, int dir)
1144{
1145 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1146 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 1147
1148 switch (clk_id) {
1149 case WM9081_SYSCLK_MCLK:
1150 case WM9081_SYSCLK_FLL_MCLK:
1151 wm9081->sysclk_source = clk_id;
1152 wm9081->mclk_rate = freq;
1153 break;
1154
1155 default:
1156 return -EINVAL;
1157 }
1158
1159 return 0;
1160}
1161
1162static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
a5479e38 1163 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
86ed3669
MB		 1164{
1165 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1166 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 1167 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669
MB		 1168
1169 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1170
e0026bea 1171 if (slots < 0 || slots > 4)
86ed3669
MB		 1172 return -EINVAL;
1173
e0026bea
MB		 1174 wm9081->tdm_width = slot_width;
1175
1176 if (slots == 0)
1177 slots = 1;
1178
86ed3669
MB		 1179 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1180
a5479e38 1181 switch (rx_mask) {
86ed3669
MB		 1182 case 1:
1183 break;
1184 case 2:
1185 aif1 |= 0x10;
1186 break;
1187 case 4:
1188 aif1 |= 0x20;
1189 break;
1190 case 8:
1191 aif1 |= 0x30;
1192 break;
1193 default:
1194 return -EINVAL;
1195 }
1196
8d50e447 1197 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
86ed3669
MB		 1198
1199 return 0;
1200}
1201
1202#define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1203
1204#define WM9081_FORMATS \
1205 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1206 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1207
1208static struct snd_soc_dai_ops wm9081_dai_ops = {
1209 .hw_params = wm9081_hw_params,
1210 .set_sysclk = wm9081_set_sysclk,
1211 .set_fmt = wm9081_set_dai_fmt,
1212 .digital_mute = wm9081_digital_mute,
1213 .set_tdm_slot = wm9081_set_tdm_slot,
1214};
1215
1216/* We report two channels because the CODEC processes a stereo signal, even
1217 * though it is only capable of handling a mono output.
1218 */
f0fba2ad
LG		 1219static struct snd_soc_dai_driver wm9081_dai = {
1220 .name = "wm9081-hifi",
86ed3669
MB		 1221 .playback = {
1222 .stream_name = "HiFi Playback",
1223 .channels_min = 1,
1224 .channels_max = 2,
1225 .rates = WM9081_RATES,
1226 .formats = WM9081_FORMATS,
1227 },
1228 .ops = &wm9081_dai_ops,
1229};
86ed3669 1230
f0fba2ad 1231static int wm9081_probe(struct snd_soc_codec *codec)
86ed3669 1232{
f0fba2ad 1233 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
ce6120cc 1234 struct snd_soc_dapm_context *dapm = &codec->dapm;
f0fba2ad
LG		 1235 int ret;
1236 u16 reg;
86ed3669 1237
f0fba2ad
LG		 1238 codec->control_data = wm9081->control_data;
1239 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm9081->control_type);
1240 if (ret != 0) {
1241 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1242 return ret;
86ed3669
MB		 1243 }
1244
f0fba2ad
LG		 1245 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1246 if (reg != 0x9081) {
1247 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1248 ret = -EINVAL;
1249 return ret;
1250 }
86ed3669 1251
f0fba2ad 1252 ret = wm9081_reset(codec);
86ed3669 1253 if (ret < 0) {
f0fba2ad
LG		 1254 dev_err(codec->dev, "Failed to issue reset\n");
1255 return ret;
86ed3669
MB		 1256 }
1257
f0fba2ad
LG		 1258 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1259
1260 /* Enable zero cross by default */
1261 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1262 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1263 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1264 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1265 reg | WM9081_SPKPGAZC);
1266
86ed3669
MB		 1267 snd_soc_add_controls(codec, wm9081_snd_controls,
1268 ARRAY_SIZE(wm9081_snd_controls));
1269 if (!wm9081->retune) {
1270 dev_dbg(codec->dev,
1271 "No ReTune Mobile data, using normal EQ\n");
1272 snd_soc_add_controls(codec, wm9081_eq_controls,
1273 ARRAY_SIZE(wm9081_eq_controls));
1274 }
1275
ce6120cc 1276 snd_soc_dapm_new_controls(dapm, wm9081_dapm_widgets,
86ed3669 1277 ARRAY_SIZE(wm9081_dapm_widgets));
ce6120cc 1278 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
86ed3669 1279
86ed3669 1280 return ret;
86ed3669
MB		 1281}
1282
f0fba2ad 1283static int wm9081_remove(struct snd_soc_codec *codec)
86ed3669 1284{
f0fba2ad 1285 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
86ed3669
MB		 1286 return 0;
1287}
1288
1289#ifdef CONFIG_PM
f0fba2ad 1290static int wm9081_suspend(struct snd_soc_codec *codec, pm_message_t state)
86ed3669 1291{
86ed3669
MB		 1292 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1293
1294 return 0;
1295}
1296
f0fba2ad 1297static int wm9081_resume(struct snd_soc_codec *codec)
86ed3669 1298{
86ed3669
MB		 1299 u16 *reg_cache = codec->reg_cache;
1300 int i;
1301
f0fba2ad 1302 for (i = 0; i < codec->driver->reg_cache_size; i++) {
86ed3669
MB		 1303 if (i == WM9081_SOFTWARE_RESET)
1304 continue;
1305
8d50e447 1306 snd_soc_write(codec, i, reg_cache[i]);
86ed3669
MB		 1307 }
1308
1309 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1310
1311 return 0;
1312}
1313#else
1314#define wm9081_suspend NULL
1315#define wm9081_resume NULL
1316#endif
1317
f0fba2ad 1318static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
86ed3669
MB		 1319 .probe = wm9081_probe,
1320 .remove = wm9081_remove,
1321 .suspend = wm9081_suspend,
1322 .resume = wm9081_resume,
f0fba2ad 1323 .set_bias_level = wm9081_set_bias_level,
e5eec34c 1324 .reg_cache_size = ARRAY_SIZE(wm9081_reg_defaults),
f0fba2ad
LG		 1325 .reg_word_size = sizeof(u16),
1326 .reg_cache_default = wm9081_reg_defaults,
1327 .volatile_register = wm9081_volatile_register,
86ed3669 1328};
86ed3669 1329
f0fba2ad 1330#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669
MB		 1331static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1332 const struct i2c_device_id *id)
1333{
1334 struct wm9081_priv *wm9081;
f0fba2ad 1335 int ret;
86ed3669
MB		 1336
1337 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1338 if (wm9081 == NULL)
1339 return -ENOMEM;
1340
86ed3669 1341 i2c_set_clientdata(i2c, wm9081);
7f984b55 1342 wm9081->control_type = SND_SOC_I2C;
f0fba2ad 1343 wm9081->control_data = i2c;
86ed3669 1344
3ee845ac
MB		 1345 if (dev_get_platdata(&i2c->dev))
1346 memcpy(&wm9081->retune, dev_get_platdata(&i2c->dev),
1347 sizeof(wm9081->retune));
1348
f0fba2ad
LG		 1349 ret = snd_soc_register_codec(&i2c->dev,
1350 &soc_codec_dev_wm9081, &wm9081_dai, 1);
1351 if (ret < 0)
1352 kfree(wm9081);
1353 return ret;
86ed3669
MB		 1354}
1355
1356static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1357{
f0fba2ad
LG		 1358 snd_soc_unregister_codec(&client->dev);
1359 kfree(i2c_get_clientdata(client));
86ed3669
MB		 1360 return 0;
1361}
1362
1363static const struct i2c_device_id wm9081_i2c_id[] = {
1364 { "wm9081", 0 },
1365 { }
1366};
1367MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1368
1369static struct i2c_driver wm9081_i2c_driver = {
1370 .driver = {
2031c064 1371 .name = "wm9081",
86ed3669
MB		 1372 .owner = THIS_MODULE,
1373 },
1374 .probe = wm9081_i2c_probe,
1375 .remove = __devexit_p(wm9081_i2c_remove),
1376 .id_table = wm9081_i2c_id,
1377};
f0fba2ad 1378#endif
86ed3669
MB		 1379
1380static int __init wm9081_modinit(void)
1381{
f0fba2ad
LG		 1382 int ret = 0;
1383#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669
MB		 1384 ret = i2c_add_driver(&wm9081_i2c_driver);
1385 if (ret != 0) {
1386 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1387 ret);
1388 }
f0fba2ad 1389#endif
86ed3669
MB		 1390 return ret;
1391}
1392module_init(wm9081_modinit);
1393
1394static void __exit wm9081_exit(void)
1395{
f0fba2ad 1396#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669 1397 i2c_del_driver(&wm9081_i2c_driver);
f0fba2ad 1398#endif
86ed3669
MB		 1399}
1400module_exit(wm9081_exit);
1401
1402
1403MODULE_DESCRIPTION("ASoC WM9081 driver");
1404MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1405MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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