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ASoC: Convert wm8971 MICBIAS to a supply widget
[deliverable/linux.git] / sound / soc / codecs / wm9081.c
CommitLineData
86ed3669
MB		 1/*
2 * wm9081.c -- WM9081 ALSA SoC Audio driver
3 *
4 * Author: Mark Brown
5 *
6 * Copyright 2009 Wolfson Microelectronics plc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
3ee845ac 18#include <linux/device.h>
86ed3669
MB		 19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
7cfa467b 22#include <linux/regmap.h>
5a0e3ad6 23#include <linux/slab.h>
86ed3669
MB		 24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
86ed3669
MB		 28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include <sound/wm9081.h>
32#include "wm9081.h"
33
7cfa467b
MB		 34static struct reg_default wm9081_reg[] = {
35 { 0, 0x9081 }, /* R0 - Software Reset */
36 { 2, 0x00B9 }, /* R2 - Analogue Lineout */
37 { 3, 0x00B9 }, /* R3 - Analogue Speaker PGA */
38 { 4, 0x0001 }, /* R4 - VMID Control */
39 { 5, 0x0068 }, /* R5 - Bias Control 1 */
40 { 7, 0x0000 }, /* R7 - Analogue Mixer */
41 { 8, 0x0000 }, /* R8 - Anti Pop Control */
42 { 9, 0x01DB }, /* R9 - Analogue Speaker 1 */
43 { 10, 0x0018 }, /* R10 - Analogue Speaker 2 */
44 { 11, 0x0180 }, /* R11 - Power Management */
45 { 12, 0x0000 }, /* R12 - Clock Control 1 */
46 { 13, 0x0038 }, /* R13 - Clock Control 2 */
47 { 14, 0x4000 }, /* R14 - Clock Control 3 */
48 { 16, 0x0000 }, /* R16 - FLL Control 1 */
49 { 17, 0x0200 }, /* R17 - FLL Control 2 */
50 { 18, 0x0000 }, /* R18 - FLL Control 3 */
51 { 19, 0x0204 }, /* R19 - FLL Control 4 */
52 { 20, 0x0000 }, /* R20 - FLL Control 5 */
53 { 22, 0x0000 }, /* R22 - Audio Interface 1 */
54 { 23, 0x0002 }, /* R23 - Audio Interface 2 */
55 { 24, 0x0008 }, /* R24 - Audio Interface 3 */
56 { 25, 0x0022 }, /* R25 - Audio Interface 4 */
57 { 27, 0x0006 }, /* R27 - Interrupt Status Mask */
58 { 28, 0x0000 }, /* R28 - Interrupt Polarity */
59 { 29, 0x0000 }, /* R29 - Interrupt Control */
60 { 30, 0x00C0 }, /* R30 - DAC Digital 1 */
61 { 31, 0x0008 }, /* R31 - DAC Digital 2 */
62 { 32, 0x09AF }, /* R32 - DRC 1 */
63 { 33, 0x4201 }, /* R33 - DRC 2 */
64 { 34, 0x0000 }, /* R34 - DRC 3 */
65 { 35, 0x0000 }, /* R35 - DRC 4 */
66 { 38, 0x0000 }, /* R38 - Write Sequencer 1 */
67 { 39, 0x0000 }, /* R39 - Write Sequencer 2 */
68 { 40, 0x0002 }, /* R40 - MW Slave 1 */
69 { 42, 0x0000 }, /* R42 - EQ 1 */
70 { 43, 0x0000 }, /* R43 - EQ 2 */
71 { 44, 0x0FCA }, /* R44 - EQ 3 */
72 { 45, 0x0400 }, /* R45 - EQ 4 */
73 { 46, 0x00B8 }, /* R46 - EQ 5 */
74 { 47, 0x1EB5 }, /* R47 - EQ 6 */
75 { 48, 0xF145 }, /* R48 - EQ 7 */
76 { 49, 0x0B75 }, /* R49 - EQ 8 */
77 { 50, 0x01C5 }, /* R50 - EQ 9 */
78 { 51, 0x169E }, /* R51 - EQ 10 */
79 { 52, 0xF829 }, /* R52 - EQ 11 */
80 { 53, 0x07AD }, /* R53 - EQ 12 */
81 { 54, 0x1103 }, /* R54 - EQ 13 */
82 { 55, 0x1C58 }, /* R55 - EQ 14 */
83 { 56, 0xF373 }, /* R56 - EQ 15 */
84 { 57, 0x0A54 }, /* R57 - EQ 16 */
85 { 58, 0x0558 }, /* R58 - EQ 17 */
86 { 59, 0x0564 }, /* R59 - EQ 18 */
87 { 60, 0x0559 }, /* R60 - EQ 19 */
88 { 61, 0x4000 }, /* R61 - EQ 20 */
86ed3669
MB		 89};
90
91static struct {
92 int ratio;
93 int clk_sys_rate;
94} clk_sys_rates[] = {
95 { 64, 0 },
96 { 128, 1 },
97 { 192, 2 },
98 { 256, 3 },
99 { 384, 4 },
100 { 512, 5 },
101 { 768, 6 },
102 { 1024, 7 },
103 { 1408, 8 },
104 { 1536, 9 },
105};
106
107static struct {
108 int rate;
109 int sample_rate;
110} sample_rates[] = {
111 { 8000, 0 },
112 { 11025, 1 },
113 { 12000, 2 },
114 { 16000, 3 },
115 { 22050, 4 },
116 { 24000, 5 },
117 { 32000, 6 },
118 { 44100, 7 },
119 { 48000, 8 },
120 { 88200, 9 },
121 { 96000, 10 },
122};
123
124static struct {
125 int div; /* *10 due to .5s */
126 int bclk_div;
127} bclk_divs[] = {
128 { 10, 0 },
129 { 15, 1 },
130 { 20, 2 },
131 { 30, 3 },
132 { 40, 4 },
133 { 50, 5 },
134 { 55, 6 },
135 { 60, 7 },
136 { 80, 8 },
137 { 100, 9 },
138 { 110, 10 },
139 { 120, 11 },
140 { 160, 12 },
141 { 200, 13 },
142 { 220, 14 },
143 { 240, 15 },
144 { 250, 16 },
145 { 300, 17 },
146 { 320, 18 },
147 { 440, 19 },
148 { 480, 20 },
149};
150
151struct wm9081_priv {
7cfa467b 152 struct regmap *regmap;
86ed3669
MB		 153 int sysclk_source;
154 int mclk_rate;
155 int sysclk_rate;
156 int fs;
157 int bclk;
158 int master;
159 int fll_fref;
160 int fll_fout;
e0026bea 161 int tdm_width;
4a5f7bda 162 struct wm9081_pdata pdata;
86ed3669
MB		 163};
164
7cfa467b 165static bool wm9081_volatile_register(struct device *dev, unsigned int reg)
86ed3669
MB		 166{
167 switch (reg) {
8d50e447 168 case WM9081_SOFTWARE_RESET:
f8faadb6 169 case WM9081_INTERRUPT_STATUS:
7cfa467b 170 return true;
86ed3669 171 default:
7cfa467b 172 return false;
86ed3669
MB		 173 }
174}
175
7cfa467b 176static bool wm9081_readable_register(struct device *dev, unsigned int reg)
86ed3669 177{
7cfa467b
MB		 178 switch (reg) {
179 case WM9081_SOFTWARE_RESET:
180 case WM9081_ANALOGUE_LINEOUT:
181 case WM9081_ANALOGUE_SPEAKER_PGA:
182 case WM9081_VMID_CONTROL:
183 case WM9081_BIAS_CONTROL_1:
184 case WM9081_ANALOGUE_MIXER:
185 case WM9081_ANTI_POP_CONTROL:
186 case WM9081_ANALOGUE_SPEAKER_1:
187 case WM9081_ANALOGUE_SPEAKER_2:
188 case WM9081_POWER_MANAGEMENT:
189 case WM9081_CLOCK_CONTROL_1:
190 case WM9081_CLOCK_CONTROL_2:
191 case WM9081_CLOCK_CONTROL_3:
192 case WM9081_FLL_CONTROL_1:
193 case WM9081_FLL_CONTROL_2:
194 case WM9081_FLL_CONTROL_3:
195 case WM9081_FLL_CONTROL_4:
196 case WM9081_FLL_CONTROL_5:
197 case WM9081_AUDIO_INTERFACE_1:
198 case WM9081_AUDIO_INTERFACE_2:
199 case WM9081_AUDIO_INTERFACE_3:
200 case WM9081_AUDIO_INTERFACE_4:
201 case WM9081_INTERRUPT_STATUS:
202 case WM9081_INTERRUPT_STATUS_MASK:
203 case WM9081_INTERRUPT_POLARITY:
204 case WM9081_INTERRUPT_CONTROL:
205 case WM9081_DAC_DIGITAL_1:
206 case WM9081_DAC_DIGITAL_2:
207 case WM9081_DRC_1:
208 case WM9081_DRC_2:
209 case WM9081_DRC_3:
210 case WM9081_DRC_4:
211 case WM9081_WRITE_SEQUENCER_1:
212 case WM9081_WRITE_SEQUENCER_2:
213 case WM9081_MW_SLAVE_1:
214 case WM9081_EQ_1:
215 case WM9081_EQ_2:
216 case WM9081_EQ_3:
217 case WM9081_EQ_4:
218 case WM9081_EQ_5:
219 case WM9081_EQ_6:
220 case WM9081_EQ_7:
221 case WM9081_EQ_8:
222 case WM9081_EQ_9:
223 case WM9081_EQ_10:
224 case WM9081_EQ_11:
225 case WM9081_EQ_12:
226 case WM9081_EQ_13:
227 case WM9081_EQ_14:
228 case WM9081_EQ_15:
229 case WM9081_EQ_16:
230 case WM9081_EQ_17:
231 case WM9081_EQ_18:
232 case WM9081_EQ_19:
233 case WM9081_EQ_20:
234 return true;
235 default:
236 return false;
237 }
238}
239
240static int wm9081_reset(struct regmap *map)
241{
242 return regmap_write(map, WM9081_SOFTWARE_RESET, 0x9081);
86ed3669
MB		 243}
244
245static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
246static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
247static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
248static unsigned int drc_max_tlv[] = {
249 TLV_DB_RANGE_HEAD(4),
250 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
251 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
252 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
253 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
254};
255static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
256static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
257
258static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
259
260static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
261static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
262static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
263
264static const char *drc_high_text[] = {
265 "1",
266 "1/2",
267 "1/4",
268 "1/8",
269 "1/16",
270 "0",
271};
272
273static const struct soc_enum drc_high =
274 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
275
276static const char *drc_low_text[] = {
277 "1",
278 "1/2",
279 "1/4",
280 "1/8",
281 "0",
282};
283
284static const struct soc_enum drc_low =
285 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
286
287static const char *drc_atk_text[] = {
288 "181us",
289 "181us",
290 "363us",
291 "726us",
292 "1.45ms",
293 "2.9ms",
294 "5.8ms",
295 "11.6ms",
296 "23.2ms",
297 "46.4ms",
298 "92.8ms",
299 "185.6ms",
300};
301
302static const struct soc_enum drc_atk =
303 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
304
305static const char *drc_dcy_text[] = {
306 "186ms",
307 "372ms",
308 "743ms",
309 "1.49s",
310 "2.97s",
311 "5.94s",
312 "11.89s",
313 "23.78s",
314 "47.56s",
315};
316
317static const struct soc_enum drc_dcy =
318 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
319
320static const char *drc_qr_dcy_text[] = {
321 "0.725ms",
322 "1.45ms",
323 "5.8ms",
324};
325
326static const struct soc_enum drc_qr_dcy =
327 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
328
329static const char *dac_deemph_text[] = {
330 "None",
331 "32kHz",
332 "44.1kHz",
333 "48kHz",
334};
335
336static const struct soc_enum dac_deemph =
337 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
338
339static const char *speaker_mode_text[] = {
340 "Class D",
341 "Class AB",
342};
343
344static const struct soc_enum speaker_mode =
345 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
346
347static int speaker_mode_get(struct snd_kcontrol *kcontrol,
348 struct snd_ctl_elem_value *ucontrol)
349{
350 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
351 unsigned int reg;
352
8d50e447 353 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 354 if (reg & WM9081_SPK_MODE)
355 ucontrol->value.integer.value[0] = 1;
356 else
357 ucontrol->value.integer.value[0] = 0;
358
359 return 0;
360}
361
362/*
363 * Stop any attempts to change speaker mode while the speaker is enabled.
364 *
25985edc 365 * We also have some special anti-pop controls dependent on speaker
86ed3669
MB		 366 * mode which must be changed along with the mode.
367 */
368static int speaker_mode_put(struct snd_kcontrol *kcontrol,
369 struct snd_ctl_elem_value *ucontrol)
370{
371 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
8d50e447
MB		 372 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
373 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 374
375 /* Are we changing anything? */
376 if (ucontrol->value.integer.value[0] ==
377 ((reg2 & WM9081_SPK_MODE) != 0))
378 return 0;
379
380 /* Don't try to change modes while enabled */
381 if (reg_pwr & WM9081_SPK_ENA)
382 return -EINVAL;
383
384 if (ucontrol->value.integer.value[0]) {
385 /* Class AB */
386 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
387 reg2 |= WM9081_SPK_MODE;
388 } else {
389 /* Class D */
390 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
391 reg2 &= ~WM9081_SPK_MODE;
392 }
393
8d50e447 394 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
86ed3669
MB		 395
396 return 0;
397}
398
399static const struct snd_kcontrol_new wm9081_snd_controls[] = {
400SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
401SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
402
403SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
404
405SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
406SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
407SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
408
409SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
410SOC_ENUM("DRC High Slope", drc_high),
411SOC_ENUM("DRC Low Slope", drc_low),
412SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
413SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
414SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
415SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
416SOC_ENUM("DRC Attack", drc_atk),
417SOC_ENUM("DRC Decay", drc_dcy),
418SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
419SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
420SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
421SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
422
423SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
424
425SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
426SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
427SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
428SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
429SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
430 out_tlv),
431SOC_ENUM("DAC Deemphasis", dac_deemph),
432SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
433};
434
435static const struct snd_kcontrol_new wm9081_eq_controls[] = {
436SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
437SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
438SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
439SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
440SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
441};
442
443static const struct snd_kcontrol_new mixer[] = {
444SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
445SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
446SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
447};
448
86ed3669
MB		 449struct _fll_div {
450 u16 fll_fratio;
451 u16 fll_outdiv;
452 u16 fll_clk_ref_div;
453 u16 n;
454 u16 k;
455};
456
457/* The size in bits of the FLL divide multiplied by 10
458 * to allow rounding later */
459#define FIXED_FLL_SIZE ((1 << 16) * 10)
460
461static struct {
462 unsigned int min;
463 unsigned int max;
464 u16 fll_fratio;
465 int ratio;
466} fll_fratios[] = {
467 { 0, 64000, 4, 16 },
468 { 64000, 128000, 3, 8 },
469 { 128000, 256000, 2, 4 },
470 { 256000, 1000000, 1, 2 },
471 { 1000000, 13500000, 0, 1 },
472};
473
474static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
475 unsigned int Fout)
476{
477 u64 Kpart;
478 unsigned int K, Ndiv, Nmod, target;
479 unsigned int div;
480 int i;
481
482 /* Fref must be <=13.5MHz */
483 div = 1;
484 while ((Fref / div) > 13500000) {
485 div *= 2;
486
487 if (div > 8) {
488 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
489 Fref);
490 return -EINVAL;
491 }
492 }
493 fll_div->fll_clk_ref_div = div / 2;
494
495 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
496
497 /* Apply the division for our remaining calculations */
498 Fref /= div;
499
500 /* Fvco should be 90-100MHz; don't check the upper bound */
501 div = 0;
502 target = Fout * 2;
503 while (target < 90000000) {
504 div++;
505 target *= 2;
506 if (div > 7) {
507 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
508 Fout);
509 return -EINVAL;
510 }
511 }
512 fll_div->fll_outdiv = div;
513
514 pr_debug("Fvco=%dHz\n", target);
515
25985edc 516 /* Find an appropriate FLL_FRATIO and factor it out of the target */
86ed3669
MB		 517 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
518 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
519 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
520 target /= fll_fratios[i].ratio;
521 break;
522 }
523 }
524 if (i == ARRAY_SIZE(fll_fratios)) {
525 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
526 return -EINVAL;
527 }
528
529 /* Now, calculate N.K */
530 Ndiv = target / Fref;
531
532 fll_div->n = Ndiv;
533 Nmod = target % Fref;
534 pr_debug("Nmod=%d\n", Nmod);
535
536 /* Calculate fractional part - scale up so we can round. */
537 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
538
539 do_div(Kpart, Fref);
540
541 K = Kpart & 0xFFFFFFFF;
542
543 if ((K % 10) >= 5)
544 K += 5;
545
546 /* Move down to proper range now rounding is done */
547 fll_div->k = K / 10;
548
549 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
550 fll_div->n, fll_div->k,
551 fll_div->fll_fratio, fll_div->fll_outdiv,
552 fll_div->fll_clk_ref_div);
553
554 return 0;
555}
556
557static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
558 unsigned int Fref, unsigned int Fout)
559{
b2c812e2 560 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 561 u16 reg1, reg4, reg5;
562 struct _fll_div fll_div;
563 int ret;
564 int clk_sys_reg;
565
566 /* Any change? */
567 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
568 return 0;
569
570 /* Disable the FLL */
571 if (Fout == 0) {
572 dev_dbg(codec->dev, "FLL disabled\n");
573 wm9081->fll_fref = 0;
574 wm9081->fll_fout = 0;
575
576 return 0;
577 }
578
579 ret = fll_factors(&fll_div, Fref, Fout);
580 if (ret != 0)
581 return ret;
582
8d50e447 583 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
86ed3669
MB		 584 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
585
586 switch (fll_id) {
587 case WM9081_SYSCLK_FLL_MCLK:
588 reg5 |= 0x1;
589 break;
590
591 default:
592 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
593 return -EINVAL;
594 }
595
596 /* Disable CLK_SYS while we reconfigure */
8d50e447 597 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669 598 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 599 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
86ed3669
MB		 600 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
601
602 /* Any FLL configuration change requires that the FLL be
603 * disabled first. */
8d50e447 604 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
86ed3669 605 reg1 &= ~WM9081_FLL_ENA;
8d50e447 606 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669
MB		 607
608 /* Apply the configuration */
609 if (fll_div.k)
610 reg1 |= WM9081_FLL_FRAC_MASK;
611 else
612 reg1 &= ~WM9081_FLL_FRAC_MASK;
8d50e447 613 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669 614
8d50e447 615 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
86ed3669
MB		 616 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
617 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
8d50e447 618 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
86ed3669 619
8d50e447 620 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
86ed3669
MB		 621 reg4 &= ~WM9081_FLL_N_MASK;
622 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
8d50e447 623 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
86ed3669
MB		 624
625 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
626 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
8d50e447 627 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
86ed3669 628
249c5156
MB		 629 /* Set gain to the recommended value */
630 snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
631 WM9081_FLL_GAIN_MASK, 0);
632
86ed3669 633 /* Enable the FLL */
8d50e447 634 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
86ed3669
MB		 635
636 /* Then bring CLK_SYS up again if it was disabled */
637 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 638 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
86ed3669
MB		 639
640 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
641
642 wm9081->fll_fref = Fref;
643 wm9081->fll_fout = Fout;
644
645 return 0;
646}
647
648static int configure_clock(struct snd_soc_codec *codec)
649{
b2c812e2 650 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 651 int new_sysclk, i, target;
652 unsigned int reg;
653 int ret = 0;
654 int mclkdiv = 0;
655 int fll = 0;
656
657 switch (wm9081->sysclk_source) {
658 case WM9081_SYSCLK_MCLK:
659 if (wm9081->mclk_rate > 12225000) {
660 mclkdiv = 1;
661 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
662 } else {
663 wm9081->sysclk_rate = wm9081->mclk_rate;
664 }
665 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
666 break;
667
668 case WM9081_SYSCLK_FLL_MCLK:
669 /* If we have a sample rate calculate a CLK_SYS that
670 * gives us a suitable DAC configuration, plus BCLK.
671 * Ideally we would check to see if we can clock
672 * directly from MCLK and only use the FLL if this is
673 * not the case, though care must be taken with free
674 * running mode.
675 */
676 if (wm9081->master && wm9081->bclk) {
677 /* Make sure we can generate CLK_SYS and BCLK
678 * and that we've got 3MHz for optimal
679 * performance. */
680 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
681 target = wm9081->fs * clk_sys_rates[i].ratio;
0154724d 682 new_sysclk = target;
86ed3669
MB		 683 if (target >= wm9081->bclk &&
684 target > 3000000)
0154724d 685 break;
86ed3669 686 }
4b75e947
MB		 687
688 if (i == ARRAY_SIZE(clk_sys_rates))
689 return -EINVAL;
690
86ed3669
MB		 691 } else if (wm9081->fs) {
692 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
693 new_sysclk = clk_sys_rates[i].ratio
694 * wm9081->fs;
695 if (new_sysclk > 3000000)
696 break;
697 }
4b75e947
MB		 698
699 if (i == ARRAY_SIZE(clk_sys_rates))
700 return -EINVAL;
701
86ed3669
MB		 702 } else {
703 new_sysclk = 12288000;
704 }
705
706 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
707 wm9081->mclk_rate, new_sysclk);
708 if (ret == 0) {
709 wm9081->sysclk_rate = new_sysclk;
710
711 /* Switch SYSCLK over to FLL */
712 fll = 1;
713 } else {
714 wm9081->sysclk_rate = wm9081->mclk_rate;
715 }
716 break;
717
718 default:
719 return -EINVAL;
720 }
721
8d50e447 722 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
86ed3669
MB		 723 if (mclkdiv)
724 reg |= WM9081_MCLKDIV2;
725 else
726 reg &= ~WM9081_MCLKDIV2;
8d50e447 727 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
86ed3669 728
8d50e447 729 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669
MB		 730 if (fll)
731 reg |= WM9081_CLK_SRC_SEL;
732 else
733 reg &= ~WM9081_CLK_SRC_SEL;
8d50e447 734 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
86ed3669
MB		 735
736 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
737
738 return ret;
739}
740
741static int clk_sys_event(struct snd_soc_dapm_widget *w,
742 struct snd_kcontrol *kcontrol, int event)
743{
744 struct snd_soc_codec *codec = w->codec;
b2c812e2 745 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 746
747 /* This should be done on init() for bypass paths */
748 switch (wm9081->sysclk_source) {
749 case WM9081_SYSCLK_MCLK:
750 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
751 break;
752 case WM9081_SYSCLK_FLL_MCLK:
753 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
754 wm9081->mclk_rate);
755 break;
756 default:
757 dev_err(codec->dev, "System clock not configured\n");
758 return -EINVAL;
759 }
760
761 switch (event) {
762 case SND_SOC_DAPM_PRE_PMU:
763 configure_clock(codec);
764 break;
765
766 case SND_SOC_DAPM_POST_PMD:
767 /* Disable the FLL if it's running */
768 wm9081_set_fll(codec, 0, 0, 0);
769 break;
770 }
771
772 return 0;
773}
774
775static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
776SND_SOC_DAPM_INPUT("IN1"),
777SND_SOC_DAPM_INPUT("IN2"),
778
779SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
780
781SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
782 mixer, ARRAY_SIZE(mixer)),
783
784SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
785
378a90f4 786SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
4e8e78e3 787SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
86ed3669
MB		 788
789SND_SOC_DAPM_OUTPUT("LINEOUT"),
790SND_SOC_DAPM_OUTPUT("SPKN"),
791SND_SOC_DAPM_OUTPUT("SPKP"),
792
793SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
794 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
795SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
796SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
a04e0c86 797SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT, 7, 0, NULL, 0),
86ed3669
MB		 798};
799
800
149c7b44 801static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
86ed3669
MB		 802 { "DAC", NULL, "CLK_SYS" },
803 { "DAC", NULL, "CLK_DSP" },
804
805 { "Mixer", "IN1 Switch", "IN1" },
806 { "Mixer", "IN2 Switch", "IN2" },
807 { "Mixer", "Playback Switch", "DAC" },
808
809 { "LINEOUT PGA", NULL, "Mixer" },
810 { "LINEOUT PGA", NULL, "TOCLK" },
811 { "LINEOUT PGA", NULL, "CLK_SYS" },
812
813 { "LINEOUT", NULL, "LINEOUT PGA" },
814
815 { "Speaker PGA", NULL, "Mixer" },
816 { "Speaker PGA", NULL, "TOCLK" },
817 { "Speaker PGA", NULL, "CLK_SYS" },
818
378a90f4 819 { "Speaker", NULL, "Speaker PGA" },
a04e0c86 820 { "Speaker", NULL, "TSENSE" },
378a90f4
MB		 821
822 { "SPKN", NULL, "Speaker" },
823 { "SPKP", NULL, "Speaker" },
86ed3669
MB		 824};
825
826static int wm9081_set_bias_level(struct snd_soc_codec *codec,
827 enum snd_soc_bias_level level)
828{
829 u16 reg;
830
831 switch (level) {
832 case SND_SOC_BIAS_ON:
833 break;
834
835 case SND_SOC_BIAS_PREPARE:
836 /* VMID=2*40k */
8d50e447 837 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669
MB		 838 reg &= ~WM9081_VMID_SEL_MASK;
839 reg |= 0x2;
8d50e447 840 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 841
842 /* Normal bias current */
8d50e447 843 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 844 reg &= ~WM9081_STBY_BIAS_ENA;
8d50e447 845 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 846 break;
847
848 case SND_SOC_BIAS_STANDBY:
849 /* Initial cold start */
ce6120cc 850 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
86ed3669 851 /* Disable LINEOUT discharge */
8d50e447 852 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
86ed3669 853 reg &= ~WM9081_LINEOUT_DISCH;
8d50e447 854 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
86ed3669
MB		 855
856 /* Select startup bias source */
8d50e447 857 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 858 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
8d50e447 859 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 860
861 /* VMID 2*4k; Soft VMID ramp enable */
8d50e447 862 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669 863 reg |= WM9081_VMID_RAMP | 0x6;
8d50e447 864 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 865
866 mdelay(100);
867
868 /* Normal bias enable & soft start off */
86ed3669 869 reg &= ~WM9081_VMID_RAMP;
8d50e447 870 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 871
872 /* Standard bias source */
8d50e447 873 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 874 reg &= ~WM9081_BIAS_SRC;
8d50e447 875 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 876 }
877
878 /* VMID 2*240k */
f1e10354 879 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669 880 reg &= ~WM9081_VMID_SEL_MASK;
9f9619a0 881 reg |= 0x04;
8d50e447 882 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 883
884 /* Standby bias current on */
8d50e447 885 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 886 reg |= WM9081_STBY_BIAS_ENA;
8d50e447 887 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 888 break;
889
890 case SND_SOC_BIAS_OFF:
adf46362 891 /* Startup bias source and disable bias */
8d50e447 892 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 893 reg |= WM9081_BIAS_SRC;
adf46362 894 reg &= ~WM9081_BIAS_ENA;
8d50e447 895 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669 896
adf46362 897 /* Disable VMID with soft ramping */
8d50e447 898 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
adf46362 899 reg &= ~WM9081_VMID_SEL_MASK;
86ed3669 900 reg |= WM9081_VMID_RAMP;
8d50e447 901 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 902
903 /* Actively discharge LINEOUT */
8d50e447 904 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
86ed3669 905 reg |= WM9081_LINEOUT_DISCH;
8d50e447 906 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
86ed3669
MB		 907 break;
908 }
909
ce6120cc 910 codec->dapm.bias_level = level;
86ed3669
MB		 911
912 return 0;
913}
914
915static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
916 unsigned int fmt)
917{
918 struct snd_soc_codec *codec = dai->codec;
b2c812e2 919 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 920 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 921
922 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
923 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
924
925 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
926 case SND_SOC_DAIFMT_CBS_CFS:
927 wm9081->master = 0;
928 break;
929 case SND_SOC_DAIFMT_CBS_CFM:
930 aif2 |= WM9081_LRCLK_DIR;
931 wm9081->master = 1;
932 break;
933 case SND_SOC_DAIFMT_CBM_CFS:
934 aif2 |= WM9081_BCLK_DIR;
935 wm9081->master = 1;
936 break;
937 case SND_SOC_DAIFMT_CBM_CFM:
938 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
939 wm9081->master = 1;
940 break;
941 default:
942 return -EINVAL;
943 }
944
945 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
946 case SND_SOC_DAIFMT_DSP_B:
947 aif2 |= WM9081_AIF_LRCLK_INV;
948 case SND_SOC_DAIFMT_DSP_A:
949 aif2 |= 0x3;
950 break;
951 case SND_SOC_DAIFMT_I2S:
952 aif2 |= 0x2;
953 break;
954 case SND_SOC_DAIFMT_RIGHT_J:
955 break;
956 case SND_SOC_DAIFMT_LEFT_J:
957 aif2 |= 0x1;
958 break;
959 default:
960 return -EINVAL;
961 }
962
963 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
964 case SND_SOC_DAIFMT_DSP_A:
965 case SND_SOC_DAIFMT_DSP_B:
966 /* frame inversion not valid for DSP modes */
967 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
968 case SND_SOC_DAIFMT_NB_NF:
969 break;
970 case SND_SOC_DAIFMT_IB_NF:
971 aif2 |= WM9081_AIF_BCLK_INV;
972 break;
973 default:
974 return -EINVAL;
975 }
976 break;
977
978 case SND_SOC_DAIFMT_I2S:
979 case SND_SOC_DAIFMT_RIGHT_J:
980 case SND_SOC_DAIFMT_LEFT_J:
981 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
982 case SND_SOC_DAIFMT_NB_NF:
983 break;
984 case SND_SOC_DAIFMT_IB_IF:
985 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
986 break;
987 case SND_SOC_DAIFMT_IB_NF:
988 aif2 |= WM9081_AIF_BCLK_INV;
989 break;
990 case SND_SOC_DAIFMT_NB_IF:
991 aif2 |= WM9081_AIF_LRCLK_INV;
992 break;
993 default:
994 return -EINVAL;
995 }
996 break;
997 default:
998 return -EINVAL;
999 }
1000
8d50e447 1001 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
86ed3669
MB		 1002
1003 return 0;
1004}
1005
1006static int wm9081_hw_params(struct snd_pcm_substream *substream,
1007 struct snd_pcm_hw_params *params,
1008 struct snd_soc_dai *dai)
1009{
1010 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1011 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 1012 int ret, i, best, best_val, cur_val;
1013 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
1014
8d50e447 1015 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
86ed3669
MB		 1016 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1017
8d50e447 1018 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669 1019
8d50e447 1020 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 1021 aif2 &= ~WM9081_AIF_WL_MASK;
1022
8d50e447 1023 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
86ed3669
MB		 1024 aif3 &= ~WM9081_BCLK_DIV_MASK;
1025
8d50e447 1026 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
86ed3669
MB		 1027 aif4 &= ~WM9081_LRCLK_RATE_MASK;
1028
86ed3669 1029 wm9081->fs = params_rate(params);
86ed3669 1030
e0026bea
MB		 1031 if (wm9081->tdm_width) {
1032 /* If TDM is set up then that fixes our BCLK. */
86ed3669
MB		 1033 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
1034 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
e0026bea
MB		 1035
1036 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
1037 } else {
1038 /* Otherwise work out a BCLK from the sample size */
1039 wm9081->bclk = 2 * wm9081->fs;
1040
1041 switch (params_format(params)) {
1042 case SNDRV_PCM_FORMAT_S16_LE:
1043 wm9081->bclk *= 16;
1044 break;
1045 case SNDRV_PCM_FORMAT_S20_3LE:
1046 wm9081->bclk *= 20;
1047 aif2 |= 0x4;
1048 break;
1049 case SNDRV_PCM_FORMAT_S24_LE:
1050 wm9081->bclk *= 24;
1051 aif2 |= 0x8;
1052 break;
1053 case SNDRV_PCM_FORMAT_S32_LE:
1054 wm9081->bclk *= 32;
1055 aif2 |= 0xc;
1056 break;
1057 default:
1058 return -EINVAL;
1059 }
86ed3669
MB		 1060 }
1061
1062 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1063
1064 ret = configure_clock(codec);
1065 if (ret != 0)
1066 return ret;
1067
1068 /* Select nearest CLK_SYS_RATE */
1069 best = 0;
1070 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1071 - wm9081->fs);
1072 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1073 cur_val = abs((wm9081->sysclk_rate /
a419aef8 1074 clk_sys_rates[i].ratio) - wm9081->fs);
86ed3669
MB		 1075 if (cur_val < best_val) {
1076 best = i;
1077 best_val = cur_val;
1078 }
1079 }
1080 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1081 clk_sys_rates[best].ratio);
1082 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1083 << WM9081_CLK_SYS_RATE_SHIFT);
1084
1085 /* SAMPLE_RATE */
1086 best = 0;
1087 best_val = abs(wm9081->fs - sample_rates[0].rate);
1088 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1089 /* Closest match */
1090 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1091 if (cur_val < best_val) {
1092 best = i;
1093 best_val = cur_val;
1094 }
1095 }
1096 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1097 sample_rates[best].rate);
0154724d
MB		 1098 clk_ctrl2 |= (sample_rates[best].sample_rate
1099 << WM9081_SAMPLE_RATE_SHIFT);
86ed3669
MB		 1100
1101 /* BCLK_DIV */
1102 best = 0;
1103 best_val = INT_MAX;
1104 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1105 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1106 - wm9081->bclk;
1107 if (cur_val < 0) /* Table is sorted */
1108 break;
1109 if (cur_val < best_val) {
1110 best = i;
1111 best_val = cur_val;
1112 }
1113 }
1114 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1115 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1116 bclk_divs[best].div, wm9081->bclk);
1117 aif3 |= bclk_divs[best].bclk_div;
1118
1119 /* LRCLK is a simple fraction of BCLK */
1120 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1121 aif4 |= wm9081->bclk / wm9081->fs;
1122
1123 /* Apply a ReTune Mobile configuration if it's in use */
4a5f7bda
MB		 1124 if (wm9081->pdata.num_retune_configs) {
1125 struct wm9081_pdata *pdata = &wm9081->pdata;
86ed3669
MB		 1126 struct wm9081_retune_mobile_setting *s;
1127 int eq1;
1128
1129 best = 0;
4a5f7bda
MB		 1130 best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
1131 for (i = 0; i < pdata->num_retune_configs; i++) {
1132 cur_val = abs(pdata->retune_configs[i].rate -
1133 wm9081->fs);
86ed3669
MB		 1134 if (cur_val < best_val) {
1135 best_val = cur_val;
1136 best = i;
1137 }
1138 }
4a5f7bda 1139 s = &pdata->retune_configs[best];
86ed3669
MB		 1140
1141 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1142 s->name, s->rate);
1143
1144 /* If the EQ is enabled then disable it while we write out */
8d50e447 1145 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
86ed3669 1146 if (eq1 & WM9081_EQ_ENA)
8d50e447 1147 snd_soc_write(codec, WM9081_EQ_1, 0);
86ed3669
MB		 1148
1149 /* Write out the other values */
1150 for (i = 1; i < ARRAY_SIZE(s->config); i++)
8d50e447 1151 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
86ed3669
MB		 1152
1153 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
8d50e447 1154 snd_soc_write(codec, WM9081_EQ_1, eq1);
86ed3669
MB		 1155 }
1156
8d50e447
MB		 1157 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1158 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1159 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1160 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
86ed3669
MB		 1161
1162 return 0;
1163}
1164
1165static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1166{
1167 struct snd_soc_codec *codec = codec_dai->codec;
1168 unsigned int reg;
1169
8d50e447 1170 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
86ed3669
MB		 1171
1172 if (mute)
1173 reg |= WM9081_DAC_MUTE;
1174 else
1175 reg &= ~WM9081_DAC_MUTE;
1176
8d50e447 1177 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
86ed3669
MB		 1178
1179 return 0;
1180}
1181
da1c6ea6
MB		 1182static int wm9081_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1183 int source, unsigned int freq, int dir)
86ed3669 1184{
b2c812e2 1185 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 1186
1187 switch (clk_id) {
1188 case WM9081_SYSCLK_MCLK:
1189 case WM9081_SYSCLK_FLL_MCLK:
1190 wm9081->sysclk_source = clk_id;
1191 wm9081->mclk_rate = freq;
1192 break;
1193
1194 default:
1195 return -EINVAL;
1196 }
1197
1198 return 0;
1199}
1200
1201static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
a5479e38 1202 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
86ed3669
MB		 1203{
1204 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1205 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 1206 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669
MB		 1207
1208 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1209
e0026bea 1210 if (slots < 0 || slots > 4)
86ed3669
MB		 1211 return -EINVAL;
1212
e0026bea
MB		 1213 wm9081->tdm_width = slot_width;
1214
1215 if (slots == 0)
1216 slots = 1;
1217
86ed3669
MB		 1218 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1219
a5479e38 1220 switch (rx_mask) {
86ed3669
MB		 1221 case 1:
1222 break;
1223 case 2:
1224 aif1 |= 0x10;
1225 break;
1226 case 4:
1227 aif1 |= 0x20;
1228 break;
1229 case 8:
1230 aif1 |= 0x30;
1231 break;
1232 default:
1233 return -EINVAL;
1234 }
1235
8d50e447 1236 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
86ed3669
MB		 1237
1238 return 0;
1239}
1240
1241#define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1242
1243#define WM9081_FORMATS \
1244 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1245 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1246
1247static struct snd_soc_dai_ops wm9081_dai_ops = {
1248 .hw_params = wm9081_hw_params,
86ed3669
MB		 1249 .set_fmt = wm9081_set_dai_fmt,
1250 .digital_mute = wm9081_digital_mute,
1251 .set_tdm_slot = wm9081_set_tdm_slot,
1252};
1253
1254/* We report two channels because the CODEC processes a stereo signal, even
1255 * though it is only capable of handling a mono output.
1256 */
f0fba2ad
LG		 1257static struct snd_soc_dai_driver wm9081_dai = {
1258 .name = "wm9081-hifi",
86ed3669
MB		 1259 .playback = {
1260 .stream_name = "HiFi Playback",
1261 .channels_min = 1,
1262 .channels_max = 2,
1263 .rates = WM9081_RATES,
1264 .formats = WM9081_FORMATS,
1265 },
1266 .ops = &wm9081_dai_ops,
1267};
86ed3669 1268
f0fba2ad 1269static int wm9081_probe(struct snd_soc_codec *codec)
86ed3669 1270{
f0fba2ad
LG		 1271 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1272 int ret;
1273 u16 reg;
86ed3669 1274
7cfa467b
MB		 1275 codec->control_data = wm9081->regmap;
1276
1277 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
f0fba2ad
LG		 1278 if (ret != 0) {
1279 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1280 return ret;
86ed3669
MB		 1281 }
1282
4a5f7bda
MB		 1283 reg = 0;
1284 if (wm9081->pdata.irq_high)
1285 reg |= WM9081_IRQ_POL;
1286 if (!wm9081->pdata.irq_cmos)
1287 reg |= WM9081_IRQ_OP_CTRL;
1288 snd_soc_update_bits(codec, WM9081_INTERRUPT_CONTROL,
1289 WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
1290
f0fba2ad
LG		 1291 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1292
1293 /* Enable zero cross by default */
1294 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1295 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1296 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1297 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1298 reg | WM9081_SPKPGAZC);
1299
4a5f7bda 1300 if (!wm9081->pdata.num_retune_configs) {
86ed3669
MB		 1301 dev_dbg(codec->dev,
1302 "No ReTune Mobile data, using normal EQ\n");
1303 snd_soc_add_controls(codec, wm9081_eq_controls,
1304 ARRAY_SIZE(wm9081_eq_controls));
1305 }
1306
86ed3669 1307 return ret;
86ed3669
MB		 1308}
1309
f0fba2ad 1310static int wm9081_remove(struct snd_soc_codec *codec)
86ed3669 1311{
f0fba2ad 1312 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
86ed3669
MB		 1313 return 0;
1314}
1315
1316#ifdef CONFIG_PM
f0fba2ad 1317static int wm9081_suspend(struct snd_soc_codec *codec, pm_message_t state)
86ed3669 1318{
86ed3669
MB		 1319 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1320
1321 return 0;
1322}
1323
f0fba2ad 1324static int wm9081_resume(struct snd_soc_codec *codec)
86ed3669 1325{
7cfa467b 1326 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669 1327
7cfa467b 1328 regcache_sync(wm9081->regmap);
86ed3669
MB		 1329
1330 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1331
1332 return 0;
1333}
1334#else
1335#define wm9081_suspend NULL
1336#define wm9081_resume NULL
1337#endif
1338
f0fba2ad 1339static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
86ed3669
MB		 1340 .probe = wm9081_probe,
1341 .remove = wm9081_remove,
1342 .suspend = wm9081_suspend,
1343 .resume = wm9081_resume,
63d24b79
MB		 1344
1345 .set_sysclk = wm9081_set_sysclk,
f0fba2ad 1346 .set_bias_level = wm9081_set_bias_level,
63d24b79 1347
680fa1f8
MB		 1348 .controls = wm9081_snd_controls,
1349 .num_controls = ARRAY_SIZE(wm9081_snd_controls),
149c7b44
MB		 1350 .dapm_widgets = wm9081_dapm_widgets,
1351 .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
1352 .dapm_routes = wm9081_audio_paths,
1353 .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
86ed3669 1354};
86ed3669 1355
7cfa467b
MB		 1356static const struct regmap_config wm9081_regmap = {
1357 .reg_bits = 8,
1358 .val_bits = 16,
1359
1360 .max_register = WM9081_MAX_REGISTER,
1361 .reg_defaults = wm9081_reg,
1362 .num_reg_defaults = ARRAY_SIZE(wm9081_reg),
1363 .volatile_reg = wm9081_volatile_register,
1364 .readable_reg = wm9081_readable_register,
1365 .cache_type = REGCACHE_RBTREE,
1366};
1367
f0fba2ad 1368#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669
MB		 1369static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1370 const struct i2c_device_id *id)
1371{
1372 struct wm9081_priv *wm9081;
7cfa467b 1373 unsigned int reg;
f0fba2ad 1374 int ret;
86ed3669
MB		 1375
1376 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1377 if (wm9081 == NULL)
1378 return -ENOMEM;
1379
86ed3669 1380 i2c_set_clientdata(i2c, wm9081);
7cfa467b
MB		 1381
1382 wm9081->regmap = regmap_init_i2c(i2c, &wm9081_regmap);
1383 if (IS_ERR(wm9081->regmap)) {
1384 ret = PTR_ERR(wm9081->regmap);
1385 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1386 goto err;
1387 }
1388
1389 ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, &reg);
1390 if (ret != 0) {
1391 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1392 goto err_regmap;
1393 }
1394 if (reg != 0x9081) {
1395 dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1396 ret = -EINVAL;
1397 goto err_regmap;
1398 }
1399
1400 ret = wm9081_reset(wm9081->regmap);
1401 if (ret < 0) {
1402 dev_err(&i2c->dev, "Failed to issue reset\n");
1403 goto err_regmap;
1404 }
86ed3669 1405
3ee845ac 1406 if (dev_get_platdata(&i2c->dev))
4a5f7bda
MB		 1407 memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
1408 sizeof(wm9081->pdata));
3ee845ac 1409
f0fba2ad
LG		 1410 ret = snd_soc_register_codec(&i2c->dev,
1411 &soc_codec_dev_wm9081, &wm9081_dai, 1);
1412 if (ret < 0)
7cfa467b
MB		 1413 goto err_regmap;
1414
1415 return 0;
1416
1417err_regmap:
1418 regmap_exit(wm9081->regmap);
1419err:
1420 kfree(wm9081);
1421
f0fba2ad 1422 return ret;
86ed3669
MB		 1423}
1424
1425static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1426{
7cfa467b
MB		 1427 struct wm9081_priv *wm9081 = i2c_get_clientdata(client);
1428
f0fba2ad 1429 snd_soc_unregister_codec(&client->dev);
7cfa467b 1430 regmap_exit(wm9081->regmap);
f0fba2ad 1431 kfree(i2c_get_clientdata(client));
86ed3669
MB		 1432 return 0;
1433}
1434
1435static const struct i2c_device_id wm9081_i2c_id[] = {
1436 { "wm9081", 0 },
1437 { }
1438};
1439MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1440
1441static struct i2c_driver wm9081_i2c_driver = {
1442 .driver = {
2031c064 1443 .name = "wm9081",
86ed3669
MB		 1444 .owner = THIS_MODULE,
1445 },
1446 .probe = wm9081_i2c_probe,
1447 .remove = __devexit_p(wm9081_i2c_remove),
1448 .id_table = wm9081_i2c_id,
1449};
f0fba2ad 1450#endif
86ed3669
MB		 1451
1452static int __init wm9081_modinit(void)
1453{
f0fba2ad
LG		 1454 int ret = 0;
1455#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669
MB		 1456 ret = i2c_add_driver(&wm9081_i2c_driver);
1457 if (ret != 0) {
1458 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1459 ret);
1460 }
f0fba2ad 1461#endif
86ed3669
MB		 1462 return ret;
1463}
1464module_init(wm9081_modinit);
1465
1466static void __exit wm9081_exit(void)
1467{
f0fba2ad 1468#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669 1469 i2c_del_driver(&wm9081_i2c_driver);
f0fba2ad 1470#endif
86ed3669
MB		 1471}
1472module_exit(wm9081_exit);
1473
1474
1475MODULE_DESCRIPTION("ASoC WM9081 driver");
1476MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1477MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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