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Linux 3.15-rc1
[deliverable/linux.git] / sound / soc / codecs / wm9081.c
CommitLineData
86ed3669
MB		 1/*
2 * wm9081.c -- WM9081 ALSA SoC Audio driver
3 *
4 * Author: Mark Brown
5 *
656baaeb 6 * Copyright 2009-12 Wolfson Microelectronics plc
86ed3669
MB		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
3ee845ac 18#include <linux/device.h>
86ed3669
MB		 19#include <linux/pm.h>
20#include <linux/i2c.h>
7cfa467b 21#include <linux/regmap.h>
5a0e3ad6 22#include <linux/slab.h>
86ed3669
MB		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
86ed3669
MB		 27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include <sound/wm9081.h>
31#include "wm9081.h"
32
7cfa467b 33static struct reg_default wm9081_reg[] = {
7cfa467b
MB		 34 { 2, 0x00B9 }, /* R2 - Analogue Lineout */
35 { 3, 0x00B9 }, /* R3 - Analogue Speaker PGA */
36 { 4, 0x0001 }, /* R4 - VMID Control */
37 { 5, 0x0068 }, /* R5 - Bias Control 1 */
38 { 7, 0x0000 }, /* R7 - Analogue Mixer */
39 { 8, 0x0000 }, /* R8 - Anti Pop Control */
40 { 9, 0x01DB }, /* R9 - Analogue Speaker 1 */
41 { 10, 0x0018 }, /* R10 - Analogue Speaker 2 */
42 { 11, 0x0180 }, /* R11 - Power Management */
43 { 12, 0x0000 }, /* R12 - Clock Control 1 */
44 { 13, 0x0038 }, /* R13 - Clock Control 2 */
45 { 14, 0x4000 }, /* R14 - Clock Control 3 */
46 { 16, 0x0000 }, /* R16 - FLL Control 1 */
47 { 17, 0x0200 }, /* R17 - FLL Control 2 */
48 { 18, 0x0000 }, /* R18 - FLL Control 3 */
49 { 19, 0x0204 }, /* R19 - FLL Control 4 */
50 { 20, 0x0000 }, /* R20 - FLL Control 5 */
51 { 22, 0x0000 }, /* R22 - Audio Interface 1 */
52 { 23, 0x0002 }, /* R23 - Audio Interface 2 */
53 { 24, 0x0008 }, /* R24 - Audio Interface 3 */
54 { 25, 0x0022 }, /* R25 - Audio Interface 4 */
55 { 27, 0x0006 }, /* R27 - Interrupt Status Mask */
56 { 28, 0x0000 }, /* R28 - Interrupt Polarity */
57 { 29, 0x0000 }, /* R29 - Interrupt Control */
58 { 30, 0x00C0 }, /* R30 - DAC Digital 1 */
59 { 31, 0x0008 }, /* R31 - DAC Digital 2 */
60 { 32, 0x09AF }, /* R32 - DRC 1 */
61 { 33, 0x4201 }, /* R33 - DRC 2 */
62 { 34, 0x0000 }, /* R34 - DRC 3 */
63 { 35, 0x0000 }, /* R35 - DRC 4 */
64 { 38, 0x0000 }, /* R38 - Write Sequencer 1 */
65 { 39, 0x0000 }, /* R39 - Write Sequencer 2 */
66 { 40, 0x0002 }, /* R40 - MW Slave 1 */
67 { 42, 0x0000 }, /* R42 - EQ 1 */
68 { 43, 0x0000 }, /* R43 - EQ 2 */
69 { 44, 0x0FCA }, /* R44 - EQ 3 */
70 { 45, 0x0400 }, /* R45 - EQ 4 */
71 { 46, 0x00B8 }, /* R46 - EQ 5 */
72 { 47, 0x1EB5 }, /* R47 - EQ 6 */
73 { 48, 0xF145 }, /* R48 - EQ 7 */
74 { 49, 0x0B75 }, /* R49 - EQ 8 */
75 { 50, 0x01C5 }, /* R50 - EQ 9 */
76 { 51, 0x169E }, /* R51 - EQ 10 */
77 { 52, 0xF829 }, /* R52 - EQ 11 */
78 { 53, 0x07AD }, /* R53 - EQ 12 */
79 { 54, 0x1103 }, /* R54 - EQ 13 */
80 { 55, 0x1C58 }, /* R55 - EQ 14 */
81 { 56, 0xF373 }, /* R56 - EQ 15 */
82 { 57, 0x0A54 }, /* R57 - EQ 16 */
83 { 58, 0x0558 }, /* R58 - EQ 17 */
84 { 59, 0x0564 }, /* R59 - EQ 18 */
85 { 60, 0x0559 }, /* R60 - EQ 19 */
86 { 61, 0x4000 }, /* R61 - EQ 20 */
86ed3669
MB		 87};
88
89static struct {
90 int ratio;
91 int clk_sys_rate;
92} clk_sys_rates[] = {
93 { 64, 0 },
94 { 128, 1 },
95 { 192, 2 },
96 { 256, 3 },
97 { 384, 4 },
98 { 512, 5 },
99 { 768, 6 },
100 { 1024, 7 },
101 { 1408, 8 },
102 { 1536, 9 },
103};
104
105static struct {
106 int rate;
107 int sample_rate;
108} sample_rates[] = {
109 { 8000, 0 },
110 { 11025, 1 },
111 { 12000, 2 },
112 { 16000, 3 },
113 { 22050, 4 },
114 { 24000, 5 },
115 { 32000, 6 },
116 { 44100, 7 },
117 { 48000, 8 },
118 { 88200, 9 },
119 { 96000, 10 },
120};
121
122static struct {
123 int div; /* *10 due to .5s */
124 int bclk_div;
125} bclk_divs[] = {
126 { 10, 0 },
127 { 15, 1 },
128 { 20, 2 },
129 { 30, 3 },
130 { 40, 4 },
131 { 50, 5 },
132 { 55, 6 },
133 { 60, 7 },
134 { 80, 8 },
135 { 100, 9 },
136 { 110, 10 },
137 { 120, 11 },
138 { 160, 12 },
139 { 200, 13 },
140 { 220, 14 },
141 { 240, 15 },
142 { 250, 16 },
143 { 300, 17 },
144 { 320, 18 },
145 { 440, 19 },
146 { 480, 20 },
147};
148
149struct wm9081_priv {
7cfa467b 150 struct regmap *regmap;
86ed3669
MB		 151 int sysclk_source;
152 int mclk_rate;
153 int sysclk_rate;
154 int fs;
155 int bclk;
156 int master;
157 int fll_fref;
158 int fll_fout;
e0026bea 159 int tdm_width;
4a5f7bda 160 struct wm9081_pdata pdata;
86ed3669
MB		 161};
162
7cfa467b 163static bool wm9081_volatile_register(struct device *dev, unsigned int reg)
86ed3669
MB		 164{
165 switch (reg) {
8d50e447 166 case WM9081_SOFTWARE_RESET:
f8faadb6 167 case WM9081_INTERRUPT_STATUS:
7cfa467b 168 return true;
86ed3669 169 default:
7cfa467b 170 return false;
86ed3669
MB		 171 }
172}
173
7cfa467b 174static bool wm9081_readable_register(struct device *dev, unsigned int reg)
86ed3669 175{
7cfa467b
MB		 176 switch (reg) {
177 case WM9081_SOFTWARE_RESET:
178 case WM9081_ANALOGUE_LINEOUT:
179 case WM9081_ANALOGUE_SPEAKER_PGA:
180 case WM9081_VMID_CONTROL:
181 case WM9081_BIAS_CONTROL_1:
182 case WM9081_ANALOGUE_MIXER:
183 case WM9081_ANTI_POP_CONTROL:
184 case WM9081_ANALOGUE_SPEAKER_1:
185 case WM9081_ANALOGUE_SPEAKER_2:
186 case WM9081_POWER_MANAGEMENT:
187 case WM9081_CLOCK_CONTROL_1:
188 case WM9081_CLOCK_CONTROL_2:
189 case WM9081_CLOCK_CONTROL_3:
190 case WM9081_FLL_CONTROL_1:
191 case WM9081_FLL_CONTROL_2:
192 case WM9081_FLL_CONTROL_3:
193 case WM9081_FLL_CONTROL_4:
194 case WM9081_FLL_CONTROL_5:
195 case WM9081_AUDIO_INTERFACE_1:
196 case WM9081_AUDIO_INTERFACE_2:
197 case WM9081_AUDIO_INTERFACE_3:
198 case WM9081_AUDIO_INTERFACE_4:
199 case WM9081_INTERRUPT_STATUS:
200 case WM9081_INTERRUPT_STATUS_MASK:
201 case WM9081_INTERRUPT_POLARITY:
202 case WM9081_INTERRUPT_CONTROL:
203 case WM9081_DAC_DIGITAL_1:
204 case WM9081_DAC_DIGITAL_2:
205 case WM9081_DRC_1:
206 case WM9081_DRC_2:
207 case WM9081_DRC_3:
208 case WM9081_DRC_4:
209 case WM9081_WRITE_SEQUENCER_1:
210 case WM9081_WRITE_SEQUENCER_2:
211 case WM9081_MW_SLAVE_1:
212 case WM9081_EQ_1:
213 case WM9081_EQ_2:
214 case WM9081_EQ_3:
215 case WM9081_EQ_4:
216 case WM9081_EQ_5:
217 case WM9081_EQ_6:
218 case WM9081_EQ_7:
219 case WM9081_EQ_8:
220 case WM9081_EQ_9:
221 case WM9081_EQ_10:
222 case WM9081_EQ_11:
223 case WM9081_EQ_12:
224 case WM9081_EQ_13:
225 case WM9081_EQ_14:
226 case WM9081_EQ_15:
227 case WM9081_EQ_16:
228 case WM9081_EQ_17:
229 case WM9081_EQ_18:
230 case WM9081_EQ_19:
231 case WM9081_EQ_20:
232 return true;
233 default:
234 return false;
235 }
236}
237
238static int wm9081_reset(struct regmap *map)
239{
240 return regmap_write(map, WM9081_SOFTWARE_RESET, 0x9081);
86ed3669
MB		 241}
242
243static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
244static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
245static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
246static unsigned int drc_max_tlv[] = {
247 TLV_DB_RANGE_HEAD(4),
248 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
249 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
250 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
251 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
252};
253static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
254static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
255
256static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
257
258static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
259static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
260static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
261
262static const char *drc_high_text[] = {
263 "1",
264 "1/2",
265 "1/4",
266 "1/8",
267 "1/16",
268 "0",
269};
270
aedbfd96 271static SOC_ENUM_SINGLE_DECL(drc_high, WM9081_DRC_3, 3, drc_high_text);
86ed3669
MB		 272
273static const char *drc_low_text[] = {
274 "1",
275 "1/2",
276 "1/4",
277 "1/8",
278 "0",
279};
280
aedbfd96 281static SOC_ENUM_SINGLE_DECL(drc_low, WM9081_DRC_3, 0, drc_low_text);
86ed3669
MB		 282
283static const char *drc_atk_text[] = {
284 "181us",
285 "181us",
286 "363us",
287 "726us",
288 "1.45ms",
289 "2.9ms",
290 "5.8ms",
291 "11.6ms",
292 "23.2ms",
293 "46.4ms",
294 "92.8ms",
295 "185.6ms",
296};
297
aedbfd96 298static SOC_ENUM_SINGLE_DECL(drc_atk, WM9081_DRC_2, 12, drc_atk_text);
86ed3669
MB		 299
300static const char *drc_dcy_text[] = {
301 "186ms",
302 "372ms",
303 "743ms",
304 "1.49s",
305 "2.97s",
306 "5.94s",
307 "11.89s",
308 "23.78s",
309 "47.56s",
310};
311
aedbfd96 312static SOC_ENUM_SINGLE_DECL(drc_dcy, WM9081_DRC_2, 8, drc_dcy_text);
86ed3669
MB		 313
314static const char *drc_qr_dcy_text[] = {
315 "0.725ms",
316 "1.45ms",
317 "5.8ms",
318};
319
aedbfd96 320static SOC_ENUM_SINGLE_DECL(drc_qr_dcy, WM9081_DRC_2, 4, drc_qr_dcy_text);
86ed3669
MB		 321
322static const char *dac_deemph_text[] = {
323 "None",
324 "32kHz",
325 "44.1kHz",
326 "48kHz",
327};
328
aedbfd96
TI		 329static SOC_ENUM_SINGLE_DECL(dac_deemph, WM9081_DAC_DIGITAL_2, 1,
330 dac_deemph_text);
86ed3669
MB		 331
332static const char *speaker_mode_text[] = {
333 "Class D",
334 "Class AB",
335};
336
aedbfd96
TI		 337static SOC_ENUM_SINGLE_DECL(speaker_mode, WM9081_ANALOGUE_SPEAKER_2, 6,
338 speaker_mode_text);
86ed3669
MB		 339
340static int speaker_mode_get(struct snd_kcontrol *kcontrol,
341 struct snd_ctl_elem_value *ucontrol)
342{
343 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
344 unsigned int reg;
345
8d50e447 346 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 347 if (reg & WM9081_SPK_MODE)
348 ucontrol->value.integer.value[0] = 1;
349 else
350 ucontrol->value.integer.value[0] = 0;
351
352 return 0;
353}
354
355/*
356 * Stop any attempts to change speaker mode while the speaker is enabled.
357 *
25985edc 358 * We also have some special anti-pop controls dependent on speaker
86ed3669
MB		 359 * mode which must be changed along with the mode.
360 */
361static int speaker_mode_put(struct snd_kcontrol *kcontrol,
362 struct snd_ctl_elem_value *ucontrol)
363{
364 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
8d50e447
MB		 365 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
366 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 367
368 /* Are we changing anything? */
369 if (ucontrol->value.integer.value[0] ==
370 ((reg2 & WM9081_SPK_MODE) != 0))
371 return 0;
372
373 /* Don't try to change modes while enabled */
374 if (reg_pwr & WM9081_SPK_ENA)
375 return -EINVAL;
376
377 if (ucontrol->value.integer.value[0]) {
378 /* Class AB */
379 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
380 reg2 |= WM9081_SPK_MODE;
381 } else {
382 /* Class D */
383 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
384 reg2 &= ~WM9081_SPK_MODE;
385 }
386
8d50e447 387 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
86ed3669
MB		 388
389 return 0;
390}
391
392static const struct snd_kcontrol_new wm9081_snd_controls[] = {
393SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
394SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
395
396SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
397
398SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
399SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
400SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
401
402SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
403SOC_ENUM("DRC High Slope", drc_high),
404SOC_ENUM("DRC Low Slope", drc_low),
405SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
406SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
407SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
408SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
409SOC_ENUM("DRC Attack", drc_atk),
410SOC_ENUM("DRC Decay", drc_dcy),
411SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
412SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
413SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
414SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
415
416SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
417
418SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
419SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
420SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
421SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
422SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
423 out_tlv),
424SOC_ENUM("DAC Deemphasis", dac_deemph),
425SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
426};
427
428static const struct snd_kcontrol_new wm9081_eq_controls[] = {
429SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
430SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
431SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
432SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
433SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
434};
435
436static const struct snd_kcontrol_new mixer[] = {
437SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
438SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
439SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
440};
441
86ed3669
MB		 442struct _fll_div {
443 u16 fll_fratio;
444 u16 fll_outdiv;
445 u16 fll_clk_ref_div;
446 u16 n;
447 u16 k;
448};
449
450/* The size in bits of the FLL divide multiplied by 10
451 * to allow rounding later */
452#define FIXED_FLL_SIZE ((1 << 16) * 10)
453
454static struct {
455 unsigned int min;
456 unsigned int max;
457 u16 fll_fratio;
458 int ratio;
459} fll_fratios[] = {
460 { 0, 64000, 4, 16 },
461 { 64000, 128000, 3, 8 },
462 { 128000, 256000, 2, 4 },
463 { 256000, 1000000, 1, 2 },
464 { 1000000, 13500000, 0, 1 },
465};
466
467static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
468 unsigned int Fout)
469{
470 u64 Kpart;
471 unsigned int K, Ndiv, Nmod, target;
472 unsigned int div;
473 int i;
474
475 /* Fref must be <=13.5MHz */
476 div = 1;
477 while ((Fref / div) > 13500000) {
478 div *= 2;
479
480 if (div > 8) {
481 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
482 Fref);
483 return -EINVAL;
484 }
485 }
486 fll_div->fll_clk_ref_div = div / 2;
487
488 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
489
490 /* Apply the division for our remaining calculations */
491 Fref /= div;
492
493 /* Fvco should be 90-100MHz; don't check the upper bound */
494 div = 0;
495 target = Fout * 2;
496 while (target < 90000000) {
497 div++;
498 target *= 2;
499 if (div > 7) {
500 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
501 Fout);
502 return -EINVAL;
503 }
504 }
505 fll_div->fll_outdiv = div;
506
507 pr_debug("Fvco=%dHz\n", target);
508
25985edc 509 /* Find an appropriate FLL_FRATIO and factor it out of the target */
86ed3669
MB		 510 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
511 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
512 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
513 target /= fll_fratios[i].ratio;
514 break;
515 }
516 }
517 if (i == ARRAY_SIZE(fll_fratios)) {
518 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
519 return -EINVAL;
520 }
521
522 /* Now, calculate N.K */
523 Ndiv = target / Fref;
524
525 fll_div->n = Ndiv;
526 Nmod = target % Fref;
527 pr_debug("Nmod=%d\n", Nmod);
528
529 /* Calculate fractional part - scale up so we can round. */
530 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
531
532 do_div(Kpart, Fref);
533
534 K = Kpart & 0xFFFFFFFF;
535
536 if ((K % 10) >= 5)
537 K += 5;
538
539 /* Move down to proper range now rounding is done */
540 fll_div->k = K / 10;
541
542 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
543 fll_div->n, fll_div->k,
544 fll_div->fll_fratio, fll_div->fll_outdiv,
545 fll_div->fll_clk_ref_div);
546
547 return 0;
548}
549
550static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
551 unsigned int Fref, unsigned int Fout)
552{
b2c812e2 553 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 554 u16 reg1, reg4, reg5;
555 struct _fll_div fll_div;
556 int ret;
557 int clk_sys_reg;
558
559 /* Any change? */
560 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
561 return 0;
562
563 /* Disable the FLL */
564 if (Fout == 0) {
565 dev_dbg(codec->dev, "FLL disabled\n");
566 wm9081->fll_fref = 0;
567 wm9081->fll_fout = 0;
568
569 return 0;
570 }
571
572 ret = fll_factors(&fll_div, Fref, Fout);
573 if (ret != 0)
574 return ret;
575
8d50e447 576 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
86ed3669
MB		 577 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
578
579 switch (fll_id) {
580 case WM9081_SYSCLK_FLL_MCLK:
581 reg5 |= 0x1;
582 break;
583
584 default:
585 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
586 return -EINVAL;
587 }
588
589 /* Disable CLK_SYS while we reconfigure */
8d50e447 590 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669 591 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 592 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
86ed3669
MB		 593 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
594
595 /* Any FLL configuration change requires that the FLL be
596 * disabled first. */
8d50e447 597 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
86ed3669 598 reg1 &= ~WM9081_FLL_ENA;
8d50e447 599 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669
MB		 600
601 /* Apply the configuration */
602 if (fll_div.k)
603 reg1 |= WM9081_FLL_FRAC_MASK;
604 else
605 reg1 &= ~WM9081_FLL_FRAC_MASK;
8d50e447 606 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669 607
8d50e447 608 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
86ed3669
MB		 609 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
610 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
8d50e447 611 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
86ed3669 612
8d50e447 613 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
86ed3669
MB		 614 reg4 &= ~WM9081_FLL_N_MASK;
615 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
8d50e447 616 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
86ed3669
MB		 617
618 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
619 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
8d50e447 620 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
86ed3669 621
249c5156
MB		 622 /* Set gain to the recommended value */
623 snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
624 WM9081_FLL_GAIN_MASK, 0);
625
86ed3669 626 /* Enable the FLL */
8d50e447 627 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
86ed3669
MB		 628
629 /* Then bring CLK_SYS up again if it was disabled */
630 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 631 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
86ed3669
MB		 632
633 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
634
635 wm9081->fll_fref = Fref;
636 wm9081->fll_fout = Fout;
637
638 return 0;
639}
640
641static int configure_clock(struct snd_soc_codec *codec)
642{
b2c812e2 643 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 644 int new_sysclk, i, target;
645 unsigned int reg;
646 int ret = 0;
647 int mclkdiv = 0;
648 int fll = 0;
649
650 switch (wm9081->sysclk_source) {
651 case WM9081_SYSCLK_MCLK:
652 if (wm9081->mclk_rate > 12225000) {
653 mclkdiv = 1;
654 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
655 } else {
656 wm9081->sysclk_rate = wm9081->mclk_rate;
657 }
658 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
659 break;
660
661 case WM9081_SYSCLK_FLL_MCLK:
662 /* If we have a sample rate calculate a CLK_SYS that
663 * gives us a suitable DAC configuration, plus BCLK.
664 * Ideally we would check to see if we can clock
665 * directly from MCLK and only use the FLL if this is
666 * not the case, though care must be taken with free
667 * running mode.
668 */
669 if (wm9081->master && wm9081->bclk) {
670 /* Make sure we can generate CLK_SYS and BCLK
671 * and that we've got 3MHz for optimal
672 * performance. */
673 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
674 target = wm9081->fs * clk_sys_rates[i].ratio;
0154724d 675 new_sysclk = target;
86ed3669
MB		 676 if (target >= wm9081->bclk &&
677 target > 3000000)
0154724d 678 break;
86ed3669 679 }
4b75e947
MB		 680
681 if (i == ARRAY_SIZE(clk_sys_rates))
682 return -EINVAL;
683
86ed3669
MB		 684 } else if (wm9081->fs) {
685 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
686 new_sysclk = clk_sys_rates[i].ratio
687 * wm9081->fs;
688 if (new_sysclk > 3000000)
689 break;
690 }
4b75e947
MB		 691
692 if (i == ARRAY_SIZE(clk_sys_rates))
693 return -EINVAL;
694
86ed3669
MB		 695 } else {
696 new_sysclk = 12288000;
697 }
698
699 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
700 wm9081->mclk_rate, new_sysclk);
701 if (ret == 0) {
702 wm9081->sysclk_rate = new_sysclk;
703
704 /* Switch SYSCLK over to FLL */
705 fll = 1;
706 } else {
707 wm9081->sysclk_rate = wm9081->mclk_rate;
708 }
709 break;
710
711 default:
712 return -EINVAL;
713 }
714
8d50e447 715 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
86ed3669
MB		 716 if (mclkdiv)
717 reg |= WM9081_MCLKDIV2;
718 else
719 reg &= ~WM9081_MCLKDIV2;
8d50e447 720 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
86ed3669 721
8d50e447 722 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669
MB		 723 if (fll)
724 reg |= WM9081_CLK_SRC_SEL;
725 else
726 reg &= ~WM9081_CLK_SRC_SEL;
8d50e447 727 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
86ed3669
MB		 728
729 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
730
731 return ret;
732}
733
734static int clk_sys_event(struct snd_soc_dapm_widget *w,
735 struct snd_kcontrol *kcontrol, int event)
736{
737 struct snd_soc_codec *codec = w->codec;
b2c812e2 738 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 739
740 /* This should be done on init() for bypass paths */
741 switch (wm9081->sysclk_source) {
742 case WM9081_SYSCLK_MCLK:
743 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
744 break;
745 case WM9081_SYSCLK_FLL_MCLK:
746 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
747 wm9081->mclk_rate);
748 break;
749 default:
750 dev_err(codec->dev, "System clock not configured\n");
751 return -EINVAL;
752 }
753
754 switch (event) {
755 case SND_SOC_DAPM_PRE_PMU:
756 configure_clock(codec);
757 break;
758
759 case SND_SOC_DAPM_POST_PMD:
760 /* Disable the FLL if it's running */
761 wm9081_set_fll(codec, 0, 0, 0);
762 break;
763 }
764
765 return 0;
766}
767
768static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
769SND_SOC_DAPM_INPUT("IN1"),
770SND_SOC_DAPM_INPUT("IN2"),
771
0fb7d0c3 772SND_SOC_DAPM_DAC("DAC", NULL, WM9081_POWER_MANAGEMENT, 0, 0),
86ed3669
MB		 773
774SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
775 mixer, ARRAY_SIZE(mixer)),
776
777SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
778
378a90f4 779SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
4e8e78e3 780SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
86ed3669
MB		 781
782SND_SOC_DAPM_OUTPUT("LINEOUT"),
783SND_SOC_DAPM_OUTPUT("SPKN"),
784SND_SOC_DAPM_OUTPUT("SPKP"),
785
786SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
787 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
788SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
789SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
a04e0c86 790SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT, 7, 0, NULL, 0),
86ed3669
MB		 791};
792
793
149c7b44 794static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
86ed3669
MB		 795 { "DAC", NULL, "CLK_SYS" },
796 { "DAC", NULL, "CLK_DSP" },
0fb7d0c3 797 { "DAC", NULL, "AIF" },
86ed3669
MB		 798
799 { "Mixer", "IN1 Switch", "IN1" },
800 { "Mixer", "IN2 Switch", "IN2" },
801 { "Mixer", "Playback Switch", "DAC" },
802
803 { "LINEOUT PGA", NULL, "Mixer" },
804 { "LINEOUT PGA", NULL, "TOCLK" },
805 { "LINEOUT PGA", NULL, "CLK_SYS" },
806
807 { "LINEOUT", NULL, "LINEOUT PGA" },
808
809 { "Speaker PGA", NULL, "Mixer" },
810 { "Speaker PGA", NULL, "TOCLK" },
811 { "Speaker PGA", NULL, "CLK_SYS" },
812
378a90f4 813 { "Speaker", NULL, "Speaker PGA" },
a04e0c86 814 { "Speaker", NULL, "TSENSE" },
378a90f4
MB		 815
816 { "SPKN", NULL, "Speaker" },
817 { "SPKP", NULL, "Speaker" },
86ed3669
MB		 818};
819
820static int wm9081_set_bias_level(struct snd_soc_codec *codec,
821 enum snd_soc_bias_level level)
822{
da157875
MB		 823 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
824
86ed3669
MB		 825 switch (level) {
826 case SND_SOC_BIAS_ON:
827 break;
828
829 case SND_SOC_BIAS_PREPARE:
830 /* VMID=2*40k */
b4027358
AL		 831 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
832 WM9081_VMID_SEL_MASK, 0x2);
86ed3669
MB		 833
834 /* Normal bias current */
b4027358
AL		 835 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
836 WM9081_STBY_BIAS_ENA, 0);
86ed3669
MB		 837 break;
838
839 case SND_SOC_BIAS_STANDBY:
840 /* Initial cold start */
ce6120cc 841 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
da157875
MB		 842 regcache_cache_only(wm9081->regmap, false);
843 regcache_sync(wm9081->regmap);
844
86ed3669 845 /* Disable LINEOUT discharge */
b4027358
AL		 846 snd_soc_update_bits(codec, WM9081_ANTI_POP_CONTROL,
847 WM9081_LINEOUT_DISCH, 0);
86ed3669
MB		 848
849 /* Select startup bias source */
b4027358
AL		 850 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
851 WM9081_BIAS_SRC | WM9081_BIAS_ENA,
852 WM9081_BIAS_SRC | WM9081_BIAS_ENA);
86ed3669
MB		 853
854 /* VMID 2*4k; Soft VMID ramp enable */
b4027358
AL		 855 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
856 WM9081_VMID_RAMP |
857 WM9081_VMID_SEL_MASK,
858 WM9081_VMID_RAMP | 0x6);
86ed3669
MB		 859
860 mdelay(100);
861
862 /* Normal bias enable & soft start off */
b4027358
AL		 863 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
864 WM9081_VMID_RAMP, 0);
86ed3669
MB		 865
866 /* Standard bias source */
b4027358
AL		 867 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
868 WM9081_BIAS_SRC, 0);
86ed3669
MB		 869 }
870
871 /* VMID 2*240k */
b4027358
AL		 872 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
873 WM9081_VMID_SEL_MASK, 0x04);
86ed3669
MB		 874
875 /* Standby bias current on */
b4027358
AL		 876 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
877 WM9081_STBY_BIAS_ENA,
878 WM9081_STBY_BIAS_ENA);
86ed3669
MB		 879 break;
880
881 case SND_SOC_BIAS_OFF:
adf46362 882 /* Startup bias source and disable bias */
b4027358
AL		 883 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
884 WM9081_BIAS_SRC | WM9081_BIAS_ENA,
885 WM9081_BIAS_SRC);
86ed3669 886
adf46362 887 /* Disable VMID with soft ramping */
b4027358
AL		 888 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
889 WM9081_VMID_RAMP | WM9081_VMID_SEL_MASK,
890 WM9081_VMID_RAMP);
86ed3669
MB		 891
892 /* Actively discharge LINEOUT */
b4027358
AL		 893 snd_soc_update_bits(codec, WM9081_ANTI_POP_CONTROL,
894 WM9081_LINEOUT_DISCH,
895 WM9081_LINEOUT_DISCH);
da157875
MB		 896
897 regcache_cache_only(wm9081->regmap, true);
86ed3669
MB		 898 break;
899 }
900
ce6120cc 901 codec->dapm.bias_level = level;
86ed3669
MB		 902
903 return 0;
904}
905
906static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
907 unsigned int fmt)
908{
909 struct snd_soc_codec *codec = dai->codec;
b2c812e2 910 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 911 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 912
913 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
914 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
915
916 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
917 case SND_SOC_DAIFMT_CBS_CFS:
918 wm9081->master = 0;
919 break;
920 case SND_SOC_DAIFMT_CBS_CFM:
921 aif2 |= WM9081_LRCLK_DIR;
922 wm9081->master = 1;
923 break;
924 case SND_SOC_DAIFMT_CBM_CFS:
925 aif2 |= WM9081_BCLK_DIR;
926 wm9081->master = 1;
927 break;
928 case SND_SOC_DAIFMT_CBM_CFM:
929 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
930 wm9081->master = 1;
931 break;
932 default:
933 return -EINVAL;
934 }
935
936 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
937 case SND_SOC_DAIFMT_DSP_B:
938 aif2 |= WM9081_AIF_LRCLK_INV;
939 case SND_SOC_DAIFMT_DSP_A:
940 aif2 |= 0x3;
941 break;
942 case SND_SOC_DAIFMT_I2S:
943 aif2 |= 0x2;
944 break;
945 case SND_SOC_DAIFMT_RIGHT_J:
946 break;
947 case SND_SOC_DAIFMT_LEFT_J:
948 aif2 |= 0x1;
949 break;
950 default:
951 return -EINVAL;
952 }
953
954 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
955 case SND_SOC_DAIFMT_DSP_A:
956 case SND_SOC_DAIFMT_DSP_B:
957 /* frame inversion not valid for DSP modes */
958 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
959 case SND_SOC_DAIFMT_NB_NF:
960 break;
961 case SND_SOC_DAIFMT_IB_NF:
962 aif2 |= WM9081_AIF_BCLK_INV;
963 break;
964 default:
965 return -EINVAL;
966 }
967 break;
968
969 case SND_SOC_DAIFMT_I2S:
970 case SND_SOC_DAIFMT_RIGHT_J:
971 case SND_SOC_DAIFMT_LEFT_J:
972 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
973 case SND_SOC_DAIFMT_NB_NF:
974 break;
975 case SND_SOC_DAIFMT_IB_IF:
976 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
977 break;
978 case SND_SOC_DAIFMT_IB_NF:
979 aif2 |= WM9081_AIF_BCLK_INV;
980 break;
981 case SND_SOC_DAIFMT_NB_IF:
982 aif2 |= WM9081_AIF_LRCLK_INV;
983 break;
984 default:
985 return -EINVAL;
986 }
987 break;
988 default:
989 return -EINVAL;
990 }
991
8d50e447 992 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
86ed3669
MB		 993
994 return 0;
995}
996
997static int wm9081_hw_params(struct snd_pcm_substream *substream,
998 struct snd_pcm_hw_params *params,
999 struct snd_soc_dai *dai)
1000{
1001 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1002 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 1003 int ret, i, best, best_val, cur_val;
1004 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
1005
8d50e447 1006 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
86ed3669
MB		 1007 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1008
8d50e447 1009 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669 1010
8d50e447 1011 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 1012 aif2 &= ~WM9081_AIF_WL_MASK;
1013
8d50e447 1014 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
86ed3669
MB		 1015 aif3 &= ~WM9081_BCLK_DIV_MASK;
1016
8d50e447 1017 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
86ed3669
MB		 1018 aif4 &= ~WM9081_LRCLK_RATE_MASK;
1019
86ed3669 1020 wm9081->fs = params_rate(params);
86ed3669 1021
e0026bea
MB		 1022 if (wm9081->tdm_width) {
1023 /* If TDM is set up then that fixes our BCLK. */
86ed3669
MB		 1024 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
1025 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
e0026bea
MB		 1026
1027 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
1028 } else {
1029 /* Otherwise work out a BCLK from the sample size */
1030 wm9081->bclk = 2 * wm9081->fs;
1031
1032 switch (params_format(params)) {
1033 case SNDRV_PCM_FORMAT_S16_LE:
1034 wm9081->bclk *= 16;
1035 break;
1036 case SNDRV_PCM_FORMAT_S20_3LE:
1037 wm9081->bclk *= 20;
1038 aif2 |= 0x4;
1039 break;
1040 case SNDRV_PCM_FORMAT_S24_LE:
1041 wm9081->bclk *= 24;
1042 aif2 |= 0x8;
1043 break;
1044 case SNDRV_PCM_FORMAT_S32_LE:
1045 wm9081->bclk *= 32;
1046 aif2 |= 0xc;
1047 break;
1048 default:
1049 return -EINVAL;
1050 }
86ed3669
MB		 1051 }
1052
1053 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1054
1055 ret = configure_clock(codec);
1056 if (ret != 0)
1057 return ret;
1058
1059 /* Select nearest CLK_SYS_RATE */
1060 best = 0;
1061 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1062 - wm9081->fs);
1063 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1064 cur_val = abs((wm9081->sysclk_rate /
a419aef8 1065 clk_sys_rates[i].ratio) - wm9081->fs);
86ed3669
MB		 1066 if (cur_val < best_val) {
1067 best = i;
1068 best_val = cur_val;
1069 }
1070 }
1071 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1072 clk_sys_rates[best].ratio);
1073 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1074 << WM9081_CLK_SYS_RATE_SHIFT);
1075
1076 /* SAMPLE_RATE */
1077 best = 0;
1078 best_val = abs(wm9081->fs - sample_rates[0].rate);
1079 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1080 /* Closest match */
1081 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1082 if (cur_val < best_val) {
1083 best = i;
1084 best_val = cur_val;
1085 }
1086 }
1087 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1088 sample_rates[best].rate);
0154724d
MB		 1089 clk_ctrl2 |= (sample_rates[best].sample_rate
1090 << WM9081_SAMPLE_RATE_SHIFT);
86ed3669
MB		 1091
1092 /* BCLK_DIV */
1093 best = 0;
1094 best_val = INT_MAX;
1095 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1096 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1097 - wm9081->bclk;
1098 if (cur_val < 0) /* Table is sorted */
1099 break;
1100 if (cur_val < best_val) {
1101 best = i;
1102 best_val = cur_val;
1103 }
1104 }
1105 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1106 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1107 bclk_divs[best].div, wm9081->bclk);
1108 aif3 |= bclk_divs[best].bclk_div;
1109
1110 /* LRCLK is a simple fraction of BCLK */
1111 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1112 aif4 |= wm9081->bclk / wm9081->fs;
1113
1114 /* Apply a ReTune Mobile configuration if it's in use */
4a5f7bda
MB		 1115 if (wm9081->pdata.num_retune_configs) {
1116 struct wm9081_pdata *pdata = &wm9081->pdata;
86ed3669
MB		 1117 struct wm9081_retune_mobile_setting *s;
1118 int eq1;
1119
1120 best = 0;
4a5f7bda
MB		 1121 best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
1122 for (i = 0; i < pdata->num_retune_configs; i++) {
1123 cur_val = abs(pdata->retune_configs[i].rate -
1124 wm9081->fs);
86ed3669
MB		 1125 if (cur_val < best_val) {
1126 best_val = cur_val;
1127 best = i;
1128 }
1129 }
4a5f7bda 1130 s = &pdata->retune_configs[best];
86ed3669
MB		 1131
1132 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1133 s->name, s->rate);
1134
1135 /* If the EQ is enabled then disable it while we write out */
8d50e447 1136 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
86ed3669 1137 if (eq1 & WM9081_EQ_ENA)
8d50e447 1138 snd_soc_write(codec, WM9081_EQ_1, 0);
86ed3669
MB		 1139
1140 /* Write out the other values */
1141 for (i = 1; i < ARRAY_SIZE(s->config); i++)
8d50e447 1142 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
86ed3669
MB		 1143
1144 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
8d50e447 1145 snd_soc_write(codec, WM9081_EQ_1, eq1);
86ed3669
MB		 1146 }
1147
8d50e447
MB		 1148 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1149 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1150 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1151 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
86ed3669
MB		 1152
1153 return 0;
1154}
1155
1156static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1157{
1158 struct snd_soc_codec *codec = codec_dai->codec;
1159 unsigned int reg;
1160
8d50e447 1161 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
86ed3669
MB		 1162
1163 if (mute)
1164 reg |= WM9081_DAC_MUTE;
1165 else
1166 reg &= ~WM9081_DAC_MUTE;
1167
8d50e447 1168 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
86ed3669
MB		 1169
1170 return 0;
1171}
1172
da1c6ea6
MB		 1173static int wm9081_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1174 int source, unsigned int freq, int dir)
86ed3669 1175{
b2c812e2 1176 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 1177
1178 switch (clk_id) {
1179 case WM9081_SYSCLK_MCLK:
1180 case WM9081_SYSCLK_FLL_MCLK:
1181 wm9081->sysclk_source = clk_id;
1182 wm9081->mclk_rate = freq;
1183 break;
1184
1185 default:
1186 return -EINVAL;
1187 }
1188
1189 return 0;
1190}
1191
1192static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
a5479e38 1193 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
86ed3669
MB		 1194{
1195 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1196 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 1197 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669
MB		 1198
1199 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1200
e0026bea 1201 if (slots < 0 || slots > 4)
86ed3669
MB		 1202 return -EINVAL;
1203
e0026bea
MB		 1204 wm9081->tdm_width = slot_width;
1205
1206 if (slots == 0)
1207 slots = 1;
1208
86ed3669
MB		 1209 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1210
a5479e38 1211 switch (rx_mask) {
86ed3669
MB		 1212 case 1:
1213 break;
1214 case 2:
1215 aif1 |= 0x10;
1216 break;
1217 case 4:
1218 aif1 |= 0x20;
1219 break;
1220 case 8:
1221 aif1 |= 0x30;
1222 break;
1223 default:
1224 return -EINVAL;
1225 }
1226
8d50e447 1227 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
86ed3669
MB		 1228
1229 return 0;
1230}
1231
1232#define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1233
1234#define WM9081_FORMATS \
1235 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1236 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1237
85e7652d 1238static const struct snd_soc_dai_ops wm9081_dai_ops = {
86ed3669 1239 .hw_params = wm9081_hw_params,
86ed3669
MB		 1240 .set_fmt = wm9081_set_dai_fmt,
1241 .digital_mute = wm9081_digital_mute,
1242 .set_tdm_slot = wm9081_set_tdm_slot,
1243};
1244
1245/* We report two channels because the CODEC processes a stereo signal, even
1246 * though it is only capable of handling a mono output.
1247 */
f0fba2ad
LG		 1248static struct snd_soc_dai_driver wm9081_dai = {
1249 .name = "wm9081-hifi",
86ed3669 1250 .playback = {
0fb7d0c3 1251 .stream_name = "AIF",
86ed3669
MB		 1252 .channels_min = 1,
1253 .channels_max = 2,
1254 .rates = WM9081_RATES,
1255 .formats = WM9081_FORMATS,
1256 },
1257 .ops = &wm9081_dai_ops,
1258};
86ed3669 1259
f0fba2ad 1260static int wm9081_probe(struct snd_soc_codec *codec)
86ed3669 1261{
f0fba2ad 1262 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669 1263
f0fba2ad 1264 /* Enable zero cross by default */
b4027358
AL		 1265 snd_soc_update_bits(codec, WM9081_ANALOGUE_LINEOUT,
1266 WM9081_LINEOUTZC, WM9081_LINEOUTZC);
1267 snd_soc_update_bits(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1268 WM9081_SPKPGAZC, WM9081_SPKPGAZC);
f0fba2ad 1269
4a5f7bda 1270 if (!wm9081->pdata.num_retune_configs) {
86ed3669
MB		 1271 dev_dbg(codec->dev,
1272 "No ReTune Mobile data, using normal EQ\n");
022658be 1273 snd_soc_add_codec_controls(codec, wm9081_eq_controls,
86ed3669
MB		 1274 ARRAY_SIZE(wm9081_eq_controls));
1275 }
1276
5d6be5aa 1277 return 0;
86ed3669
MB		 1278}
1279
f0fba2ad 1280static int wm9081_remove(struct snd_soc_codec *codec)
86ed3669 1281{
f0fba2ad 1282 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
86ed3669
MB		 1283 return 0;
1284}
1285
f0fba2ad 1286static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
86ed3669
MB		 1287 .probe = wm9081_probe,
1288 .remove = wm9081_remove,
63d24b79
MB		 1289
1290 .set_sysclk = wm9081_set_sysclk,
f0fba2ad 1291 .set_bias_level = wm9081_set_bias_level,
63d24b79 1292
da157875
MB		 1293 .idle_bias_off = true,
1294
680fa1f8
MB		 1295 .controls = wm9081_snd_controls,
1296 .num_controls = ARRAY_SIZE(wm9081_snd_controls),
149c7b44
MB		 1297 .dapm_widgets = wm9081_dapm_widgets,
1298 .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
1299 .dapm_routes = wm9081_audio_paths,
1300 .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
86ed3669 1301};
86ed3669 1302
7cfa467b
MB		 1303static const struct regmap_config wm9081_regmap = {
1304 .reg_bits = 8,
1305 .val_bits = 16,
1306
1307 .max_register = WM9081_MAX_REGISTER,
1308 .reg_defaults = wm9081_reg,
1309 .num_reg_defaults = ARRAY_SIZE(wm9081_reg),
1310 .volatile_reg = wm9081_volatile_register,
1311 .readable_reg = wm9081_readable_register,
1312 .cache_type = REGCACHE_RBTREE,
1313};
1314
3f300269 1315#if IS_ENABLED(CONFIG_I2C)
7a79e94e
BP		 1316static int wm9081_i2c_probe(struct i2c_client *i2c,
1317 const struct i2c_device_id *id)
86ed3669
MB		 1318{
1319 struct wm9081_priv *wm9081;
7cfa467b 1320 unsigned int reg;
f0fba2ad 1321 int ret;
86ed3669 1322
897f7847
MB		 1323 wm9081 = devm_kzalloc(&i2c->dev, sizeof(struct wm9081_priv),
1324 GFP_KERNEL);
86ed3669
MB		 1325 if (wm9081 == NULL)
1326 return -ENOMEM;
1327
86ed3669 1328 i2c_set_clientdata(i2c, wm9081);
7cfa467b 1329
a5710c01 1330 wm9081->regmap = devm_regmap_init_i2c(i2c, &wm9081_regmap);
7cfa467b
MB		 1331 if (IS_ERR(wm9081->regmap)) {
1332 ret = PTR_ERR(wm9081->regmap);
1333 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
a5710c01 1334 return ret;
7cfa467b
MB		 1335 }
1336
1337 ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, &reg);
1338 if (ret != 0) {
1339 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
a5710c01 1340 return ret;
7cfa467b
MB		 1341 }
1342 if (reg != 0x9081) {
1343 dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg);
a5710c01 1344 return -EINVAL;
7cfa467b
MB		 1345 }
1346
1347 ret = wm9081_reset(wm9081->regmap);
1348 if (ret < 0) {
1349 dev_err(&i2c->dev, "Failed to issue reset\n");
a5710c01 1350 return ret;
7cfa467b 1351 }
86ed3669 1352
3ee845ac 1353 if (dev_get_platdata(&i2c->dev))
4a5f7bda
MB		 1354 memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
1355 sizeof(wm9081->pdata));
3ee845ac 1356
68fcde97
MB		 1357 reg = 0;
1358 if (wm9081->pdata.irq_high)
1359 reg |= WM9081_IRQ_POL;
1360 if (!wm9081->pdata.irq_cmos)
1361 reg |= WM9081_IRQ_OP_CTRL;
1362 regmap_update_bits(wm9081->regmap, WM9081_INTERRUPT_CONTROL,
1363 WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
1364
da157875 1365 regcache_cache_only(wm9081->regmap, true);
68fcde97 1366
f0fba2ad
LG		 1367 ret = snd_soc_register_codec(&i2c->dev,
1368 &soc_codec_dev_wm9081, &wm9081_dai, 1);
1369 if (ret < 0)
a5710c01 1370 return ret;
7cfa467b
MB		 1371
1372 return 0;
86ed3669
MB		 1373}
1374
7a79e94e 1375static int wm9081_i2c_remove(struct i2c_client *client)
86ed3669 1376{
f0fba2ad 1377 snd_soc_unregister_codec(&client->dev);
86ed3669
MB		 1378 return 0;
1379}
1380
1381static const struct i2c_device_id wm9081_i2c_id[] = {
1382 { "wm9081", 0 },
1383 { }
1384};
1385MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1386
1387static struct i2c_driver wm9081_i2c_driver = {
1388 .driver = {
2031c064 1389 .name = "wm9081",
86ed3669
MB		 1390 .owner = THIS_MODULE,
1391 },
1392 .probe = wm9081_i2c_probe,
7a79e94e 1393 .remove = wm9081_i2c_remove,
86ed3669
MB		 1394 .id_table = wm9081_i2c_id,
1395};
f0fba2ad 1396#endif
86ed3669 1397
2dbc34d8 1398module_i2c_driver(wm9081_i2c_driver);
86ed3669
MB		 1399
1400MODULE_DESCRIPTION("ASoC WM9081 driver");
1401MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1402MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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