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ASoC: wm_adsp: Attach buffers and streams together
[deliverable/linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
cf17c83c 18#include <linux/list.h>
2159ad93
MB		 19#include <linux/pm.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
973838a0 22#include <linux/regulator/consumer.h>
2159ad93 23#include <linux/slab.h>
cdcd7f72 24#include <linux/vmalloc.h>
6ab2b7b4 25#include <linux/workqueue.h>
f9f55e31 26#include <linux/debugfs.h>
2159ad93
MB		 27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/jack.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34
35#include <linux/mfd/arizona/registers.h>
36
dc91428a 37#include "arizona.h"
2159ad93
MB		 38#include "wm_adsp.h"
39
40#define adsp_crit(_dsp, fmt, ...) \
41 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
42#define adsp_err(_dsp, fmt, ...) \
43 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
44#define adsp_warn(_dsp, fmt, ...) \
45 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46#define adsp_info(_dsp, fmt, ...) \
47 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
48#define adsp_dbg(_dsp, fmt, ...) \
49 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
50
51#define ADSP1_CONTROL_1 0x00
52#define ADSP1_CONTROL_2 0x02
53#define ADSP1_CONTROL_3 0x03
54#define ADSP1_CONTROL_4 0x04
55#define ADSP1_CONTROL_5 0x06
56#define ADSP1_CONTROL_6 0x07
57#define ADSP1_CONTROL_7 0x08
58#define ADSP1_CONTROL_8 0x09
59#define ADSP1_CONTROL_9 0x0A
60#define ADSP1_CONTROL_10 0x0B
61#define ADSP1_CONTROL_11 0x0C
62#define ADSP1_CONTROL_12 0x0D
63#define ADSP1_CONTROL_13 0x0F
64#define ADSP1_CONTROL_14 0x10
65#define ADSP1_CONTROL_15 0x11
66#define ADSP1_CONTROL_16 0x12
67#define ADSP1_CONTROL_17 0x13
68#define ADSP1_CONTROL_18 0x14
69#define ADSP1_CONTROL_19 0x16
70#define ADSP1_CONTROL_20 0x17
71#define ADSP1_CONTROL_21 0x18
72#define ADSP1_CONTROL_22 0x1A
73#define ADSP1_CONTROL_23 0x1B
74#define ADSP1_CONTROL_24 0x1C
75#define ADSP1_CONTROL_25 0x1E
76#define ADSP1_CONTROL_26 0x20
77#define ADSP1_CONTROL_27 0x21
78#define ADSP1_CONTROL_28 0x22
79#define ADSP1_CONTROL_29 0x23
80#define ADSP1_CONTROL_30 0x24
81#define ADSP1_CONTROL_31 0x26
82
83/*
84 * ADSP1 Control 19
85 */
86#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
87#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
88#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
89
90
91/*
92 * ADSP1 Control 30
93 */
94#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
95#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
96#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
97#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
98#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
99#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
100#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
101#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
102#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
103#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
104#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
105#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
106#define ADSP1_START 0x0001 /* DSP1_START */
107#define ADSP1_START_MASK 0x0001 /* DSP1_START */
108#define ADSP1_START_SHIFT 0 /* DSP1_START */
109#define ADSP1_START_WIDTH 1 /* DSP1_START */
110
94e205bf
CR		 111/*
112 * ADSP1 Control 31
113 */
114#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
115#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
116#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
117
2d30b575
MB		 118#define ADSP2_CONTROL 0x0
119#define ADSP2_CLOCKING 0x1
120#define ADSP2_STATUS1 0x4
121#define ADSP2_WDMA_CONFIG_1 0x30
122#define ADSP2_WDMA_CONFIG_2 0x31
123#define ADSP2_RDMA_CONFIG_1 0x34
2159ad93 124
10337b07
RF		 125#define ADSP2_SCRATCH0 0x40
126#define ADSP2_SCRATCH1 0x41
127#define ADSP2_SCRATCH2 0x42
128#define ADSP2_SCRATCH3 0x43
129
2159ad93
MB		 130/*
131 * ADSP2 Control
132 */
133
134#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
135#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
136#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
137#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
138#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
139#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
140#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
141#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
142#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
143#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
144#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
145#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
146#define ADSP2_START 0x0001 /* DSP1_START */
147#define ADSP2_START_MASK 0x0001 /* DSP1_START */
148#define ADSP2_START_SHIFT 0 /* DSP1_START */
149#define ADSP2_START_WIDTH 1 /* DSP1_START */
150
973838a0
MB		 151/*
152 * ADSP2 clocking
153 */
154#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
155#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
156#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
157
2159ad93
MB		 158/*
159 * ADSP2 Status 1
160 */
161#define ADSP2_RAM_RDY 0x0001
162#define ADSP2_RAM_RDY_MASK 0x0001
163#define ADSP2_RAM_RDY_SHIFT 0
164#define ADSP2_RAM_RDY_WIDTH 1
165
cf17c83c
MB		 166struct wm_adsp_buf {
167 struct list_head list;
168 void *buf;
169};
170
171static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
172 struct list_head *list)
173{
174 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
175
176 if (buf == NULL)
177 return NULL;
178
cdcd7f72 179 buf->buf = vmalloc(len);
cf17c83c 180 if (!buf->buf) {
cdcd7f72 181 vfree(buf);
cf17c83c
MB		 182 return NULL;
183 }
cdcd7f72 184 memcpy(buf->buf, src, len);
cf17c83c
MB		 185
186 if (list)
187 list_add_tail(&buf->list, list);
188
189 return buf;
190}
191
192static void wm_adsp_buf_free(struct list_head *list)
193{
194 while (!list_empty(list)) {
195 struct wm_adsp_buf *buf = list_first_entry(list,
196 struct wm_adsp_buf,
197 list);
198 list_del(&buf->list);
cdcd7f72 199 vfree(buf->buf);
cf17c83c
MB		 200 kfree(buf);
201 }
202}
203
04d1300f
CK		 204#define WM_ADSP_FW_MBC_VSS 0
205#define WM_ADSP_FW_HIFI 1
206#define WM_ADSP_FW_TX 2
207#define WM_ADSP_FW_TX_SPK 3
208#define WM_ADSP_FW_RX 4
209#define WM_ADSP_FW_RX_ANC 5
210#define WM_ADSP_FW_CTRL 6
211#define WM_ADSP_FW_ASR 7
212#define WM_ADSP_FW_TRACE 8
213#define WM_ADSP_FW_SPK_PROT 9
214#define WM_ADSP_FW_MISC 10
215
216#define WM_ADSP_NUM_FW 11
dd84f925 217
1023dbd9 218static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
04d1300f
CK		 219 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
220 [WM_ADSP_FW_HIFI] = "MasterHiFi",
221 [WM_ADSP_FW_TX] = "Tx",
222 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
223 [WM_ADSP_FW_RX] = "Rx",
224 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
225 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
226 [WM_ADSP_FW_ASR] = "ASR Assist",
227 [WM_ADSP_FW_TRACE] = "Dbg Trace",
228 [WM_ADSP_FW_SPK_PROT] = "Protection",
229 [WM_ADSP_FW_MISC] = "Misc",
1023dbd9
MB		 230};
231
2cd19bdb
CK		 232struct wm_adsp_system_config_xm_hdr {
233 __be32 sys_enable;
234 __be32 fw_id;
235 __be32 fw_rev;
236 __be32 boot_status;
237 __be32 watchdog;
238 __be32 dma_buffer_size;
239 __be32 rdma[6];
240 __be32 wdma[8];
241 __be32 build_job_name[3];
242 __be32 build_job_number;
243};
244
245struct wm_adsp_alg_xm_struct {
246 __be32 magic;
247 __be32 smoothing;
248 __be32 threshold;
249 __be32 host_buf_ptr;
250 __be32 start_seq;
251 __be32 high_water_mark;
252 __be32 low_water_mark;
253 __be64 smoothed_power;
254};
255
256struct wm_adsp_buffer {
257 __be32 X_buf_base; /* XM base addr of first X area */
258 __be32 X_buf_size; /* Size of 1st X area in words */
259 __be32 X_buf_base2; /* XM base addr of 2nd X area */
260 __be32 X_buf_brk; /* Total X size in words */
261 __be32 Y_buf_base; /* YM base addr of Y area */
262 __be32 wrap; /* Total size X and Y in words */
263 __be32 high_water_mark; /* Point at which IRQ is asserted */
264 __be32 irq_count; /* bits 1-31 count IRQ assertions */
265 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
266 __be32 next_write_index; /* word index of next write */
267 __be32 next_read_index; /* word index of next read */
268 __be32 error; /* error if any */
269 __be32 oldest_block_index; /* word index of oldest surviving */
270 __be32 requested_rewind; /* how many blocks rewind was done */
271 __be32 reserved_space; /* internal */
272 __be32 min_free; /* min free space since stream start */
273 __be32 blocks_written[2]; /* total blocks written (64 bit) */
274 __be32 words_written[2]; /* total words written (64 bit) */
275};
276
277struct wm_adsp_compr_buf {
278 struct wm_adsp *dsp;
279
280 struct wm_adsp_buffer_region *regions;
281 u32 host_buf_ptr;
282};
283
406abc95
CK		 284struct wm_adsp_compr {
285 struct wm_adsp *dsp;
95fe9597 286 struct wm_adsp_compr_buf *buf;
406abc95
CK		 287
288 struct snd_compr_stream *stream;
289 struct snd_compressed_buffer size;
290};
291
292#define WM_ADSP_DATA_WORD_SIZE 3
293
294#define WM_ADSP_MIN_FRAGMENTS 1
295#define WM_ADSP_MAX_FRAGMENTS 256
296#define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
297#define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
298
2cd19bdb
CK		 299#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
300
301#define HOST_BUFFER_FIELD(field) \
302 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
303
304#define ALG_XM_FIELD(field) \
305 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
306
307static int wm_adsp_buffer_init(struct wm_adsp *dsp);
308static int wm_adsp_buffer_free(struct wm_adsp *dsp);
309
310struct wm_adsp_buffer_region {
311 unsigned int offset;
312 unsigned int cumulative_size;
313 unsigned int mem_type;
314 unsigned int base_addr;
315};
316
317struct wm_adsp_buffer_region_def {
318 unsigned int mem_type;
319 unsigned int base_offset;
320 unsigned int size_offset;
321};
322
323static struct wm_adsp_buffer_region_def ez2control_regions[] = {
324 {
325 .mem_type = WMFW_ADSP2_XM,
326 .base_offset = HOST_BUFFER_FIELD(X_buf_base),
327 .size_offset = HOST_BUFFER_FIELD(X_buf_size),
328 },
329 {
330 .mem_type = WMFW_ADSP2_XM,
331 .base_offset = HOST_BUFFER_FIELD(X_buf_base2),
332 .size_offset = HOST_BUFFER_FIELD(X_buf_brk),
333 },
334 {
335 .mem_type = WMFW_ADSP2_YM,
336 .base_offset = HOST_BUFFER_FIELD(Y_buf_base),
337 .size_offset = HOST_BUFFER_FIELD(wrap),
338 },
339};
340
406abc95
CK		 341struct wm_adsp_fw_caps {
342 u32 id;
343 struct snd_codec_desc desc;
2cd19bdb
CK		 344 int num_regions;
345 struct wm_adsp_buffer_region_def *region_defs;
406abc95
CK		 346};
347
348static const struct wm_adsp_fw_caps ez2control_caps[] = {
349 {
350 .id = SND_AUDIOCODEC_BESPOKE,
351 .desc = {
352 .max_ch = 1,
353 .sample_rates = { 16000 },
354 .num_sample_rates = 1,
355 .formats = SNDRV_PCM_FMTBIT_S16_LE,
356 },
2cd19bdb
CK		 357 .num_regions = ARRAY_SIZE(ez2control_regions),
358 .region_defs = ez2control_regions,
406abc95
CK		 359 },
360};
361
362static const struct {
1023dbd9 363 const char *file;
406abc95
CK		 364 int compr_direction;
365 int num_caps;
366 const struct wm_adsp_fw_caps *caps;
1023dbd9 367} wm_adsp_fw[WM_ADSP_NUM_FW] = {
04d1300f
CK		 368 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
369 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
370 [WM_ADSP_FW_TX] = { .file = "tx" },
371 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
372 [WM_ADSP_FW_RX] = { .file = "rx" },
373 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
406abc95
CK		 374 [WM_ADSP_FW_CTRL] = {
375 .file = "ctrl",
376 .compr_direction = SND_COMPRESS_CAPTURE,
377 .num_caps = ARRAY_SIZE(ez2control_caps),
378 .caps = ez2control_caps,
379 },
04d1300f
CK		 380 [WM_ADSP_FW_ASR] = { .file = "asr" },
381 [WM_ADSP_FW_TRACE] = { .file = "trace" },
382 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
383 [WM_ADSP_FW_MISC] = { .file = "misc" },
1023dbd9
MB		 384};
385
6ab2b7b4
DP		 386struct wm_coeff_ctl_ops {
387 int (*xget)(struct snd_kcontrol *kcontrol,
388 struct snd_ctl_elem_value *ucontrol);
389 int (*xput)(struct snd_kcontrol *kcontrol,
390 struct snd_ctl_elem_value *ucontrol);
391 int (*xinfo)(struct snd_kcontrol *kcontrol,
392 struct snd_ctl_elem_info *uinfo);
393};
394
6ab2b7b4
DP		 395struct wm_coeff_ctl {
396 const char *name;
2323736d 397 const char *fw_name;
3809f001 398 struct wm_adsp_alg_region alg_region;
6ab2b7b4 399 struct wm_coeff_ctl_ops ops;
3809f001 400 struct wm_adsp *dsp;
6ab2b7b4
DP		 401 unsigned int enabled:1;
402 struct list_head list;
403 void *cache;
2323736d 404 unsigned int offset;
6ab2b7b4 405 size_t len;
0c2e3f34 406 unsigned int set:1;
6ab2b7b4 407 struct snd_kcontrol *kcontrol;
26c22a19 408 unsigned int flags;
6ab2b7b4
DP		 409};
410
f9f55e31
RF		 411#ifdef CONFIG_DEBUG_FS
412static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
413{
414 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
415
f9f55e31
RF		 416 kfree(dsp->wmfw_file_name);
417 dsp->wmfw_file_name = tmp;
f9f55e31
RF		 418}
419
420static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
421{
422 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
423
f9f55e31
RF		 424 kfree(dsp->bin_file_name);
425 dsp->bin_file_name = tmp;
f9f55e31
RF		 426}
427
428static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
429{
f9f55e31
RF		 430 kfree(dsp->wmfw_file_name);
431 kfree(dsp->bin_file_name);
432 dsp->wmfw_file_name = NULL;
433 dsp->bin_file_name = NULL;
f9f55e31
RF		 434}
435
436static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
437 char __user *user_buf,
438 size_t count, loff_t *ppos)
439{
440 struct wm_adsp *dsp = file->private_data;
441 ssize_t ret;
442
078e7183 443 mutex_lock(&dsp->pwr_lock);
f9f55e31
RF		 444
445 if (!dsp->wmfw_file_name || !dsp->running)
446 ret = 0;
447 else
448 ret = simple_read_from_buffer(user_buf, count, ppos,
449 dsp->wmfw_file_name,
450 strlen(dsp->wmfw_file_name));
451
078e7183 452 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 453 return ret;
454}
455
456static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
457 char __user *user_buf,
458 size_t count, loff_t *ppos)
459{
460 struct wm_adsp *dsp = file->private_data;
461 ssize_t ret;
462
078e7183 463 mutex_lock(&dsp->pwr_lock);
f9f55e31
RF		 464
465 if (!dsp->bin_file_name || !dsp->running)
466 ret = 0;
467 else
468 ret = simple_read_from_buffer(user_buf, count, ppos,
469 dsp->bin_file_name,
470 strlen(dsp->bin_file_name));
471
078e7183 472 mutex_unlock(&dsp->pwr_lock);
f9f55e31
RF		 473 return ret;
474}
475
476static const struct {
477 const char *name;
478 const struct file_operations fops;
479} wm_adsp_debugfs_fops[] = {
480 {
481 .name = "wmfw_file_name",
482 .fops = {
483 .open = simple_open,
484 .read = wm_adsp_debugfs_wmfw_read,
485 },
486 },
487 {
488 .name = "bin_file_name",
489 .fops = {
490 .open = simple_open,
491 .read = wm_adsp_debugfs_bin_read,
492 },
493 },
494};
495
496static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
497 struct snd_soc_codec *codec)
498{
499 struct dentry *root = NULL;
500 char *root_name;
501 int i;
502
503 if (!codec->component.debugfs_root) {
504 adsp_err(dsp, "No codec debugfs root\n");
505 goto err;
506 }
507
508 root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
509 if (!root_name)
510 goto err;
511
512 snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
513 root = debugfs_create_dir(root_name, codec->component.debugfs_root);
514 kfree(root_name);
515
516 if (!root)
517 goto err;
518
519 if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running))
520 goto err;
521
522 if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id))
523 goto err;
524
525 if (!debugfs_create_x32("fw_version", S_IRUGO, root,
526 &dsp->fw_id_version))
527 goto err;
528
529 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
530 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
531 S_IRUGO, root, dsp,
532 &wm_adsp_debugfs_fops[i].fops))
533 goto err;
534 }
535
536 dsp->debugfs_root = root;
537 return;
538
539err:
540 debugfs_remove_recursive(root);
541 adsp_err(dsp, "Failed to create debugfs\n");
542}
543
544static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
545{
546 wm_adsp_debugfs_clear(dsp);
547 debugfs_remove_recursive(dsp->debugfs_root);
548}
549#else
550static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
551 struct snd_soc_codec *codec)
552{
553}
554
555static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
556{
557}
558
559static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
560 const char *s)
561{
562}
563
564static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
565 const char *s)
566{
567}
568
569static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
570{
571}
572#endif
573
1023dbd9
MB		 574static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
575 struct snd_ctl_elem_value *ucontrol)
576{
ea53bf77 577 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 578 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 579 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
1023dbd9 580
3809f001 581 ucontrol->value.integer.value[0] = dsp[e->shift_l].fw;
1023dbd9
MB		 582
583 return 0;
584}
585
586static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
587 struct snd_ctl_elem_value *ucontrol)
588{
ea53bf77 589 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1023dbd9 590 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3809f001 591 struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
d27c5e15 592 int ret = 0;
1023dbd9 593
3809f001 594 if (ucontrol->value.integer.value[0] == dsp[e->shift_l].fw)
1023dbd9
MB		 595 return 0;
596
597 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
598 return -EINVAL;
599
d27c5e15
CK		 600 mutex_lock(&dsp[e->shift_l].pwr_lock);
601
406abc95 602 if (dsp[e->shift_l].running || dsp[e->shift_l].compr)
d27c5e15
CK		 603 ret = -EBUSY;
604 else
605 dsp[e->shift_l].fw = ucontrol->value.integer.value[0];
1023dbd9 606
d27c5e15 607 mutex_unlock(&dsp[e->shift_l].pwr_lock);
1023dbd9 608
d27c5e15 609 return ret;
1023dbd9
MB		 610}
611
612static const struct soc_enum wm_adsp_fw_enum[] = {
613 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
614 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
615 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
616 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
617};
618
336d0442 619const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
1023dbd9
MB		 620 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
621 wm_adsp_fw_get, wm_adsp_fw_put),
622 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
623 wm_adsp_fw_get, wm_adsp_fw_put),
624 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
625 wm_adsp_fw_get, wm_adsp_fw_put),
336d0442
RF		 626 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
627 wm_adsp_fw_get, wm_adsp_fw_put),
b6ed61cf 628};
336d0442 629EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
2159ad93
MB		 630
631static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
632 int type)
633{
634 int i;
635
636 for (i = 0; i < dsp->num_mems; i++)
637 if (dsp->mem[i].type == type)
638 return &dsp->mem[i];
639
640 return NULL;
641}
642
3809f001 643static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
45b9ee72
MB		 644 unsigned int offset)
645{
3809f001 646 if (WARN_ON(!mem))
6c452bda 647 return offset;
3809f001 648 switch (mem->type) {
45b9ee72 649 case WMFW_ADSP1_PM:
3809f001 650 return mem->base + (offset * 3);
45b9ee72 651 case WMFW_ADSP1_DM:
3809f001 652 return mem->base + (offset * 2);
45b9ee72 653 case WMFW_ADSP2_XM:
3809f001 654 return mem->base + (offset * 2);
45b9ee72 655 case WMFW_ADSP2_YM:
3809f001 656 return mem->base + (offset * 2);
45b9ee72 657 case WMFW_ADSP1_ZM:
3809f001 658 return mem->base + (offset * 2);
45b9ee72 659 default:
6c452bda 660 WARN(1, "Unknown memory region type");
45b9ee72
MB		 661 return offset;
662 }
663}
664
10337b07
RF		 665static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
666{
667 u16 scratch[4];
668 int ret;
669
670 ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
671 scratch, sizeof(scratch));
672 if (ret) {
673 adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
674 return;
675 }
676
677 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
678 be16_to_cpu(scratch[0]),
679 be16_to_cpu(scratch[1]),
680 be16_to_cpu(scratch[2]),
681 be16_to_cpu(scratch[3]));
682}
683
7585a5b0 684static int wm_coeff_info(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 685 struct snd_ctl_elem_info *uinfo)
686{
7585a5b0 687 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4
DP		 688
689 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
690 uinfo->count = ctl->len;
691 return 0;
692}
693
c9f8dd71 694static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 695 const void *buf, size_t len)
696{
3809f001 697 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 698 const struct wm_adsp_region *mem;
3809f001 699 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 700 void *scratch;
701 int ret;
702 unsigned int reg;
703
3809f001 704 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 705 if (!mem) {
3809f001
CK		 706 adsp_err(dsp, "No base for region %x\n",
707 alg_region->type);
6ab2b7b4
DP		 708 return -EINVAL;
709 }
710
2323736d 711 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 712 reg = wm_adsp_region_to_reg(mem, reg);
713
714 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
715 if (!scratch)
716 return -ENOMEM;
717
3809f001 718 ret = regmap_raw_write(dsp->regmap, reg, scratch,
6ab2b7b4
DP		 719 ctl->len);
720 if (ret) {
3809f001 721 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
43bc3bf6 722 ctl->len, reg, ret);
6ab2b7b4
DP		 723 kfree(scratch);
724 return ret;
725 }
3809f001 726 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", ctl->len, reg);
6ab2b7b4
DP		 727
728 kfree(scratch);
729
730 return 0;
731}
732
7585a5b0 733static int wm_coeff_put(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 734 struct snd_ctl_elem_value *ucontrol)
735{
7585a5b0 736 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4 737 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 738 int ret = 0;
739
740 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4
DP		 741
742 memcpy(ctl->cache, p, ctl->len);
743
65d17a9c 744 ctl->set = 1;
168d10e7
CK		 745 if (ctl->enabled)
746 ret = wm_coeff_write_control(ctl, p, ctl->len);
6ab2b7b4 747
168d10e7
CK		 748 mutex_unlock(&ctl->dsp->pwr_lock);
749
750 return ret;
6ab2b7b4
DP		 751}
752
c9f8dd71 753static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
6ab2b7b4
DP		 754 void *buf, size_t len)
755{
3809f001 756 struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
6ab2b7b4 757 const struct wm_adsp_region *mem;
3809f001 758 struct wm_adsp *dsp = ctl->dsp;
6ab2b7b4
DP		 759 void *scratch;
760 int ret;
761 unsigned int reg;
762
3809f001 763 mem = wm_adsp_find_region(dsp, alg_region->type);
6ab2b7b4 764 if (!mem) {
3809f001
CK		 765 adsp_err(dsp, "No base for region %x\n",
766 alg_region->type);
6ab2b7b4
DP		 767 return -EINVAL;
768 }
769
2323736d 770 reg = ctl->alg_region.base + ctl->offset;
6ab2b7b4
DP		 771 reg = wm_adsp_region_to_reg(mem, reg);
772
773 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
774 if (!scratch)
775 return -ENOMEM;
776
3809f001 777 ret = regmap_raw_read(dsp->regmap, reg, scratch, ctl->len);
6ab2b7b4 778 if (ret) {
3809f001 779 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
43bc3bf6 780 ctl->len, reg, ret);
6ab2b7b4
DP		 781 kfree(scratch);
782 return ret;
783 }
3809f001 784 adsp_dbg(dsp, "Read %zu bytes from %x\n", ctl->len, reg);
6ab2b7b4
DP		 785
786 memcpy(buf, scratch, ctl->len);
787 kfree(scratch);
788
789 return 0;
790}
791
7585a5b0 792static int wm_coeff_get(struct snd_kcontrol *kctl,
6ab2b7b4
DP		 793 struct snd_ctl_elem_value *ucontrol)
794{
7585a5b0 795 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kctl->private_value;
6ab2b7b4 796 char *p = ucontrol->value.bytes.data;
168d10e7
CK		 797 int ret = 0;
798
799 mutex_lock(&ctl->dsp->pwr_lock);
6ab2b7b4 800
26c22a19
CK		 801 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
802 if (ctl->enabled)
168d10e7 803 ret = wm_coeff_read_control(ctl, p, ctl->len);
26c22a19 804 else
168d10e7
CK		 805 ret = -EPERM;
806 } else {
bc1765d6
CK		 807 if (!ctl->flags && ctl->enabled)
808 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
809
168d10e7 810 memcpy(p, ctl->cache, ctl->len);
26c22a19
CK		 811 }
812
168d10e7 813 mutex_unlock(&ctl->dsp->pwr_lock);
26c22a19 814
168d10e7 815 return ret;
6ab2b7b4
DP		 816}
817
6ab2b7b4 818struct wmfw_ctl_work {
3809f001 819 struct wm_adsp *dsp;
6ab2b7b4
DP		 820 struct wm_coeff_ctl *ctl;
821 struct work_struct work;
822};
823
3809f001 824static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
6ab2b7b4
DP		 825{
826 struct snd_kcontrol_new *kcontrol;
827 int ret;
828
92bb4c32 829 if (!ctl || !ctl->name)
6ab2b7b4
DP		 830 return -EINVAL;
831
832 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
833 if (!kcontrol)
834 return -ENOMEM;
835 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
836
837 kcontrol->name = ctl->name;
838 kcontrol->info = wm_coeff_info;
839 kcontrol->get = wm_coeff_get;
840 kcontrol->put = wm_coeff_put;
841 kcontrol->private_value = (unsigned long)ctl;
842
26c22a19
CK		 843 if (ctl->flags) {
844 if (ctl->flags & WMFW_CTL_FLAG_WRITEABLE)
845 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
846 if (ctl->flags & WMFW_CTL_FLAG_READABLE)
847 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_READ;
848 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
849 kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_VOLATILE;
850 }
851
3809f001 852 ret = snd_soc_add_card_controls(dsp->card,
81ad93ec 853 kcontrol, 1);
6ab2b7b4
DP		 854 if (ret < 0)
855 goto err_kcontrol;
856
857 kfree(kcontrol);
858
3809f001 859 ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card,
81ad93ec
DP		 860 ctl->name);
861
6ab2b7b4
DP		 862 return 0;
863
864err_kcontrol:
865 kfree(kcontrol);
866 return ret;
867}
868
b21acc1c
CK		 869static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
870{
871 struct wm_coeff_ctl *ctl;
872 int ret;
873
874 list_for_each_entry(ctl, &dsp->ctl_list, list) {
875 if (!ctl->enabled || ctl->set)
876 continue;
26c22a19
CK		 877 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
878 continue;
879
b21acc1c
CK		 880 ret = wm_coeff_read_control(ctl,
881 ctl->cache,
882 ctl->len);
883 if (ret < 0)
884 return ret;
885 }
886
887 return 0;
888}
889
890static int wm_coeff_sync_controls(struct wm_adsp *dsp)
891{
892 struct wm_coeff_ctl *ctl;
893 int ret;
894
895 list_for_each_entry(ctl, &dsp->ctl_list, list) {
896 if (!ctl->enabled)
897 continue;
26c22a19 898 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
b21acc1c
CK		 899 ret = wm_coeff_write_control(ctl,
900 ctl->cache,
901 ctl->len);
902 if (ret < 0)
903 return ret;
904 }
905 }
906
907 return 0;
908}
909
910static void wm_adsp_ctl_work(struct work_struct *work)
911{
912 struct wmfw_ctl_work *ctl_work = container_of(work,
913 struct wmfw_ctl_work,
914 work);
915
916 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
917 kfree(ctl_work);
918}
919
920static int wm_adsp_create_control(struct wm_adsp *dsp,
921 const struct wm_adsp_alg_region *alg_region,
2323736d 922 unsigned int offset, unsigned int len,
26c22a19
CK		 923 const char *subname, unsigned int subname_len,
924 unsigned int flags)
b21acc1c
CK		 925{
926 struct wm_coeff_ctl *ctl;
927 struct wmfw_ctl_work *ctl_work;
928 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
929 char *region_name;
930 int ret;
931
26c22a19
CK		 932 if (flags & WMFW_CTL_FLAG_SYS)
933 return 0;
934
b21acc1c
CK		 935 switch (alg_region->type) {
936 case WMFW_ADSP1_PM:
937 region_name = "PM";
938 break;
939 case WMFW_ADSP1_DM:
940 region_name = "DM";
941 break;
942 case WMFW_ADSP2_XM:
943 region_name = "XM";
944 break;
945 case WMFW_ADSP2_YM:
946 region_name = "YM";
947 break;
948 case WMFW_ADSP1_ZM:
949 region_name = "ZM";
950 break;
951 default:
2323736d 952 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
b21acc1c
CK		 953 return -EINVAL;
954 }
955
cb5b57a9
CK		 956 switch (dsp->fw_ver) {
957 case 0:
958 case 1:
959 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
960 dsp->num, region_name, alg_region->alg);
961 break;
962 default:
963 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
964 "DSP%d%c %.12s %x", dsp->num, *region_name,
965 wm_adsp_fw_text[dsp->fw], alg_region->alg);
966
967 /* Truncate the subname from the start if it is too long */
968 if (subname) {
969 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
970 int skip = 0;
971
972 if (subname_len > avail)
973 skip = subname_len - avail;
974
975 snprintf(name + ret,
976 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
977 subname_len - skip, subname + skip);
978 }
979 break;
980 }
b21acc1c 981
7585a5b0 982 list_for_each_entry(ctl, &dsp->ctl_list, list) {
b21acc1c
CK		 983 if (!strcmp(ctl->name, name)) {
984 if (!ctl->enabled)
985 ctl->enabled = 1;
986 return 0;
987 }
988 }
989
990 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
991 if (!ctl)
992 return -ENOMEM;
2323736d 993 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
b21acc1c
CK		 994 ctl->alg_region = *alg_region;
995 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
996 if (!ctl->name) {
997 ret = -ENOMEM;
998 goto err_ctl;
999 }
1000 ctl->enabled = 1;
1001 ctl->set = 0;
1002 ctl->ops.xget = wm_coeff_get;
1003 ctl->ops.xput = wm_coeff_put;
1004 ctl->dsp = dsp;
1005
26c22a19 1006 ctl->flags = flags;
2323736d 1007 ctl->offset = offset;
b21acc1c
CK		 1008 if (len > 512) {
1009 adsp_warn(dsp, "Truncating control %s from %d\n",
1010 ctl->name, len);
1011 len = 512;
1012 }
1013 ctl->len = len;
1014 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1015 if (!ctl->cache) {
1016 ret = -ENOMEM;
1017 goto err_ctl_name;
1018 }
1019
2323736d
CK		 1020 list_add(&ctl->list, &dsp->ctl_list);
1021
b21acc1c
CK		 1022 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1023 if (!ctl_work) {
1024 ret = -ENOMEM;
1025 goto err_ctl_cache;
1026 }
1027
1028 ctl_work->dsp = dsp;
1029 ctl_work->ctl = ctl;
1030 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1031 schedule_work(&ctl_work->work);
1032
1033 return 0;
1034
1035err_ctl_cache:
1036 kfree(ctl->cache);
1037err_ctl_name:
1038 kfree(ctl->name);
1039err_ctl:
1040 kfree(ctl);
1041
1042 return ret;
1043}
1044
2323736d
CK		 1045struct wm_coeff_parsed_alg {
1046 int id;
1047 const u8 *name;
1048 int name_len;
1049 int ncoeff;
1050};
1051
1052struct wm_coeff_parsed_coeff {
1053 int offset;
1054 int mem_type;
1055 const u8 *name;
1056 int name_len;
1057 int ctl_type;
1058 int flags;
1059 int len;
1060};
1061
cb5b57a9
CK		 1062static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1063{
1064 int length;
1065
1066 switch (bytes) {
1067 case 1:
1068 length = **pos;
1069 break;
1070 case 2:
8299ee81 1071 length = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1072 break;
1073 default:
1074 return 0;
1075 }
1076
1077 if (str)
1078 *str = *pos + bytes;
1079
1080 *pos += ((length + bytes) + 3) & ~0x03;
1081
1082 return length;
1083}
1084
1085static int wm_coeff_parse_int(int bytes, const u8 **pos)
1086{
1087 int val = 0;
1088
1089 switch (bytes) {
1090 case 2:
8299ee81 1091 val = le16_to_cpu(*((__le16 *)*pos));
cb5b57a9
CK		 1092 break;
1093 case 4:
8299ee81 1094 val = le32_to_cpu(*((__le32 *)*pos));
cb5b57a9
CK		 1095 break;
1096 default:
1097 break;
1098 }
1099
1100 *pos += bytes;
1101
1102 return val;
1103}
1104
2323736d
CK		 1105static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1106 struct wm_coeff_parsed_alg *blk)
1107{
1108 const struct wmfw_adsp_alg_data *raw;
1109
cb5b57a9
CK		 1110 switch (dsp->fw_ver) {
1111 case 0:
1112 case 1:
1113 raw = (const struct wmfw_adsp_alg_data *)*data;
1114 *data = raw->data;
2323736d 1115
cb5b57a9
CK		 1116 blk->id = le32_to_cpu(raw->id);
1117 blk->name = raw->name;
1118 blk->name_len = strlen(raw->name);
1119 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1120 break;
1121 default:
1122 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1123 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1124 &blk->name);
1125 wm_coeff_parse_string(sizeof(u16), data, NULL);
1126 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1127 break;
1128 }
2323736d
CK		 1129
1130 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1131 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1132 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1133}
1134
1135static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1136 struct wm_coeff_parsed_coeff *blk)
1137{
1138 const struct wmfw_adsp_coeff_data *raw;
cb5b57a9
CK		 1139 const u8 *tmp;
1140 int length;
2323736d 1141
cb5b57a9
CK		 1142 switch (dsp->fw_ver) {
1143 case 0:
1144 case 1:
1145 raw = (const struct wmfw_adsp_coeff_data *)*data;
1146 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1147
1148 blk->offset = le16_to_cpu(raw->hdr.offset);
1149 blk->mem_type = le16_to_cpu(raw->hdr.type);
1150 blk->name = raw->name;
1151 blk->name_len = strlen(raw->name);
1152 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1153 blk->flags = le16_to_cpu(raw->flags);
1154 blk->len = le32_to_cpu(raw->len);
1155 break;
1156 default:
1157 tmp = *data;
1158 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1159 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1160 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1161 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1162 &blk->name);
1163 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1164 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1165 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1166 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1167 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1168
1169 *data = *data + sizeof(raw->hdr) + length;
1170 break;
1171 }
2323736d
CK		 1172
1173 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1174 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1175 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1176 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1177 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1178 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1179}
1180
1181static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1182 const struct wmfw_region *region)
1183{
1184 struct wm_adsp_alg_region alg_region = {};
1185 struct wm_coeff_parsed_alg alg_blk;
1186 struct wm_coeff_parsed_coeff coeff_blk;
1187 const u8 *data = region->data;
1188 int i, ret;
1189
1190 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1191 for (i = 0; i < alg_blk.ncoeff; i++) {
1192 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1193
1194 switch (coeff_blk.ctl_type) {
1195 case SNDRV_CTL_ELEM_TYPE_BYTES:
1196 break;
1197 default:
1198 adsp_err(dsp, "Unknown control type: %d\n",
1199 coeff_blk.ctl_type);
1200 return -EINVAL;
1201 }
1202
1203 alg_region.type = coeff_blk.mem_type;
1204 alg_region.alg = alg_blk.id;
1205
1206 ret = wm_adsp_create_control(dsp, &alg_region,
1207 coeff_blk.offset,
1208 coeff_blk.len,
1209 coeff_blk.name,
26c22a19
CK		 1210 coeff_blk.name_len,
1211 coeff_blk.flags);
2323736d
CK		 1212 if (ret < 0)
1213 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1214 coeff_blk.name_len, coeff_blk.name, ret);
1215 }
1216
1217 return 0;
1218}
1219
2159ad93
MB		 1220static int wm_adsp_load(struct wm_adsp *dsp)
1221{
cf17c83c 1222 LIST_HEAD(buf_list);
2159ad93
MB		 1223 const struct firmware *firmware;
1224 struct regmap *regmap = dsp->regmap;
1225 unsigned int pos = 0;
1226 const struct wmfw_header *header;
1227 const struct wmfw_adsp1_sizes *adsp1_sizes;
1228 const struct wmfw_adsp2_sizes *adsp2_sizes;
1229 const struct wmfw_footer *footer;
1230 const struct wmfw_region *region;
1231 const struct wm_adsp_region *mem;
1232 const char *region_name;
1233 char *file, *text;
cf17c83c 1234 struct wm_adsp_buf *buf;
2159ad93
MB		 1235 unsigned int reg;
1236 int regions = 0;
1237 int ret, offset, type, sizes;
1238
1239 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1240 if (file == NULL)
1241 return -ENOMEM;
1242
1023dbd9
MB		 1243 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
1244 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1245 file[PAGE_SIZE - 1] = '\0';
1246
1247 ret = request_firmware(&firmware, file, dsp->dev);
1248 if (ret != 0) {
1249 adsp_err(dsp, "Failed to request '%s'\n", file);
1250 goto out;
1251 }
1252 ret = -EINVAL;
1253
1254 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1255 if (pos >= firmware->size) {
1256 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1257 file, firmware->size);
1258 goto out_fw;
1259 }
1260
7585a5b0 1261 header = (void *)&firmware->data[0];
2159ad93
MB		 1262
1263 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1264 adsp_err(dsp, "%s: invalid magic\n", file);
1265 goto out_fw;
1266 }
1267
2323736d
CK		 1268 switch (header->ver) {
1269 case 0:
c61e59fe
CK		 1270 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1271 file, header->ver);
1272 break;
2323736d 1273 case 1:
cb5b57a9 1274 case 2:
2323736d
CK		 1275 break;
1276 default:
2159ad93
MB		 1277 adsp_err(dsp, "%s: unknown file format %d\n",
1278 file, header->ver);
1279 goto out_fw;
1280 }
2323736d 1281
3626992a 1282 adsp_info(dsp, "Firmware version: %d\n", header->ver);
2323736d 1283 dsp->fw_ver = header->ver;
2159ad93
MB		 1284
1285 if (header->core != dsp->type) {
1286 adsp_err(dsp, "%s: invalid core %d != %d\n",
1287 file, header->core, dsp->type);
1288 goto out_fw;
1289 }
1290
1291 switch (dsp->type) {
1292 case WMFW_ADSP1:
1293 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1294 adsp1_sizes = (void *)&(header[1]);
1295 footer = (void *)&(adsp1_sizes[1]);
1296 sizes = sizeof(*adsp1_sizes);
1297
1298 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1299 file, le32_to_cpu(adsp1_sizes->dm),
1300 le32_to_cpu(adsp1_sizes->pm),
1301 le32_to_cpu(adsp1_sizes->zm));
1302 break;
1303
1304 case WMFW_ADSP2:
1305 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1306 adsp2_sizes = (void *)&(header[1]);
1307 footer = (void *)&(adsp2_sizes[1]);
1308 sizes = sizeof(*adsp2_sizes);
1309
1310 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1311 file, le32_to_cpu(adsp2_sizes->xm),
1312 le32_to_cpu(adsp2_sizes->ym),
1313 le32_to_cpu(adsp2_sizes->pm),
1314 le32_to_cpu(adsp2_sizes->zm));
1315 break;
1316
1317 default:
6c452bda 1318 WARN(1, "Unknown DSP type");
2159ad93
MB		 1319 goto out_fw;
1320 }
1321
1322 if (le32_to_cpu(header->len) != sizeof(*header) +
1323 sizes + sizeof(*footer)) {
1324 adsp_err(dsp, "%s: unexpected header length %d\n",
1325 file, le32_to_cpu(header->len));
1326 goto out_fw;
1327 }
1328
1329 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1330 le64_to_cpu(footer->timestamp));
1331
1332 while (pos < firmware->size &&
1333 pos - firmware->size > sizeof(*region)) {
1334 region = (void *)&(firmware->data[pos]);
1335 region_name = "Unknown";
1336 reg = 0;
1337 text = NULL;
1338 offset = le32_to_cpu(region->offset) & 0xffffff;
1339 type = be32_to_cpu(region->type) & 0xff;
1340 mem = wm_adsp_find_region(dsp, type);
7585a5b0 1341
2159ad93
MB		 1342 switch (type) {
1343 case WMFW_NAME_TEXT:
1344 region_name = "Firmware name";
1345 text = kzalloc(le32_to_cpu(region->len) + 1,
1346 GFP_KERNEL);
1347 break;
2323736d
CK		 1348 case WMFW_ALGORITHM_DATA:
1349 region_name = "Algorithm";
1350 ret = wm_adsp_parse_coeff(dsp, region);
1351 if (ret != 0)
1352 goto out_fw;
1353 break;
2159ad93
MB		 1354 case WMFW_INFO_TEXT:
1355 region_name = "Information";
1356 text = kzalloc(le32_to_cpu(region->len) + 1,
1357 GFP_KERNEL);
1358 break;
1359 case WMFW_ABSOLUTE:
1360 region_name = "Absolute";
1361 reg = offset;
1362 break;
1363 case WMFW_ADSP1_PM:
2159ad93 1364 region_name = "PM";
45b9ee72 1365 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1366 break;
1367 case WMFW_ADSP1_DM:
2159ad93 1368 region_name = "DM";
45b9ee72 1369 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1370 break;
1371 case WMFW_ADSP2_XM:
2159ad93 1372 region_name = "XM";
45b9ee72 1373 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1374 break;
1375 case WMFW_ADSP2_YM:
2159ad93 1376 region_name = "YM";
45b9ee72 1377 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1378 break;
1379 case WMFW_ADSP1_ZM:
2159ad93 1380 region_name = "ZM";
45b9ee72 1381 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 1382 break;
1383 default:
1384 adsp_warn(dsp,
1385 "%s.%d: Unknown region type %x at %d(%x)\n",
1386 file, regions, type, pos, pos);
1387 break;
1388 }
1389
1390 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1391 regions, le32_to_cpu(region->len), offset,
1392 region_name);
1393
1394 if (text) {
1395 memcpy(text, region->data, le32_to_cpu(region->len));
1396 adsp_info(dsp, "%s: %s\n", file, text);
1397 kfree(text);
1398 }
1399
1400 if (reg) {
cdcd7f72
CK		 1401 buf = wm_adsp_buf_alloc(region->data,
1402 le32_to_cpu(region->len),
1403 &buf_list);
1404 if (!buf) {
1405 adsp_err(dsp, "Out of memory\n");
1406 ret = -ENOMEM;
1407 goto out_fw;
1408 }
c1a7898d 1409
cdcd7f72
CK		 1410 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1411 le32_to_cpu(region->len));
1412 if (ret != 0) {
1413 adsp_err(dsp,
1414 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1415 file, regions,
1416 le32_to_cpu(region->len), offset,
1417 region_name, ret);
1418 goto out_fw;
2159ad93
MB		 1419 }
1420 }
1421
1422 pos += le32_to_cpu(region->len) + sizeof(*region);
1423 regions++;
1424 }
cf17c83c
MB		 1425
1426 ret = regmap_async_complete(regmap);
1427 if (ret != 0) {
1428 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1429 goto out_fw;
1430 }
1431
2159ad93
MB		 1432 if (pos > firmware->size)
1433 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1434 file, regions, pos - firmware->size);
1435
f9f55e31
RF		 1436 wm_adsp_debugfs_save_wmfwname(dsp, file);
1437
2159ad93 1438out_fw:
cf17c83c
MB		 1439 regmap_async_complete(regmap);
1440 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1441 release_firmware(firmware);
1442out:
1443 kfree(file);
1444
1445 return ret;
1446}
1447
2323736d
CK		 1448static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1449 const struct wm_adsp_alg_region *alg_region)
1450{
1451 struct wm_coeff_ctl *ctl;
1452
1453 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1454 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1455 alg_region->alg == ctl->alg_region.alg &&
1456 alg_region->type == ctl->alg_region.type) {
1457 ctl->alg_region.base = alg_region->base;
1458 }
1459 }
1460}
1461
3809f001 1462static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
b618a185 1463 unsigned int pos, unsigned int len)
db40517c 1464{
b618a185
CK		 1465 void *alg;
1466 int ret;
db40517c 1467 __be32 val;
db40517c 1468
3809f001 1469 if (n_algs == 0) {
b618a185
CK		 1470 adsp_err(dsp, "No algorithms\n");
1471 return ERR_PTR(-EINVAL);
db40517c
MB		 1472 }
1473
3809f001
CK		 1474 if (n_algs > 1024) {
1475 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
b618a185
CK		 1476 return ERR_PTR(-EINVAL);
1477 }
db40517c 1478
b618a185
CK		 1479 /* Read the terminator first to validate the length */
1480 ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
1481 if (ret != 0) {
1482 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1483 ret);
1484 return ERR_PTR(ret);
1485 }
db40517c 1486
b618a185
CK		 1487 if (be32_to_cpu(val) != 0xbedead)
1488 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1489 pos + len, be32_to_cpu(val));
d62f4bc6 1490
b618a185
CK		 1491 alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
1492 if (!alg)
1493 return ERR_PTR(-ENOMEM);
db40517c 1494
b618a185
CK		 1495 ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
1496 if (ret != 0) {
1497 adsp_err(dsp, "Failed to read algorithm list: %d\n",
1498 ret);
1499 kfree(alg);
1500 return ERR_PTR(ret);
1501 }
ac50009f 1502
b618a185
CK		 1503 return alg;
1504}
ac50009f 1505
14197095
CK		 1506static struct wm_adsp_alg_region *
1507 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1508{
1509 struct wm_adsp_alg_region *alg_region;
1510
1511 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1512 if (id == alg_region->alg && type == alg_region->type)
1513 return alg_region;
1514 }
1515
1516 return NULL;
1517}
1518
d9d20e17
CK		 1519static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1520 int type, __be32 id,
1521 __be32 base)
1522{
1523 struct wm_adsp_alg_region *alg_region;
1524
1525 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1526 if (!alg_region)
1527 return ERR_PTR(-ENOMEM);
1528
1529 alg_region->type = type;
1530 alg_region->alg = be32_to_cpu(id);
1531 alg_region->base = be32_to_cpu(base);
1532
1533 list_add_tail(&alg_region->list, &dsp->alg_regions);
1534
2323736d
CK		 1535 if (dsp->fw_ver > 0)
1536 wm_adsp_ctl_fixup_base(dsp, alg_region);
1537
d9d20e17
CK		 1538 return alg_region;
1539}
1540
b618a185
CK		 1541static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1542{
1543 struct wmfw_adsp1_id_hdr adsp1_id;
1544 struct wmfw_adsp1_alg_hdr *adsp1_alg;
3809f001 1545 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1546 const struct wm_adsp_region *mem;
1547 unsigned int pos, len;
3809f001 1548 size_t n_algs;
b618a185 1549 int i, ret;
db40517c 1550
b618a185
CK		 1551 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
1552 if (WARN_ON(!mem))
1553 return -EINVAL;
1554
1555 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
1556 sizeof(adsp1_id));
1557 if (ret != 0) {
1558 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1559 ret);
1560 return ret;
1561 }
db40517c 1562
3809f001 1563 n_algs = be32_to_cpu(adsp1_id.n_algs);
b618a185
CK		 1564 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
1565 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1566 dsp->fw_id,
1567 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
1568 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
1569 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
3809f001 1570 n_algs);
b618a185 1571
d9d20e17
CK		 1572 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1573 adsp1_id.fw.id, adsp1_id.zm);
1574 if (IS_ERR(alg_region))
1575 return PTR_ERR(alg_region);
d62f4bc6 1576
d9d20e17
CK		 1577 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1578 adsp1_id.fw.id, adsp1_id.dm);
1579 if (IS_ERR(alg_region))
1580 return PTR_ERR(alg_region);
db40517c 1581
b618a185 1582 pos = sizeof(adsp1_id) / 2;
3809f001 1583 len = (sizeof(*adsp1_alg) * n_algs) / 2;
b618a185 1584
3809f001 1585 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1586 if (IS_ERR(adsp1_alg))
1587 return PTR_ERR(adsp1_alg);
1588
3809f001 1589 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1590 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1591 i, be32_to_cpu(adsp1_alg[i].alg.id),
1592 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1593 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1594 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1595 be32_to_cpu(adsp1_alg[i].dm),
1596 be32_to_cpu(adsp1_alg[i].zm));
ac50009f 1597
d9d20e17
CK		 1598 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
1599 adsp1_alg[i].alg.id,
1600 adsp1_alg[i].dm);
1601 if (IS_ERR(alg_region)) {
1602 ret = PTR_ERR(alg_region);
b618a185
CK		 1603 goto out;
1604 }
2323736d
CK		 1605 if (dsp->fw_ver == 0) {
1606 if (i + 1 < n_algs) {
1607 len = be32_to_cpu(adsp1_alg[i + 1].dm);
1608 len -= be32_to_cpu(adsp1_alg[i].dm);
1609 len *= 4;
1610 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1611 len, NULL, 0, 0);
2323736d
CK		 1612 } else {
1613 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1614 be32_to_cpu(adsp1_alg[i].alg.id));
1615 }
b618a185 1616 }
ac50009f 1617
d9d20e17
CK		 1618 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
1619 adsp1_alg[i].alg.id,
1620 adsp1_alg[i].zm);
1621 if (IS_ERR(alg_region)) {
1622 ret = PTR_ERR(alg_region);
b618a185
CK		 1623 goto out;
1624 }
2323736d
CK		 1625 if (dsp->fw_ver == 0) {
1626 if (i + 1 < n_algs) {
1627 len = be32_to_cpu(adsp1_alg[i + 1].zm);
1628 len -= be32_to_cpu(adsp1_alg[i].zm);
1629 len *= 4;
1630 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1631 len, NULL, 0, 0);
2323736d
CK		 1632 } else {
1633 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1634 be32_to_cpu(adsp1_alg[i].alg.id));
1635 }
b618a185 1636 }
db40517c
MB		 1637 }
1638
b618a185
CK		 1639out:
1640 kfree(adsp1_alg);
1641 return ret;
1642}
db40517c 1643
b618a185
CK		 1644static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
1645{
1646 struct wmfw_adsp2_id_hdr adsp2_id;
1647 struct wmfw_adsp2_alg_hdr *adsp2_alg;
3809f001 1648 struct wm_adsp_alg_region *alg_region;
b618a185
CK		 1649 const struct wm_adsp_region *mem;
1650 unsigned int pos, len;
3809f001 1651 size_t n_algs;
b618a185
CK		 1652 int i, ret;
1653
1654 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
1655 if (WARN_ON(!mem))
d62f4bc6 1656 return -EINVAL;
d62f4bc6 1657
b618a185
CK		 1658 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
1659 sizeof(adsp2_id));
db40517c 1660 if (ret != 0) {
b618a185
CK		 1661 adsp_err(dsp, "Failed to read algorithm info: %d\n",
1662 ret);
db40517c
MB		 1663 return ret;
1664 }
1665
3809f001 1666 n_algs = be32_to_cpu(adsp2_id.n_algs);
b618a185 1667 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
f9f55e31 1668 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
b618a185
CK		 1669 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
1670 dsp->fw_id,
f9f55e31
RF		 1671 (dsp->fw_id_version & 0xff0000) >> 16,
1672 (dsp->fw_id_version & 0xff00) >> 8,
1673 dsp->fw_id_version & 0xff,
3809f001 1674 n_algs);
b618a185 1675
d9d20e17
CK		 1676 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1677 adsp2_id.fw.id, adsp2_id.xm);
1678 if (IS_ERR(alg_region))
1679 return PTR_ERR(alg_region);
db40517c 1680
d9d20e17
CK		 1681 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1682 adsp2_id.fw.id, adsp2_id.ym);
1683 if (IS_ERR(alg_region))
1684 return PTR_ERR(alg_region);
db40517c 1685
d9d20e17
CK		 1686 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1687 adsp2_id.fw.id, adsp2_id.zm);
1688 if (IS_ERR(alg_region))
1689 return PTR_ERR(alg_region);
db40517c 1690
b618a185 1691 pos = sizeof(adsp2_id) / 2;
3809f001 1692 len = (sizeof(*adsp2_alg) * n_algs) / 2;
db40517c 1693
3809f001 1694 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
b618a185
CK		 1695 if (IS_ERR(adsp2_alg))
1696 return PTR_ERR(adsp2_alg);
471f4885 1697
3809f001 1698 for (i = 0; i < n_algs; i++) {
b618a185
CK		 1699 adsp_info(dsp,
1700 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1701 i, be32_to_cpu(adsp2_alg[i].alg.id),
1702 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1703 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1704 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1705 be32_to_cpu(adsp2_alg[i].xm),
1706 be32_to_cpu(adsp2_alg[i].ym),
1707 be32_to_cpu(adsp2_alg[i].zm));
db40517c 1708
d9d20e17
CK		 1709 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
1710 adsp2_alg[i].alg.id,
1711 adsp2_alg[i].xm);
1712 if (IS_ERR(alg_region)) {
1713 ret = PTR_ERR(alg_region);
b618a185
CK		 1714 goto out;
1715 }
2323736d
CK		 1716 if (dsp->fw_ver == 0) {
1717 if (i + 1 < n_algs) {
1718 len = be32_to_cpu(adsp2_alg[i + 1].xm);
1719 len -= be32_to_cpu(adsp2_alg[i].xm);
1720 len *= 4;
1721 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1722 len, NULL, 0, 0);
2323736d
CK		 1723 } else {
1724 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1725 be32_to_cpu(adsp2_alg[i].alg.id));
1726 }
b618a185 1727 }
471f4885 1728
d9d20e17
CK		 1729 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
1730 adsp2_alg[i].alg.id,
1731 adsp2_alg[i].ym);
1732 if (IS_ERR(alg_region)) {
1733 ret = PTR_ERR(alg_region);
b618a185
CK		 1734 goto out;
1735 }
2323736d
CK		 1736 if (dsp->fw_ver == 0) {
1737 if (i + 1 < n_algs) {
1738 len = be32_to_cpu(adsp2_alg[i + 1].ym);
1739 len -= be32_to_cpu(adsp2_alg[i].ym);
1740 len *= 4;
1741 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1742 len, NULL, 0, 0);
2323736d
CK		 1743 } else {
1744 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1745 be32_to_cpu(adsp2_alg[i].alg.id));
1746 }
b618a185 1747 }
471f4885 1748
d9d20e17
CK		 1749 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
1750 adsp2_alg[i].alg.id,
1751 adsp2_alg[i].zm);
1752 if (IS_ERR(alg_region)) {
1753 ret = PTR_ERR(alg_region);
b618a185
CK		 1754 goto out;
1755 }
2323736d
CK		 1756 if (dsp->fw_ver == 0) {
1757 if (i + 1 < n_algs) {
1758 len = be32_to_cpu(adsp2_alg[i + 1].zm);
1759 len -= be32_to_cpu(adsp2_alg[i].zm);
1760 len *= 4;
1761 wm_adsp_create_control(dsp, alg_region, 0,
26c22a19 1762 len, NULL, 0, 0);
2323736d
CK		 1763 } else {
1764 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1765 be32_to_cpu(adsp2_alg[i].alg.id));
1766 }
db40517c
MB		 1767 }
1768 }
1769
1770out:
b618a185 1771 kfree(adsp2_alg);
db40517c
MB		 1772 return ret;
1773}
1774
2159ad93
MB		 1775static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1776{
cf17c83c 1777 LIST_HEAD(buf_list);
2159ad93
MB		 1778 struct regmap *regmap = dsp->regmap;
1779 struct wmfw_coeff_hdr *hdr;
1780 struct wmfw_coeff_item *blk;
1781 const struct firmware *firmware;
471f4885
MB		 1782 const struct wm_adsp_region *mem;
1783 struct wm_adsp_alg_region *alg_region;
2159ad93
MB		 1784 const char *region_name;
1785 int ret, pos, blocks, type, offset, reg;
1786 char *file;
cf17c83c 1787 struct wm_adsp_buf *buf;
2159ad93
MB		 1788
1789 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1790 if (file == NULL)
1791 return -ENOMEM;
1792
1023dbd9
MB		 1793 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1794 wm_adsp_fw[dsp->fw].file);
2159ad93
MB		 1795 file[PAGE_SIZE - 1] = '\0';
1796
1797 ret = request_firmware(&firmware, file, dsp->dev);
1798 if (ret != 0) {
1799 adsp_warn(dsp, "Failed to request '%s'\n", file);
1800 ret = 0;
1801 goto out;
1802 }
1803 ret = -EINVAL;
1804
1805 if (sizeof(*hdr) >= firmware->size) {
1806 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1807 file, firmware->size);
1808 goto out_fw;
1809 }
1810
7585a5b0 1811 hdr = (void *)&firmware->data[0];
2159ad93
MB		 1812 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1813 adsp_err(dsp, "%s: invalid magic\n", file);
a4cdbec7 1814 goto out_fw;
2159ad93
MB		 1815 }
1816
c712326d
MB		 1817 switch (be32_to_cpu(hdr->rev) & 0xff) {
1818 case 1:
1819 break;
1820 default:
1821 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1822 file, be32_to_cpu(hdr->rev) & 0xff);
1823 ret = -EINVAL;
1824 goto out_fw;
1825 }
1826
2159ad93
MB		 1827 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1828 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1829 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1830 le32_to_cpu(hdr->ver) & 0xff);
1831
1832 pos = le32_to_cpu(hdr->len);
1833
1834 blocks = 0;
1835 while (pos < firmware->size &&
1836 pos - firmware->size > sizeof(*blk)) {
7585a5b0 1837 blk = (void *)(&firmware->data[pos]);
2159ad93 1838
c712326d
MB		 1839 type = le16_to_cpu(blk->type);
1840 offset = le16_to_cpu(blk->offset);
2159ad93
MB		 1841
1842 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1843 file, blocks, le32_to_cpu(blk->id),
1844 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1845 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1846 le32_to_cpu(blk->ver) & 0xff);
1847 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1848 file, blocks, le32_to_cpu(blk->len), offset, type);
1849
1850 reg = 0;
1851 region_name = "Unknown";
1852 switch (type) {
c712326d
MB		 1853 case (WMFW_NAME_TEXT << 8):
1854 case (WMFW_INFO_TEXT << 8):
2159ad93 1855 break;
c712326d 1856 case (WMFW_ABSOLUTE << 8):
f395a218
MB		 1857 /*
1858 * Old files may use this for global
1859 * coefficients.
1860 */
1861 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1862 offset == 0) {
1863 region_name = "global coefficients";
1864 mem = wm_adsp_find_region(dsp, type);
1865 if (!mem) {
1866 adsp_err(dsp, "No ZM\n");
1867 break;
1868 }
1869 reg = wm_adsp_region_to_reg(mem, 0);
1870
1871 } else {
1872 region_name = "register";
1873 reg = offset;
1874 }
2159ad93 1875 break;
471f4885
MB		 1876
1877 case WMFW_ADSP1_DM:
1878 case WMFW_ADSP1_ZM:
1879 case WMFW_ADSP2_XM:
1880 case WMFW_ADSP2_YM:
1881 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1882 file, blocks, le32_to_cpu(blk->len),
1883 type, le32_to_cpu(blk->id));
1884
1885 mem = wm_adsp_find_region(dsp, type);
1886 if (!mem) {
1887 adsp_err(dsp, "No base for region %x\n", type);
1888 break;
1889 }
1890
14197095
CK		 1891 alg_region = wm_adsp_find_alg_region(dsp, type,
1892 le32_to_cpu(blk->id));
1893 if (alg_region) {
1894 reg = alg_region->base;
1895 reg = wm_adsp_region_to_reg(mem, reg);
1896 reg += offset;
1897 } else {
471f4885
MB		 1898 adsp_err(dsp, "No %x for algorithm %x\n",
1899 type, le32_to_cpu(blk->id));
14197095 1900 }
471f4885
MB		 1901 break;
1902
2159ad93 1903 default:
25c62f7e
MB		 1904 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1905 file, blocks, type, pos);
2159ad93
MB		 1906 break;
1907 }
1908
1909 if (reg) {
cf17c83c
MB		 1910 buf = wm_adsp_buf_alloc(blk->data,
1911 le32_to_cpu(blk->len),
1912 &buf_list);
a76fefab
MB		 1913 if (!buf) {
1914 adsp_err(dsp, "Out of memory\n");
f4b82812
WY		 1915 ret = -ENOMEM;
1916 goto out_fw;
a76fefab
MB		 1917 }
1918
20da6d5a
MB		 1919 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1920 file, blocks, le32_to_cpu(blk->len),
1921 reg);
cf17c83c
MB		 1922 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1923 le32_to_cpu(blk->len));
2159ad93
MB		 1924 if (ret != 0) {
1925 adsp_err(dsp,
43bc3bf6
DP		 1926 "%s.%d: Failed to write to %x in %s: %d\n",
1927 file, blocks, reg, region_name, ret);
2159ad93
MB		 1928 }
1929 }
1930
be951017 1931 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2159ad93
MB		 1932 blocks++;
1933 }
1934
cf17c83c
MB		 1935 ret = regmap_async_complete(regmap);
1936 if (ret != 0)
1937 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1938
2159ad93
MB		 1939 if (pos > firmware->size)
1940 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1941 file, blocks, pos - firmware->size);
1942
f9f55e31
RF		 1943 wm_adsp_debugfs_save_binname(dsp, file);
1944
2159ad93 1945out_fw:
9da7a5a9 1946 regmap_async_complete(regmap);
2159ad93 1947 release_firmware(firmware);
cf17c83c 1948 wm_adsp_buf_free(&buf_list);
2159ad93
MB		 1949out:
1950 kfree(file);
f4b82812 1951 return ret;
2159ad93
MB		 1952}
1953
3809f001 1954int wm_adsp1_init(struct wm_adsp *dsp)
5e7a7a22 1955{
3809f001 1956 INIT_LIST_HEAD(&dsp->alg_regions);
5e7a7a22 1957
078e7183
CK		 1958 mutex_init(&dsp->pwr_lock);
1959
5e7a7a22
MB		 1960 return 0;
1961}
1962EXPORT_SYMBOL_GPL(wm_adsp1_init);
1963
2159ad93
MB		 1964int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1965 struct snd_kcontrol *kcontrol,
1966 int event)
1967{
72718517 1968 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2159ad93
MB		 1969 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1970 struct wm_adsp *dsp = &dsps[w->shift];
b0101b4f 1971 struct wm_adsp_alg_region *alg_region;
6ab2b7b4 1972 struct wm_coeff_ctl *ctl;
2159ad93 1973 int ret;
7585a5b0 1974 unsigned int val;
2159ad93 1975
00200107 1976 dsp->card = codec->component.card;
92bb4c32 1977
078e7183
CK		 1978 mutex_lock(&dsp->pwr_lock);
1979
2159ad93
MB		 1980 switch (event) {
1981 case SND_SOC_DAPM_POST_PMU:
1982 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1983 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1984
94e205bf
CR		 1985 /*
1986 * For simplicity set the DSP clock rate to be the
1987 * SYSCLK rate rather than making it configurable.
1988 */
7585a5b0 1989 if (dsp->sysclk_reg) {
94e205bf
CR		 1990 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1991 if (ret != 0) {
1992 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1993 ret);
078e7183 1994 goto err_mutex;
94e205bf
CR		 1995 }
1996
1997 val = (val & dsp->sysclk_mask)
1998 >> dsp->sysclk_shift;
1999
2000 ret = regmap_update_bits(dsp->regmap,
2001 dsp->base + ADSP1_CONTROL_31,
2002 ADSP1_CLK_SEL_MASK, val);
2003 if (ret != 0) {
2004 adsp_err(dsp, "Failed to set clock rate: %d\n",
2005 ret);
078e7183 2006 goto err_mutex;
94e205bf
CR		 2007 }
2008 }
2009
2159ad93
MB		 2010 ret = wm_adsp_load(dsp);
2011 if (ret != 0)
078e7183 2012 goto err_ena;
2159ad93 2013
b618a185 2014 ret = wm_adsp1_setup_algs(dsp);
db40517c 2015 if (ret != 0)
078e7183 2016 goto err_ena;
db40517c 2017
2159ad93
MB		 2018 ret = wm_adsp_load_coeff(dsp);
2019 if (ret != 0)
078e7183 2020 goto err_ena;
2159ad93 2021
0c2e3f34 2022 /* Initialize caches for enabled and unset controls */
81ad93ec 2023 ret = wm_coeff_init_control_caches(dsp);
6ab2b7b4 2024 if (ret != 0)
078e7183 2025 goto err_ena;
6ab2b7b4 2026
0c2e3f34 2027 /* Sync set controls */
81ad93ec 2028 ret = wm_coeff_sync_controls(dsp);
6ab2b7b4 2029 if (ret != 0)
078e7183 2030 goto err_ena;
6ab2b7b4 2031
2159ad93
MB		 2032 /* Start the core running */
2033 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2034 ADSP1_CORE_ENA | ADSP1_START,
2035 ADSP1_CORE_ENA | ADSP1_START);
2036 break;
2037
2038 case SND_SOC_DAPM_PRE_PMD:
2039 /* Halt the core */
2040 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2041 ADSP1_CORE_ENA | ADSP1_START, 0);
2042
2043 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2044 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2045
2046 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2047 ADSP1_SYS_ENA, 0);
6ab2b7b4 2048
81ad93ec 2049 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2050 ctl->enabled = 0;
b0101b4f
DP		 2051
2052 while (!list_empty(&dsp->alg_regions)) {
2053 alg_region = list_first_entry(&dsp->alg_regions,
2054 struct wm_adsp_alg_region,
2055 list);
2056 list_del(&alg_region->list);
2057 kfree(alg_region);
2058 }
2159ad93
MB		 2059 break;
2060
2061 default:
2062 break;
2063 }
2064
078e7183
CK		 2065 mutex_unlock(&dsp->pwr_lock);
2066
2159ad93
MB		 2067 return 0;
2068
078e7183 2069err_ena:
2159ad93
MB		 2070 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2071 ADSP1_SYS_ENA, 0);
078e7183
CK		 2072err_mutex:
2073 mutex_unlock(&dsp->pwr_lock);
2074
2159ad93
MB		 2075 return ret;
2076}
2077EXPORT_SYMBOL_GPL(wm_adsp1_event);
2078
2079static int wm_adsp2_ena(struct wm_adsp *dsp)
2080{
2081 unsigned int val;
2082 int ret, count;
2083
1552c325
MB		 2084 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2085 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2159ad93
MB		 2086 if (ret != 0)
2087 return ret;
2088
2089 /* Wait for the RAM to start, should be near instantaneous */
939fd1e8 2090 for (count = 0; count < 10; ++count) {
2159ad93
MB		 2091 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
2092 &val);
2093 if (ret != 0)
2094 return ret;
939fd1e8
CK		 2095
2096 if (val & ADSP2_RAM_RDY)
2097 break;
2098
2099 msleep(1);
2100 }
2159ad93
MB		 2101
2102 if (!(val & ADSP2_RAM_RDY)) {
2103 adsp_err(dsp, "Failed to start DSP RAM\n");
2104 return -EBUSY;
2105 }
2106
2107 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2159ad93
MB		 2108
2109 return 0;
2110}
2111
18b1a902 2112static void wm_adsp2_boot_work(struct work_struct *work)
2159ad93 2113{
d8a64d6a
CK		 2114 struct wm_adsp *dsp = container_of(work,
2115 struct wm_adsp,
2116 boot_work);
2159ad93 2117 int ret;
d8a64d6a 2118 unsigned int val;
2159ad93 2119
078e7183
CK		 2120 mutex_lock(&dsp->pwr_lock);
2121
d8a64d6a
CK		 2122 /*
2123 * For simplicity set the DSP clock rate to be the
2124 * SYSCLK rate rather than making it configurable.
2125 */
2126 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
2127 if (ret != 0) {
2128 adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret);
078e7183 2129 goto err_mutex;
d8a64d6a
CK		 2130 }
2131 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
2132 >> ARIZONA_SYSCLK_FREQ_SHIFT;
92bb4c32 2133
d8a64d6a
CK		 2134 ret = regmap_update_bits_async(dsp->regmap,
2135 dsp->base + ADSP2_CLOCKING,
2136 ADSP2_CLK_SEL_MASK, val);
2137 if (ret != 0) {
2138 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
078e7183 2139 goto err_mutex;
d8a64d6a 2140 }
dd49e2c8 2141
d8a64d6a
CK		 2142 ret = wm_adsp2_ena(dsp);
2143 if (ret != 0)
078e7183 2144 goto err_mutex;
2159ad93 2145
d8a64d6a
CK		 2146 ret = wm_adsp_load(dsp);
2147 if (ret != 0)
078e7183 2148 goto err_ena;
2159ad93 2149
b618a185 2150 ret = wm_adsp2_setup_algs(dsp);
d8a64d6a 2151 if (ret != 0)
078e7183 2152 goto err_ena;
db40517c 2153
d8a64d6a
CK		 2154 ret = wm_adsp_load_coeff(dsp);
2155 if (ret != 0)
078e7183 2156 goto err_ena;
2159ad93 2157
d8a64d6a
CK		 2158 /* Initialize caches for enabled and unset controls */
2159 ret = wm_coeff_init_control_caches(dsp);
2160 if (ret != 0)
078e7183 2161 goto err_ena;
6ab2b7b4 2162
d8a64d6a
CK		 2163 /* Sync set controls */
2164 ret = wm_coeff_sync_controls(dsp);
2165 if (ret != 0)
078e7183 2166 goto err_ena;
d8a64d6a 2167
d8a64d6a
CK		 2168 dsp->running = true;
2169
078e7183
CK		 2170 mutex_unlock(&dsp->pwr_lock);
2171
d8a64d6a 2172 return;
6ab2b7b4 2173
078e7183 2174err_ena:
d8a64d6a
CK		 2175 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2176 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
078e7183
CK		 2177err_mutex:
2178 mutex_unlock(&dsp->pwr_lock);
d8a64d6a
CK		 2179}
2180
12db5edd
CK		 2181int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
2182 struct snd_kcontrol *kcontrol, int event)
2183{
72718517 2184 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
12db5edd
CK		 2185 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2186 struct wm_adsp *dsp = &dsps[w->shift];
2187
00200107 2188 dsp->card = codec->component.card;
12db5edd
CK		 2189
2190 switch (event) {
2191 case SND_SOC_DAPM_PRE_PMU:
2192 queue_work(system_unbound_wq, &dsp->boot_work);
2193 break;
2194 default:
2195 break;
cab27258 2196 }
12db5edd
CK		 2197
2198 return 0;
2199}
2200EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2201
d8a64d6a
CK		 2202int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2203 struct snd_kcontrol *kcontrol, int event)
2204{
72718517 2205 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
d8a64d6a
CK		 2206 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
2207 struct wm_adsp *dsp = &dsps[w->shift];
2208 struct wm_adsp_alg_region *alg_region;
2209 struct wm_coeff_ctl *ctl;
2210 int ret;
2211
d8a64d6a
CK		 2212 switch (event) {
2213 case SND_SOC_DAPM_POST_PMU:
d8a64d6a
CK		 2214 flush_work(&dsp->boot_work);
2215
2216 if (!dsp->running)
2217 return -EIO;
6ab2b7b4 2218
d8a64d6a
CK		 2219 ret = regmap_update_bits(dsp->regmap,
2220 dsp->base + ADSP2_CONTROL,
00e4c3b6
CK		 2221 ADSP2_CORE_ENA | ADSP2_START,
2222 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 2223 if (ret != 0)
2224 goto err;
2cd19bdb
CK		 2225
2226 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2227 ret = wm_adsp_buffer_init(dsp);
2228
2159ad93
MB		 2229 break;
2230
2231 case SND_SOC_DAPM_PRE_PMD:
10337b07
RF		 2232 /* Log firmware state, it can be useful for analysis */
2233 wm_adsp2_show_fw_status(dsp);
2234
078e7183
CK		 2235 mutex_lock(&dsp->pwr_lock);
2236
f9f55e31
RF		 2237 wm_adsp_debugfs_clear(dsp);
2238
2239 dsp->fw_id = 0;
2240 dsp->fw_id_version = 0;
1023dbd9
MB		 2241 dsp->running = false;
2242
2159ad93 2243 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 2244 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
2245 ADSP2_START, 0);
973838a0 2246
2d30b575
MB		 2247 /* Make sure DMAs are quiesced */
2248 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2249 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2250 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2251
81ad93ec 2252 list_for_each_entry(ctl, &dsp->ctl_list, list)
6ab2b7b4 2253 ctl->enabled = 0;
6ab2b7b4 2254
471f4885
MB		 2255 while (!list_empty(&dsp->alg_regions)) {
2256 alg_region = list_first_entry(&dsp->alg_regions,
2257 struct wm_adsp_alg_region,
2258 list);
2259 list_del(&alg_region->list);
2260 kfree(alg_region);
2261 }
ddbc5efe 2262
2cd19bdb
CK		 2263 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2264 wm_adsp_buffer_free(dsp);
2265
078e7183
CK		 2266 mutex_unlock(&dsp->pwr_lock);
2267
ddbc5efe 2268 adsp_dbg(dsp, "Shutdown complete\n");
2159ad93
MB		 2269 break;
2270
2271 default:
2272 break;
2273 }
2274
2275 return 0;
2276err:
2277 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 2278 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 2279 return ret;
2280}
2281EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0 2282
f5e2ce92
RF		 2283int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2284{
f9f55e31
RF		 2285 wm_adsp2_init_debugfs(dsp, codec);
2286
218e5087 2287 return snd_soc_add_codec_controls(codec,
336d0442
RF		 2288 &wm_adsp_fw_controls[dsp->num - 1],
2289 1);
f5e2ce92
RF		 2290}
2291EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe);
2292
2293int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec)
2294{
f9f55e31
RF		 2295 wm_adsp2_cleanup_debugfs(dsp);
2296
f5e2ce92
RF		 2297 return 0;
2298}
2299EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove);
2300
81ac58b1 2301int wm_adsp2_init(struct wm_adsp *dsp)
973838a0
MB		 2302{
2303 int ret;
2304
10a2b662
MB		 2305 /*
2306 * Disable the DSP memory by default when in reset for a small
2307 * power saving.
2308 */
3809f001 2309 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
10a2b662
MB		 2310 ADSP2_MEM_ENA, 0);
2311 if (ret != 0) {
3809f001 2312 adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
10a2b662
MB		 2313 return ret;
2314 }
2315
3809f001
CK		 2316 INIT_LIST_HEAD(&dsp->alg_regions);
2317 INIT_LIST_HEAD(&dsp->ctl_list);
2318 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
6ab2b7b4 2319
078e7183
CK		 2320 mutex_init(&dsp->pwr_lock);
2321
973838a0
MB		 2322 return 0;
2323}
2324EXPORT_SYMBOL_GPL(wm_adsp2_init);
0a37c6ef 2325
406abc95
CK		 2326int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
2327{
2328 struct wm_adsp_compr *compr;
2329 int ret = 0;
2330
2331 mutex_lock(&dsp->pwr_lock);
2332
2333 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
2334 adsp_err(dsp, "Firmware does not support compressed API\n");
2335 ret = -ENXIO;
2336 goto out;
2337 }
2338
2339 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
2340 adsp_err(dsp, "Firmware does not support stream direction\n");
2341 ret = -EINVAL;
2342 goto out;
2343 }
2344
95fe9597
CK		 2345 if (dsp->compr) {
2346 /* It is expect this limitation will be removed in future */
2347 adsp_err(dsp, "Only a single stream supported per DSP\n");
2348 ret = -EBUSY;
2349 goto out;
2350 }
2351
406abc95
CK		 2352 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
2353 if (!compr) {
2354 ret = -ENOMEM;
2355 goto out;
2356 }
2357
2358 compr->dsp = dsp;
2359 compr->stream = stream;
2360
2361 dsp->compr = compr;
2362
2363 stream->runtime->private_data = compr;
2364
2365out:
2366 mutex_unlock(&dsp->pwr_lock);
2367
2368 return ret;
2369}
2370EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
2371
2372int wm_adsp_compr_free(struct snd_compr_stream *stream)
2373{
2374 struct wm_adsp_compr *compr = stream->runtime->private_data;
2375 struct wm_adsp *dsp = compr->dsp;
2376
2377 mutex_lock(&dsp->pwr_lock);
2378
2379 dsp->compr = NULL;
2380
2381 kfree(compr);
2382
2383 mutex_unlock(&dsp->pwr_lock);
2384
2385 return 0;
2386}
2387EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
2388
2389static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
2390 struct snd_compr_params *params)
2391{
2392 struct wm_adsp_compr *compr = stream->runtime->private_data;
2393 struct wm_adsp *dsp = compr->dsp;
2394 const struct wm_adsp_fw_caps *caps;
2395 const struct snd_codec_desc *desc;
2396 int i, j;
2397
2398 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
2399 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
2400 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
2401 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
2402 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
2403 adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
2404 params->buffer.fragment_size,
2405 params->buffer.fragments);
2406
2407 return -EINVAL;
2408 }
2409
2410 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
2411 caps = &wm_adsp_fw[dsp->fw].caps[i];
2412 desc = &caps->desc;
2413
2414 if (caps->id != params->codec.id)
2415 continue;
2416
2417 if (stream->direction == SND_COMPRESS_PLAYBACK) {
2418 if (desc->max_ch < params->codec.ch_out)
2419 continue;
2420 } else {
2421 if (desc->max_ch < params->codec.ch_in)
2422 continue;
2423 }
2424
2425 if (!(desc->formats & (1 << params->codec.format)))
2426 continue;
2427
2428 for (j = 0; j < desc->num_sample_rates; ++j)
2429 if (desc->sample_rates[j] == params->codec.sample_rate)
2430 return 0;
2431 }
2432
2433 adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
2434 params->codec.id, params->codec.ch_in, params->codec.ch_out,
2435 params->codec.sample_rate, params->codec.format);
2436 return -EINVAL;
2437}
2438
2439int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
2440 struct snd_compr_params *params)
2441{
2442 struct wm_adsp_compr *compr = stream->runtime->private_data;
2443 int ret;
2444
2445 ret = wm_adsp_compr_check_params(stream, params);
2446 if (ret)
2447 return ret;
2448
2449 compr->size = params->buffer;
2450
2451 adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
2452 compr->size.fragment_size, compr->size.fragments);
2453
2454 return 0;
2455}
2456EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
2457
2458int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
2459 struct snd_compr_caps *caps)
2460{
2461 struct wm_adsp_compr *compr = stream->runtime->private_data;
2462 int fw = compr->dsp->fw;
2463 int i;
2464
2465 if (wm_adsp_fw[fw].caps) {
2466 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
2467 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
2468
2469 caps->num_codecs = i;
2470 caps->direction = wm_adsp_fw[fw].compr_direction;
2471
2472 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
2473 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
2474 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
2475 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
2476 }
2477
2478 return 0;
2479}
2480EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
2481
2cd19bdb
CK		 2482static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
2483 unsigned int mem_addr,
2484 unsigned int num_words, u32 *data)
2485{
2486 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2487 unsigned int i, reg;
2488 int ret;
2489
2490 if (!mem)
2491 return -EINVAL;
2492
2493 reg = wm_adsp_region_to_reg(mem, mem_addr);
2494
2495 ret = regmap_raw_read(dsp->regmap, reg, data,
2496 sizeof(*data) * num_words);
2497 if (ret < 0)
2498 return ret;
2499
2500 for (i = 0; i < num_words; ++i)
2501 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
2502
2503 return 0;
2504}
2505
2506static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
2507 unsigned int mem_addr, u32 *data)
2508{
2509 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
2510}
2511
2512static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
2513 unsigned int mem_addr, u32 data)
2514{
2515 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
2516 unsigned int reg;
2517
2518 if (!mem)
2519 return -EINVAL;
2520
2521 reg = wm_adsp_region_to_reg(mem, mem_addr);
2522
2523 data = cpu_to_be32(data & 0x00ffffffu);
2524
2525 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
2526}
2527
2528static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
2529 unsigned int field_offset, u32 *data)
2530{
2531 return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM,
2532 buf->host_buf_ptr + field_offset, data);
2533}
2534
2535static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
2536 unsigned int field_offset, u32 data)
2537{
2538 return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM,
2539 buf->host_buf_ptr + field_offset, data);
2540}
2541
2542static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
2543{
2544 struct wm_adsp_alg_region *alg_region;
2545 struct wm_adsp *dsp = buf->dsp;
2546 u32 xmalg, addr, magic;
2547 int i, ret;
2548
2549 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
2550 xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
2551
2552 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
2553 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
2554 if (ret < 0)
2555 return ret;
2556
2557 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
2558 return -EINVAL;
2559
2560 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
2561 for (i = 0; i < 5; ++i) {
2562 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
2563 &buf->host_buf_ptr);
2564 if (ret < 0)
2565 return ret;
2566
2567 if (buf->host_buf_ptr)
2568 break;
2569
2570 usleep_range(1000, 2000);
2571 }
2572
2573 if (!buf->host_buf_ptr)
2574 return -EIO;
2575
2576 adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
2577
2578 return 0;
2579}
2580
2581static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
2582{
2583 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
2584 struct wm_adsp_buffer_region *region;
2585 u32 offset = 0;
2586 int i, ret;
2587
2588 for (i = 0; i < caps->num_regions; ++i) {
2589 region = &buf->regions[i];
2590
2591 region->offset = offset;
2592 region->mem_type = caps->region_defs[i].mem_type;
2593
2594 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
2595 &region->base_addr);
2596 if (ret < 0)
2597 return ret;
2598
2599 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
2600 &offset);
2601 if (ret < 0)
2602 return ret;
2603
2604 region->cumulative_size = offset;
2605
2606 adsp_dbg(buf->dsp,
2607 "region=%d type=%d base=%04x off=%04x size=%04x\n",
2608 i, region->mem_type, region->base_addr,
2609 region->offset, region->cumulative_size);
2610 }
2611
2612 return 0;
2613}
2614
2615static int wm_adsp_buffer_init(struct wm_adsp *dsp)
2616{
2617 struct wm_adsp_compr_buf *buf;
2618 int ret;
2619
2620 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
2621 if (!buf)
2622 return -ENOMEM;
2623
2624 buf->dsp = dsp;
2625
2626 ret = wm_adsp_buffer_locate(buf);
2627 if (ret < 0) {
2628 adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret);
2629 goto err_buffer;
2630 }
2631
2632 buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions,
2633 sizeof(*buf->regions), GFP_KERNEL);
2634 if (!buf->regions) {
2635 ret = -ENOMEM;
2636 goto err_buffer;
2637 }
2638
2639 ret = wm_adsp_buffer_populate(buf);
2640 if (ret < 0) {
2641 adsp_err(dsp, "Failed to populate host buffer: %d\n", ret);
2642 goto err_regions;
2643 }
2644
2645 dsp->buffer = buf;
2646
2647 return 0;
2648
2649err_regions:
2650 kfree(buf->regions);
2651err_buffer:
2652 kfree(buf);
2653 return ret;
2654}
2655
2656static int wm_adsp_buffer_free(struct wm_adsp *dsp)
2657{
2658 if (dsp->buffer) {
2659 kfree(dsp->buffer->regions);
2660 kfree(dsp->buffer);
2661
2662 dsp->buffer = NULL;
2663 }
2664
2665 return 0;
2666}
2667
95fe9597
CK		 2668static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2669{
2670 return compr->buf != NULL;
2671}
2672
2673static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
2674{
2675 /*
2676 * Note this will be more complex once each DSP can support multiple
2677 * streams
2678 */
2679 if (!compr->dsp->buffer)
2680 return -EINVAL;
2681
2682 compr->buf = compr->dsp->buffer;
2683
2684 return 0;
2685}
2686
2687int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
2688{
2689 struct wm_adsp_compr *compr = stream->runtime->private_data;
2690 struct wm_adsp *dsp = compr->dsp;
2691 int ret = 0;
2692
2693 adsp_dbg(dsp, "Trigger: %d\n", cmd);
2694
2695 mutex_lock(&dsp->pwr_lock);
2696
2697 switch (cmd) {
2698 case SNDRV_PCM_TRIGGER_START:
2699 if (wm_adsp_compr_attached(compr))
2700 break;
2701
2702 ret = wm_adsp_compr_attach(compr);
2703 if (ret < 0) {
2704 adsp_err(dsp, "Failed to link buffer and stream: %d\n",
2705 ret);
2706 break;
2707 }
2708 break;
2709 case SNDRV_PCM_TRIGGER_STOP:
2710 break;
2711 default:
2712 ret = -EINVAL;
2713 break;
2714 }
2715
2716 mutex_unlock(&dsp->pwr_lock);
2717
2718 return ret;
2719}
2720EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
2721
0a37c6ef 2722MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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