projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'nios2/for-next'
[deliverable/linux.git] / sound / soc / codecs / wm_hubs.c
CommitLineData
a2342ae3
MB		 1/*
2 * wm_hubs.c -- WM8993/4 common code
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
a2342ae3
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
79ef0abc 20#include <linux/mfd/wm8994/registers.h>
a2342ae3
MB		 21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
a2342ae3
MB		 25#include <sound/initval.h>
26#include <sound/tlv.h>
27
28#include "wm8993.h"
29#include "wm_hubs.h"
30
31const DECLARE_TLV_DB_SCALE(wm_hubs_spkmix_tlv, -300, 300, 0);
32EXPORT_SYMBOL_GPL(wm_hubs_spkmix_tlv);
33
34static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1650, 150, 0);
35static const DECLARE_TLV_DB_SCALE(inmix_sw_tlv, 0, 3000, 0);
36static const DECLARE_TLV_DB_SCALE(inmix_tlv, -1500, 300, 1);
37static const DECLARE_TLV_DB_SCALE(earpiece_tlv, -600, 600, 0);
38static const DECLARE_TLV_DB_SCALE(outmix_tlv, -2100, 300, 0);
39static const DECLARE_TLV_DB_SCALE(spkmixout_tlv, -1800, 600, 1);
40static const DECLARE_TLV_DB_SCALE(outpga_tlv, -5700, 100, 0);
2e45a25f 41static const DECLARE_TLV_DB_RANGE(spkboost_tlv,
a2342ae3 42 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
2e45a25f
LPC		 43 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0)
44);
a2342ae3
MB		 45static const DECLARE_TLV_DB_SCALE(line_tlv, -600, 600, 0);
46
47static const char *speaker_ref_text[] = {
48 "SPKVDD/2",
49 "VMID",
50};
51
abc4b4fb
TI		 52static SOC_ENUM_SINGLE_DECL(speaker_ref,
53 WM8993_SPEAKER_MIXER, 8, speaker_ref_text);
a2342ae3
MB		 54
55static const char *speaker_mode_text[] = {
56 "Class D",
57 "Class AB",
58};
59
abc4b4fb
TI		 60static SOC_ENUM_SINGLE_DECL(speaker_mode,
61 WM8993_SPKMIXR_ATTENUATION, 8, speaker_mode_text);
a2342ae3 62
4dcc93d0 63static void wait_for_dc_servo(struct snd_soc_codec *codec, unsigned int op)
a2342ae3 64{
d96ca3cd 65 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
a2342ae3
MB		 66 unsigned int reg;
67 int count = 0;
1479c3fb 68 int timeout;
4dcc93d0
MB		 69 unsigned int val;
70
71 val = op | WM8993_DCS_ENA_CHAN_0 | WM8993_DCS_ENA_CHAN_1;
72
73 /* Trigger the command */
74 snd_soc_write(codec, WM8993_DC_SERVO_0, val);
a2342ae3
MB		 75
76 dev_dbg(codec->dev, "Waiting for DC servo...\n");
3ed7074c 77
1479c3fb
MB		 78 if (hubs->dcs_done_irq)
79 timeout = 4;
80 else
81 timeout = 400;
d96ca3cd 82
1479c3fb
MB		 83 do {
84 count++;
85
86 if (hubs->dcs_done_irq)
87 wait_for_completion_timeout(&hubs->dcs_done,
88 msecs_to_jiffies(250));
89 else
d96ca3cd 90 msleep(1);
1479c3fb
MB		 91
92 reg = snd_soc_read(codec, WM8993_DC_SERVO_0);
93 dev_dbg(codec->dev, "DC servo: %x\n", reg);
94 } while (reg & op && count < timeout);
a2342ae3 95
4dcc93d0 96 if (reg & op)
5a9f91ca
MB		 97 dev_err(codec->dev, "Timed out waiting for DC Servo %x\n",
98 op);
a2342ae3
MB		 99}
100
d96ca3cd
MB		 101irqreturn_t wm_hubs_dcs_done(int irq, void *data)
102{
103 struct wm_hubs_data *hubs = data;
104
105 complete(&hubs->dcs_done);
106
107 return IRQ_HANDLED;
108}
109EXPORT_SYMBOL_GPL(wm_hubs_dcs_done);
110
af31a227
MB		 111static bool wm_hubs_dac_hp_direct(struct snd_soc_codec *codec)
112{
113 int reg;
114
115 /* If we're going via the mixer we'll need to do additional checks */
116 reg = snd_soc_read(codec, WM8993_OUTPUT_MIXER1);
117 if (!(reg & WM8993_DACL_TO_HPOUT1L)) {
118 if (reg & ~WM8993_DACL_TO_MIXOUTL) {
119 dev_vdbg(codec->dev, "Analogue paths connected: %x\n",
120 reg & ~WM8993_DACL_TO_HPOUT1L);
121 return false;
122 } else {
123 dev_vdbg(codec->dev, "HPL connected to mixer\n");
af31a227
MB		 124 }
125 } else {
126 dev_vdbg(codec->dev, "HPL connected to DAC\n");
127 }
128
129 reg = snd_soc_read(codec, WM8993_OUTPUT_MIXER2);
130 if (!(reg & WM8993_DACR_TO_HPOUT1R)) {
131 if (reg & ~WM8993_DACR_TO_MIXOUTR) {
132 dev_vdbg(codec->dev, "Analogue paths connected: %x\n",
133 reg & ~WM8993_DACR_TO_HPOUT1R);
134 return false;
135 } else {
136 dev_vdbg(codec->dev, "HPR connected to mixer\n");
af31a227
MB		 137 }
138 } else {
139 dev_vdbg(codec->dev, "HPR connected to DAC\n");
140 }
141
142 return true;
143}
144
94aa733a
MB		 145struct wm_hubs_dcs_cache {
146 struct list_head list;
147 unsigned int left;
148 unsigned int right;
149 u16 dcs_cfg;
150};
151
152static bool wm_hubs_dcs_cache_get(struct snd_soc_codec *codec,
153 struct wm_hubs_dcs_cache **entry)
154{
155 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
156 struct wm_hubs_dcs_cache *cache;
157 unsigned int left, right;
158
159 left = snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME);
160 left &= WM8993_HPOUT1L_VOL_MASK;
161
162 right = snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME);
163 right &= WM8993_HPOUT1R_VOL_MASK;
164
165 list_for_each_entry(cache, &hubs->dcs_cache, list) {
166 if (cache->left != left || cache->right != right)
167 continue;
168
169 *entry = cache;
170 return true;
171 }
172
173 return false;
174}
175
176static void wm_hubs_dcs_cache_set(struct snd_soc_codec *codec, u16 dcs_cfg)
177{
178 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
179 struct wm_hubs_dcs_cache *cache;
180
181 if (hubs->no_cache_dac_hp_direct)
182 return;
183
184 cache = devm_kzalloc(codec->dev, sizeof(*cache), GFP_KERNEL);
ba546687 185 if (!cache)
94aa733a 186 return;
94aa733a
MB		 187
188 cache->left = snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME);
189 cache->left &= WM8993_HPOUT1L_VOL_MASK;
190
191 cache->right = snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME);
192 cache->right &= WM8993_HPOUT1R_VOL_MASK;
193
194 cache->dcs_cfg = dcs_cfg;
195
196 list_add_tail(&cache->list, &hubs->dcs_cache);
197}
198
1f5353e7 199static int wm_hubs_read_dc_servo(struct snd_soc_codec *codec,
fae4efa2
MB		 200 u16 *reg_l, u16 *reg_r)
201{
202 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
203 u16 dcs_reg, reg;
1f5353e7 204 int ret = 0;
fae4efa2
MB		 205
206 switch (hubs->dcs_readback_mode) {
207 case 2:
208 dcs_reg = WM8994_DC_SERVO_4E;
209 break;
210 case 1:
211 dcs_reg = WM8994_DC_SERVO_READBACK;
212 break;
213 default:
214 dcs_reg = WM8993_DC_SERVO_3;
215 break;
216 }
217
218 /* Different chips in the family support different readback
219 * methods.
220 */
221 switch (hubs->dcs_readback_mode) {
222 case 0:
223 *reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1)
224 & WM8993_DCS_INTEG_CHAN_0_MASK;
225 *reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2)
226 & WM8993_DCS_INTEG_CHAN_1_MASK;
227 break;
228 case 2:
229 case 1:
230 reg = snd_soc_read(codec, dcs_reg);
231 *reg_r = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK)
232 >> WM8993_DCS_DAC_WR_VAL_1_SHIFT;
233 *reg_l = reg & WM8993_DCS_DAC_WR_VAL_0_MASK;
234 break;
235 default:
236 WARN(1, "Unknown DCS readback method\n");
1f5353e7 237 ret = -1;
fae4efa2 238 }
1f5353e7 239 return ret;
fae4efa2
MB		 240}
241
3ed7074c
MB		 242/*
243 * Startup calibration of the DC servo
244 */
a7892c35 245static void enable_dc_servo(struct snd_soc_codec *codec)
3ed7074c 246{
b2c812e2 247 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
94aa733a 248 struct wm_hubs_dcs_cache *cache;
20a4e7fc 249 s8 offset;
fae4efa2 250 u16 reg_l, reg_r, dcs_cfg, dcs_reg;
79ef0abc
MB		 251
252 switch (hubs->dcs_readback_mode) {
253 case 2:
254 dcs_reg = WM8994_DC_SERVO_4E;
255 break;
256 default:
257 dcs_reg = WM8993_DC_SERVO_3;
258 break;
259 }
3ed7074c 260
fec6dd83
MB		 261 /* If we're using a digital only path and have a previously
262 * callibrated DC servo offset stored then use that. */
94aa733a
MB		 263 if (wm_hubs_dac_hp_direct(codec) &&
264 wm_hubs_dcs_cache_get(codec, &cache)) {
265 dev_dbg(codec->dev, "Using cached DCS offset %x for %d,%d\n",
266 cache->dcs_cfg, cache->left, cache->right);
267 snd_soc_write(codec, dcs_reg, cache->dcs_cfg);
fec6dd83
MB		 268 wait_for_dc_servo(codec,
269 WM8993_DCS_TRIG_DAC_WR_0 |
270 WM8993_DCS_TRIG_DAC_WR_1);
271 return;
272 }
273
f9acf9fe 274 if (hubs->series_startup) {
11cef5f0
MB		 275 /* Set for 32 series updates */
276 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
277 WM8993_DCS_SERIES_NO_01_MASK,
278 32 << WM8993_DCS_SERIES_NO_01_SHIFT);
279 wait_for_dc_servo(codec,
280 WM8993_DCS_TRIG_SERIES_0 |
281 WM8993_DCS_TRIG_SERIES_1);
282 } else {
283 wait_for_dc_servo(codec,
284 WM8993_DCS_TRIG_STARTUP_0 |
285 WM8993_DCS_TRIG_STARTUP_1);
286 }
3ed7074c 287
1f5353e7
TG		 288 if (wm_hubs_read_dc_servo(codec, &reg_l, &reg_r) < 0)
289 return;
fec6dd83
MB		 290
291 dev_dbg(codec->dev, "DCS input: %x %x\n", reg_l, reg_r);
292
3ed7074c 293 /* Apply correction to DC servo result */
4537c4e7
MB		 294 if (hubs->dcs_codes_l || hubs->dcs_codes_r) {
295 dev_dbg(codec->dev,
296 "Applying %d/%d code DC servo correction\n",
297 hubs->dcs_codes_l, hubs->dcs_codes_r);
3ed7074c 298
d5b040c9 299 /* HPOUT1R */
363947d7 300 offset = (s8)reg_r;
20bac1f3
MB		 301 dev_dbg(codec->dev, "DCS right %d->%d\n", offset,
302 offset + hubs->dcs_codes_r);
4537c4e7 303 offset += hubs->dcs_codes_r;
20a4e7fc 304 dcs_cfg = (u8)offset << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
3ed7074c 305
d5b040c9 306 /* HPOUT1L */
363947d7 307 offset = (s8)reg_l;
20bac1f3
MB		 308 dev_dbg(codec->dev, "DCS left %d->%d\n", offset,
309 offset + hubs->dcs_codes_l);
4537c4e7 310 offset += hubs->dcs_codes_l;
20a4e7fc 311 dcs_cfg |= (u8)offset;
3ed7074c 312
3254d285
MB		 313 dev_dbg(codec->dev, "DCS result: %x\n", dcs_cfg);
314
3ed7074c 315 /* Do it */
79ef0abc 316 snd_soc_write(codec, dcs_reg, dcs_cfg);
4dcc93d0
MB		 317 wait_for_dc_servo(codec,
318 WM8993_DCS_TRIG_DAC_WR_0 |
319 WM8993_DCS_TRIG_DAC_WR_1);
fec6dd83 320 } else {
d5b040c9
MB		 321 dcs_cfg = reg_r << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
322 dcs_cfg |= reg_l;
3ed7074c 323 }
fec6dd83
MB		 324
325 /* Save the callibrated offset if we're in class W mode and
326 * therefore don't have any analogue signal mixed in. */
94aa733a
MB		 327 if (wm_hubs_dac_hp_direct(codec))
328 wm_hubs_dcs_cache_set(codec, dcs_cfg);
3ed7074c
MB		 329}
330
a2342ae3
MB		 331/*
332 * Update the DC servo calibration on gain changes
333 */
334static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
3ed7074c 335 struct snd_ctl_elem_value *ucontrol)
a2342ae3 336{
ea53bf77 337 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b2c812e2 338 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
a2342ae3
MB		 339 int ret;
340
c4671a95 341 ret = snd_soc_put_volsw(kcontrol, ucontrol);
a2342ae3 342
ae9d8607
MB		 343 /* If we're applying an offset correction then updating the
344 * callibration would be likely to introduce further offsets. */
4537c4e7 345 if (hubs->dcs_codes_l || hubs->dcs_codes_r || hubs->no_series_update)
ae9d8607
MB		 346 return ret;
347
a2342ae3
MB		 348 /* Only need to do this if the outputs are active */
349 if (snd_soc_read(codec, WM8993_POWER_MANAGEMENT_1)
350 & (WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA))
351 snd_soc_update_bits(codec,
352 WM8993_DC_SERVO_0,
353 WM8993_DCS_TRIG_SINGLE_0 |
354 WM8993_DCS_TRIG_SINGLE_1,
355 WM8993_DCS_TRIG_SINGLE_0 |
356 WM8993_DCS_TRIG_SINGLE_1);
357
358 return ret;
359}
360
361static const struct snd_kcontrol_new analogue_snd_controls[] = {
362SOC_SINGLE_TLV("IN1L Volume", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
363 inpga_tlv),
364SOC_SINGLE("IN1L Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
ea02c63d 365SOC_SINGLE("IN1L ZC Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
a2342ae3
MB		 366
367SOC_SINGLE_TLV("IN1R Volume", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
368 inpga_tlv),
369SOC_SINGLE("IN1R Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
ea02c63d 370SOC_SINGLE("IN1R ZC Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
a2342ae3
MB		 371
372
373SOC_SINGLE_TLV("IN2L Volume", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
374 inpga_tlv),
375SOC_SINGLE("IN2L Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
ea02c63d 376SOC_SINGLE("IN2L ZC Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
a2342ae3
MB		 377
378SOC_SINGLE_TLV("IN2R Volume", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
379 inpga_tlv),
380SOC_SINGLE("IN2R Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
ea02c63d 381SOC_SINGLE("IN2R ZC Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
a2342ae3
MB		 382
383SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8993_INPUT_MIXER3, 7, 1, 0,
384 inmix_sw_tlv),
385SOC_SINGLE_TLV("MIXINL IN1L Volume", WM8993_INPUT_MIXER3, 4, 1, 0,
386 inmix_sw_tlv),
387SOC_SINGLE_TLV("MIXINL Output Record Volume", WM8993_INPUT_MIXER3, 0, 7, 0,
388 inmix_tlv),
389SOC_SINGLE_TLV("MIXINL IN1LP Volume", WM8993_INPUT_MIXER5, 6, 7, 0, inmix_tlv),
390SOC_SINGLE_TLV("MIXINL Direct Voice Volume", WM8993_INPUT_MIXER5, 0, 6, 0,
391 inmix_tlv),
392
393SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8993_INPUT_MIXER4, 7, 1, 0,
394 inmix_sw_tlv),
395SOC_SINGLE_TLV("MIXINR IN1R Volume", WM8993_INPUT_MIXER4, 4, 1, 0,
396 inmix_sw_tlv),
397SOC_SINGLE_TLV("MIXINR Output Record Volume", WM8993_INPUT_MIXER4, 0, 7, 0,
398 inmix_tlv),
399SOC_SINGLE_TLV("MIXINR IN1RP Volume", WM8993_INPUT_MIXER6, 6, 7, 0, inmix_tlv),
400SOC_SINGLE_TLV("MIXINR Direct Voice Volume", WM8993_INPUT_MIXER6, 0, 6, 0,
401 inmix_tlv),
402
403SOC_SINGLE_TLV("Left Output Mixer IN2RN Volume", WM8993_OUTPUT_MIXER5, 6, 7, 1,
404 outmix_tlv),
405SOC_SINGLE_TLV("Left Output Mixer IN2LN Volume", WM8993_OUTPUT_MIXER3, 6, 7, 1,
406 outmix_tlv),
407SOC_SINGLE_TLV("Left Output Mixer IN2LP Volume", WM8993_OUTPUT_MIXER3, 9, 7, 1,
408 outmix_tlv),
409SOC_SINGLE_TLV("Left Output Mixer IN1L Volume", WM8993_OUTPUT_MIXER3, 0, 7, 1,
410 outmix_tlv),
411SOC_SINGLE_TLV("Left Output Mixer IN1R Volume", WM8993_OUTPUT_MIXER3, 3, 7, 1,
412 outmix_tlv),
413SOC_SINGLE_TLV("Left Output Mixer Right Input Volume",
414 WM8993_OUTPUT_MIXER5, 3, 7, 1, outmix_tlv),
415SOC_SINGLE_TLV("Left Output Mixer Left Input Volume",
416 WM8993_OUTPUT_MIXER5, 0, 7, 1, outmix_tlv),
417SOC_SINGLE_TLV("Left Output Mixer DAC Volume", WM8993_OUTPUT_MIXER5, 9, 7, 1,
418 outmix_tlv),
419
420SOC_SINGLE_TLV("Right Output Mixer IN2LN Volume",
421 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
422SOC_SINGLE_TLV("Right Output Mixer IN2RN Volume",
423 WM8993_OUTPUT_MIXER4, 6, 7, 1, outmix_tlv),
424SOC_SINGLE_TLV("Right Output Mixer IN1L Volume",
425 WM8993_OUTPUT_MIXER4, 3, 7, 1, outmix_tlv),
426SOC_SINGLE_TLV("Right Output Mixer IN1R Volume",
427 WM8993_OUTPUT_MIXER4, 0, 7, 1, outmix_tlv),
428SOC_SINGLE_TLV("Right Output Mixer IN2RP Volume",
429 WM8993_OUTPUT_MIXER4, 9, 7, 1, outmix_tlv),
430SOC_SINGLE_TLV("Right Output Mixer Left Input Volume",
431 WM8993_OUTPUT_MIXER6, 3, 7, 1, outmix_tlv),
432SOC_SINGLE_TLV("Right Output Mixer Right Input Volume",
433 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
434SOC_SINGLE_TLV("Right Output Mixer DAC Volume",
435 WM8993_OUTPUT_MIXER6, 9, 7, 1, outmix_tlv),
436
437SOC_DOUBLE_R_TLV("Output Volume", WM8993_LEFT_OPGA_VOLUME,
438 WM8993_RIGHT_OPGA_VOLUME, 0, 63, 0, outpga_tlv),
439SOC_DOUBLE_R("Output Switch", WM8993_LEFT_OPGA_VOLUME,
440 WM8993_RIGHT_OPGA_VOLUME, 6, 1, 0),
441SOC_DOUBLE_R("Output ZC Switch", WM8993_LEFT_OPGA_VOLUME,
442 WM8993_RIGHT_OPGA_VOLUME, 7, 1, 0),
443
444SOC_SINGLE("Earpiece Switch", WM8993_HPOUT2_VOLUME, 5, 1, 1),
445SOC_SINGLE_TLV("Earpiece Volume", WM8993_HPOUT2_VOLUME, 4, 1, 1, earpiece_tlv),
446
447SOC_SINGLE_TLV("SPKL Input Volume", WM8993_SPKMIXL_ATTENUATION,
448 5, 1, 1, wm_hubs_spkmix_tlv),
449SOC_SINGLE_TLV("SPKL IN1LP Volume", WM8993_SPKMIXL_ATTENUATION,
450 4, 1, 1, wm_hubs_spkmix_tlv),
451SOC_SINGLE_TLV("SPKL Output Volume", WM8993_SPKMIXL_ATTENUATION,
452 3, 1, 1, wm_hubs_spkmix_tlv),
453
454SOC_SINGLE_TLV("SPKR Input Volume", WM8993_SPKMIXR_ATTENUATION,
455 5, 1, 1, wm_hubs_spkmix_tlv),
456SOC_SINGLE_TLV("SPKR IN1RP Volume", WM8993_SPKMIXR_ATTENUATION,
457 4, 1, 1, wm_hubs_spkmix_tlv),
458SOC_SINGLE_TLV("SPKR Output Volume", WM8993_SPKMIXR_ATTENUATION,
459 3, 1, 1, wm_hubs_spkmix_tlv),
460
461SOC_DOUBLE_R_TLV("Speaker Mixer Volume",
462 WM8993_SPKMIXL_ATTENUATION, WM8993_SPKMIXR_ATTENUATION,
463 0, 3, 1, spkmixout_tlv),
464SOC_DOUBLE_R_TLV("Speaker Volume",
465 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
466 0, 63, 0, outpga_tlv),
467SOC_DOUBLE_R("Speaker Switch",
468 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
469 6, 1, 0),
470SOC_DOUBLE_R("Speaker ZC Switch",
471 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
472 7, 1, 0),
ed8cc471 473SOC_DOUBLE_TLV("Speaker Boost Volume", WM8993_SPKOUT_BOOST, 3, 0, 7, 0,
a2342ae3
MB		 474 spkboost_tlv),
475SOC_ENUM("Speaker Reference", speaker_ref),
476SOC_ENUM("Speaker Mode", speaker_mode),
477
0f9887d1
PU		 478SOC_DOUBLE_R_EXT_TLV("Headphone Volume",
479 WM8993_LEFT_OUTPUT_VOLUME, WM8993_RIGHT_OUTPUT_VOLUME,
c4671a95 480 0, 63, 0, snd_soc_get_volsw, wm8993_put_dc_servo,
0f9887d1
PU		 481 outpga_tlv),
482
a2342ae3
MB		 483SOC_DOUBLE_R("Headphone Switch", WM8993_LEFT_OUTPUT_VOLUME,
484 WM8993_RIGHT_OUTPUT_VOLUME, 6, 1, 0),
485SOC_DOUBLE_R("Headphone ZC Switch", WM8993_LEFT_OUTPUT_VOLUME,
486 WM8993_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
487
488SOC_SINGLE("LINEOUT1N Switch", WM8993_LINE_OUTPUTS_VOLUME, 6, 1, 1),
489SOC_SINGLE("LINEOUT1P Switch", WM8993_LINE_OUTPUTS_VOLUME, 5, 1, 1),
490SOC_SINGLE_TLV("LINEOUT1 Volume", WM8993_LINE_OUTPUTS_VOLUME, 4, 1, 1,
491 line_tlv),
492
493SOC_SINGLE("LINEOUT2N Switch", WM8993_LINE_OUTPUTS_VOLUME, 2, 1, 1),
494SOC_SINGLE("LINEOUT2P Switch", WM8993_LINE_OUTPUTS_VOLUME, 1, 1, 1),
495SOC_SINGLE_TLV("LINEOUT2 Volume", WM8993_LINE_OUTPUTS_VOLUME, 0, 1, 1,
496 line_tlv),
497};
498
3ed7074c
MB		 499static int hp_supply_event(struct snd_soc_dapm_widget *w,
500 struct snd_kcontrol *kcontrol, int event)
501{
0201e505 502 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
b2c812e2 503 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
3ed7074c
MB		 504
505 switch (event) {
506 case SND_SOC_DAPM_PRE_PMU:
507 switch (hubs->hp_startup_mode) {
508 case 0:
509 break;
510 case 1:
511 /* Enable the headphone amp */
512 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
513 WM8993_HPOUT1L_ENA |
514 WM8993_HPOUT1R_ENA,
515 WM8993_HPOUT1L_ENA |
516 WM8993_HPOUT1R_ENA);
517
518 /* Enable the second stage */
519 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
520 WM8993_HPOUT1L_DLY |
521 WM8993_HPOUT1R_DLY,
522 WM8993_HPOUT1L_DLY |
523 WM8993_HPOUT1R_DLY);
524 break;
525 default:
526 dev_err(codec->dev, "Unknown HP startup mode %d\n",
527 hubs->hp_startup_mode);
528 break;
529 }
268ff145 530 break;
3ed7074c
MB		 531
532 case SND_SOC_DAPM_PRE_PMD:
533 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
534 WM8993_CP_ENA, 0);
535 break;
536 }
537
538 return 0;
539}
540
a2342ae3
MB		 541static int hp_event(struct snd_soc_dapm_widget *w,
542 struct snd_kcontrol *kcontrol, int event)
543{
0201e505 544 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
a2342ae3
MB		 545 unsigned int reg = snd_soc_read(codec, WM8993_ANALOGUE_HP_0);
546
547 switch (event) {
548 case SND_SOC_DAPM_POST_PMU:
549 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
550 WM8993_CP_ENA, WM8993_CP_ENA);
551
552 msleep(5);
553
554 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
555 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
556 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA);
557
558 reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
559 snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
560
3ed7074c 561 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
f9925d44 562 WM8993_DCS_TIMER_PERIOD_01_MASK, 0);
3ed7074c 563
a7892c35 564 enable_dc_servo(codec);
a2342ae3
MB		 565
566 reg |= WM8993_HPOUT1R_OUTP | WM8993_HPOUT1R_RMV_SHORT |
567 WM8993_HPOUT1L_OUTP | WM8993_HPOUT1L_RMV_SHORT;
568 snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
569 break;
570
571 case SND_SOC_DAPM_PRE_PMD:
3ed7074c 572 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
6adb26bd
MB		 573 WM8993_HPOUT1L_OUTP |
574 WM8993_HPOUT1R_OUTP |
3ed7074c
MB		 575 WM8993_HPOUT1L_RMV_SHORT |
576 WM8993_HPOUT1R_RMV_SHORT, 0);
a2342ae3 577
3ed7074c 578 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
6adb26bd
MB		 579 WM8993_HPOUT1L_DLY |
580 WM8993_HPOUT1R_DLY, 0);
a2342ae3 581
395e4b73
MB		 582 snd_soc_write(codec, WM8993_DC_SERVO_0, 0);
583
a2342ae3
MB		 584 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
585 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
586 0);
a2342ae3
MB		 587 break;
588 }
589
590 return 0;
591}
592
593static int earpiece_event(struct snd_soc_dapm_widget *w,
594 struct snd_kcontrol *control, int event)
595{
0201e505 596 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
a2342ae3
MB		 597 u16 reg = snd_soc_read(codec, WM8993_ANTIPOP1) & ~WM8993_HPOUT2_IN_ENA;
598
599 switch (event) {
600 case SND_SOC_DAPM_PRE_PMU:
601 reg |= WM8993_HPOUT2_IN_ENA;
602 snd_soc_write(codec, WM8993_ANTIPOP1, reg);
603 udelay(50);
604 break;
605
606 case SND_SOC_DAPM_POST_PMD:
607 snd_soc_write(codec, WM8993_ANTIPOP1, reg);
608 break;
609
610 default:
9a743400 611 WARN(1, "Invalid event %d\n", event);
a2342ae3
MB		 612 break;
613 }
614
615 return 0;
616}
617
5f2f3890
MB		 618static int lineout_event(struct snd_soc_dapm_widget *w,
619 struct snd_kcontrol *control, int event)
620{
0201e505 621 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5f2f3890
MB		 622 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
623 bool *flag;
624
625 switch (w->shift) {
626 case WM8993_LINEOUT1N_ENA_SHIFT:
627 flag = &hubs->lineout1n_ena;
628 break;
629 case WM8993_LINEOUT1P_ENA_SHIFT:
630 flag = &hubs->lineout1p_ena;
631 break;
632 case WM8993_LINEOUT2N_ENA_SHIFT:
633 flag = &hubs->lineout2n_ena;
634 break;
635 case WM8993_LINEOUT2P_ENA_SHIFT:
636 flag = &hubs->lineout2p_ena;
637 break;
638 default:
639 WARN(1, "Unknown line output");
640 return -EINVAL;
641 }
642
643 *flag = SND_SOC_DAPM_EVENT_ON(event);
644
645 return 0;
646}
647
02e79476
MB		 648static int micbias_event(struct snd_soc_dapm_widget *w,
649 struct snd_kcontrol *kcontrol, int event)
650{
0201e505 651 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
02e79476
MB		 652 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
653
654 switch (w->shift) {
655 case WM8993_MICB1_ENA_SHIFT:
656 if (hubs->micb1_delay)
657 msleep(hubs->micb1_delay);
658 break;
659 case WM8993_MICB2_ENA_SHIFT:
660 if (hubs->micb2_delay)
661 msleep(hubs->micb2_delay);
662 break;
663 default:
664 return -EINVAL;
665 }
666
667 return 0;
668}
669
c340304d
MB		 670void wm_hubs_update_class_w(struct snd_soc_codec *codec)
671{
672 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
673 int enable = WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ;
674
675 if (!wm_hubs_dac_hp_direct(codec))
676 enable = false;
677
678 if (hubs->check_class_w_digital && !hubs->check_class_w_digital(codec))
679 enable = false;
680
681 dev_vdbg(codec->dev, "Class W %s\n", enable ? "enabled" : "disabled");
682
683 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
684 WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ, enable);
eb4d5fc1
MB		 685
686 snd_soc_write(codec, WM8993_LEFT_OUTPUT_VOLUME,
687 snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME));
688 snd_soc_write(codec, WM8993_RIGHT_OUTPUT_VOLUME,
689 snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME));
c340304d
MB		 690}
691EXPORT_SYMBOL_GPL(wm_hubs_update_class_w);
692
04de57c1 693#define WM_HUBS_SINGLE_W(xname, reg, shift, max, invert) \
98809ae2
LPC		 694 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
695 snd_soc_dapm_get_volsw, class_w_put_volsw)
04de57c1
MB		 696
697static int class_w_put_volsw(struct snd_kcontrol *kcontrol,
698 struct snd_ctl_elem_value *ucontrol)
699{
eee5d7f9 700 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
04de57c1
MB		 701 int ret;
702
703 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
704
705 wm_hubs_update_class_w(codec);
706
707 return ret;
708}
709
c340304d
MB		 710#define WM_HUBS_ENUM_W(xname, xenum) \
711{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
712 .info = snd_soc_info_enum_double, \
713 .get = snd_soc_dapm_get_enum_double, \
04de57c1 714 .put = class_w_put_double, \
c340304d
MB		 715 .private_value = (unsigned long)&xenum }
716
04de57c1
MB		 717static int class_w_put_double(struct snd_kcontrol *kcontrol,
718 struct snd_ctl_elem_value *ucontrol)
c340304d 719{
eee5d7f9 720 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
c340304d
MB		 721 int ret;
722
723 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
724
725 wm_hubs_update_class_w(codec);
726
727 return ret;
728}
729
730static const char *hp_mux_text[] = {
731 "Mixer",
732 "DAC",
733};
734
abc4b4fb
TI		 735static SOC_ENUM_SINGLE_DECL(hpl_enum,
736 WM8993_OUTPUT_MIXER1, 8, hp_mux_text);
c340304d
MB		 737
738const struct snd_kcontrol_new wm_hubs_hpl_mux =
739 WM_HUBS_ENUM_W("Left Headphone Mux", hpl_enum);
740EXPORT_SYMBOL_GPL(wm_hubs_hpl_mux);
741
abc4b4fb
TI		 742static SOC_ENUM_SINGLE_DECL(hpr_enum,
743 WM8993_OUTPUT_MIXER2, 8, hp_mux_text);
c340304d
MB		 744
745const struct snd_kcontrol_new wm_hubs_hpr_mux =
746 WM_HUBS_ENUM_W("Right Headphone Mux", hpr_enum);
747EXPORT_SYMBOL_GPL(wm_hubs_hpr_mux);
748
a2342ae3
MB		 749static const struct snd_kcontrol_new in1l_pga[] = {
750SOC_DAPM_SINGLE("IN1LP Switch", WM8993_INPUT_MIXER2, 5, 1, 0),
751SOC_DAPM_SINGLE("IN1LN Switch", WM8993_INPUT_MIXER2, 4, 1, 0),
752};
753
754static const struct snd_kcontrol_new in1r_pga[] = {
755SOC_DAPM_SINGLE("IN1RP Switch", WM8993_INPUT_MIXER2, 1, 1, 0),
756SOC_DAPM_SINGLE("IN1RN Switch", WM8993_INPUT_MIXER2, 0, 1, 0),
757};
758
759static const struct snd_kcontrol_new in2l_pga[] = {
760SOC_DAPM_SINGLE("IN2LP Switch", WM8993_INPUT_MIXER2, 7, 1, 0),
761SOC_DAPM_SINGLE("IN2LN Switch", WM8993_INPUT_MIXER2, 6, 1, 0),
762};
763
764static const struct snd_kcontrol_new in2r_pga[] = {
765SOC_DAPM_SINGLE("IN2RP Switch", WM8993_INPUT_MIXER2, 3, 1, 0),
766SOC_DAPM_SINGLE("IN2RN Switch", WM8993_INPUT_MIXER2, 2, 1, 0),
767};
768
769static const struct snd_kcontrol_new mixinl[] = {
770SOC_DAPM_SINGLE("IN2L Switch", WM8993_INPUT_MIXER3, 8, 1, 0),
771SOC_DAPM_SINGLE("IN1L Switch", WM8993_INPUT_MIXER3, 5, 1, 0),
772};
773
774static const struct snd_kcontrol_new mixinr[] = {
775SOC_DAPM_SINGLE("IN2R Switch", WM8993_INPUT_MIXER4, 8, 1, 0),
776SOC_DAPM_SINGLE("IN1R Switch", WM8993_INPUT_MIXER4, 5, 1, 0),
777};
778
779static const struct snd_kcontrol_new left_output_mixer[] = {
04de57c1
MB		 780WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER1, 7, 1, 0),
781WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER1, 6, 1, 0),
782WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER1, 5, 1, 0),
783WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER1, 4, 1, 0),
784WM_HUBS_SINGLE_W("IN2LP Switch", WM8993_OUTPUT_MIXER1, 1, 1, 0),
785WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER1, 3, 1, 0),
786WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER1, 2, 1, 0),
787WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER1, 0, 1, 0),
a2342ae3
MB		 788};
789
790static const struct snd_kcontrol_new right_output_mixer[] = {
04de57c1
MB		 791WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER2, 7, 1, 0),
792WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER2, 6, 1, 0),
793WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER2, 5, 1, 0),
794WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER2, 4, 1, 0),
795WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER2, 3, 1, 0),
796WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER2, 2, 1, 0),
797WM_HUBS_SINGLE_W("IN2RP Switch", WM8993_OUTPUT_MIXER2, 1, 1, 0),
798WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER2, 0, 1, 0),
a2342ae3
MB		 799};
800
801static const struct snd_kcontrol_new earpiece_mixer[] = {
802SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_HPOUT2_MIXER, 5, 1, 0),
803SOC_DAPM_SINGLE("Left Output Switch", WM8993_HPOUT2_MIXER, 4, 1, 0),
804SOC_DAPM_SINGLE("Right Output Switch", WM8993_HPOUT2_MIXER, 3, 1, 0),
805};
806
807static const struct snd_kcontrol_new left_speaker_boost[] = {
808SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 5, 1, 0),
809SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 4, 1, 0),
810SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 3, 1, 0),
811};
812
813static const struct snd_kcontrol_new right_speaker_boost[] = {
814SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 2, 1, 0),
815SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 1, 1, 0),
816SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 0, 1, 0),
817};
818
819static const struct snd_kcontrol_new line1_mix[] = {
820SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER1, 2, 1, 0),
821SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER1, 1, 1, 0),
822SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
823};
824
825static const struct snd_kcontrol_new line1n_mix[] = {
826SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 6, 1, 0),
827SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER1, 5, 1, 0),
828};
829
830static const struct snd_kcontrol_new line1p_mix[] = {
831SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
832};
833
834static const struct snd_kcontrol_new line2_mix[] = {
43b6cec2
MB		 835SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER2, 2, 1, 0),
836SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER2, 1, 1, 0),
a2342ae3
MB		 837SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
838};
839
840static const struct snd_kcontrol_new line2n_mix[] = {
114395c6
UK		 841SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER2, 5, 1, 0),
842SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 6, 1, 0),
a2342ae3
MB		 843};
844
845static const struct snd_kcontrol_new line2p_mix[] = {
846SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
847};
848
849static const struct snd_soc_dapm_widget analogue_dapm_widgets[] = {
850SND_SOC_DAPM_INPUT("IN1LN"),
851SND_SOC_DAPM_INPUT("IN1LP"),
852SND_SOC_DAPM_INPUT("IN2LN"),
34825948 853SND_SOC_DAPM_INPUT("IN2LP:VXRN"),
a2342ae3
MB		 854SND_SOC_DAPM_INPUT("IN1RN"),
855SND_SOC_DAPM_INPUT("IN1RP"),
856SND_SOC_DAPM_INPUT("IN2RN"),
34825948 857SND_SOC_DAPM_INPUT("IN2RP:VXRP"),
a2342ae3 858
02e79476
MB		 859SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8993_POWER_MANAGEMENT_1, 5, 0,
860 micbias_event, SND_SOC_DAPM_POST_PMU),
861SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8993_POWER_MANAGEMENT_1, 4, 0,
862 micbias_event, SND_SOC_DAPM_POST_PMU),
a2342ae3
MB		 863
864SND_SOC_DAPM_MIXER("IN1L PGA", WM8993_POWER_MANAGEMENT_2, 6, 0,
865 in1l_pga, ARRAY_SIZE(in1l_pga)),
866SND_SOC_DAPM_MIXER("IN1R PGA", WM8993_POWER_MANAGEMENT_2, 4, 0,
867 in1r_pga, ARRAY_SIZE(in1r_pga)),
868
869SND_SOC_DAPM_MIXER("IN2L PGA", WM8993_POWER_MANAGEMENT_2, 7, 0,
870 in2l_pga, ARRAY_SIZE(in2l_pga)),
871SND_SOC_DAPM_MIXER("IN2R PGA", WM8993_POWER_MANAGEMENT_2, 5, 0,
872 in2r_pga, ARRAY_SIZE(in2r_pga)),
873
a2342ae3
MB		 874SND_SOC_DAPM_MIXER("MIXINL", WM8993_POWER_MANAGEMENT_2, 9, 0,
875 mixinl, ARRAY_SIZE(mixinl)),
876SND_SOC_DAPM_MIXER("MIXINR", WM8993_POWER_MANAGEMENT_2, 8, 0,
877 mixinr, ARRAY_SIZE(mixinr)),
878
a2342ae3
MB		 879SND_SOC_DAPM_MIXER("Left Output Mixer", WM8993_POWER_MANAGEMENT_3, 5, 0,
880 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
881SND_SOC_DAPM_MIXER("Right Output Mixer", WM8993_POWER_MANAGEMENT_3, 4, 0,
882 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
883
884SND_SOC_DAPM_PGA("Left Output PGA", WM8993_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
885SND_SOC_DAPM_PGA("Right Output PGA", WM8993_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
886
3ed7074c
MB		 887SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, hp_supply_event,
888 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
26422625
MB		 889SND_SOC_DAPM_OUT_DRV_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
890 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
a2342ae3
MB		 891
892SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
893 earpiece_mixer, ARRAY_SIZE(earpiece_mixer)),
894SND_SOC_DAPM_PGA_E("Earpiece Driver", WM8993_POWER_MANAGEMENT_1, 11, 0,
895 NULL, 0, earpiece_event,
896 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
897
898SND_SOC_DAPM_MIXER("SPKL Boost", SND_SOC_NOPM, 0, 0,
899 left_speaker_boost, ARRAY_SIZE(left_speaker_boost)),
900SND_SOC_DAPM_MIXER("SPKR Boost", SND_SOC_NOPM, 0, 0,
901 right_speaker_boost, ARRAY_SIZE(right_speaker_boost)),
902
03431972 903SND_SOC_DAPM_SUPPLY("TSHUT", WM8993_POWER_MANAGEMENT_2, 14, 0, NULL, 0),
dc9c7454
MB		 904SND_SOC_DAPM_OUT_DRV("SPKL Driver", WM8993_POWER_MANAGEMENT_1, 12, 0,
905 NULL, 0),
906SND_SOC_DAPM_OUT_DRV("SPKR Driver", WM8993_POWER_MANAGEMENT_1, 13, 0,
907 NULL, 0),
a2342ae3
MB		 908
909SND_SOC_DAPM_MIXER("LINEOUT1 Mixer", SND_SOC_NOPM, 0, 0,
910 line1_mix, ARRAY_SIZE(line1_mix)),
911SND_SOC_DAPM_MIXER("LINEOUT2 Mixer", SND_SOC_NOPM, 0, 0,
912 line2_mix, ARRAY_SIZE(line2_mix)),
913
914SND_SOC_DAPM_MIXER("LINEOUT1N Mixer", SND_SOC_NOPM, 0, 0,
915 line1n_mix, ARRAY_SIZE(line1n_mix)),
916SND_SOC_DAPM_MIXER("LINEOUT1P Mixer", SND_SOC_NOPM, 0, 0,
917 line1p_mix, ARRAY_SIZE(line1p_mix)),
918SND_SOC_DAPM_MIXER("LINEOUT2N Mixer", SND_SOC_NOPM, 0, 0,
919 line2n_mix, ARRAY_SIZE(line2n_mix)),
920SND_SOC_DAPM_MIXER("LINEOUT2P Mixer", SND_SOC_NOPM, 0, 0,
921 line2p_mix, ARRAY_SIZE(line2p_mix)),
922
5f2f3890
MB		 923SND_SOC_DAPM_OUT_DRV_E("LINEOUT1N Driver", WM8993_POWER_MANAGEMENT_3, 13, 0,
924 NULL, 0, lineout_event,
925 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
926SND_SOC_DAPM_OUT_DRV_E("LINEOUT1P Driver", WM8993_POWER_MANAGEMENT_3, 12, 0,
927 NULL, 0, lineout_event,
928 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
929SND_SOC_DAPM_OUT_DRV_E("LINEOUT2N Driver", WM8993_POWER_MANAGEMENT_3, 11, 0,
930 NULL, 0, lineout_event,
931 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
932SND_SOC_DAPM_OUT_DRV_E("LINEOUT2P Driver", WM8993_POWER_MANAGEMENT_3, 10, 0,
933 NULL, 0, lineout_event,
934 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
a2342ae3
MB		 935
936SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
937SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
938SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
939SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
940SND_SOC_DAPM_OUTPUT("HPOUT1L"),
941SND_SOC_DAPM_OUTPUT("HPOUT1R"),
942SND_SOC_DAPM_OUTPUT("HPOUT2P"),
943SND_SOC_DAPM_OUTPUT("HPOUT2N"),
944SND_SOC_DAPM_OUTPUT("LINEOUT1P"),
945SND_SOC_DAPM_OUTPUT("LINEOUT1N"),
946SND_SOC_DAPM_OUTPUT("LINEOUT2P"),
947SND_SOC_DAPM_OUTPUT("LINEOUT2N"),
948};
949
950static const struct snd_soc_dapm_route analogue_routes[] = {
4baafdd7
MB		 951 { "MICBIAS1", NULL, "CLK_SYS" },
952 { "MICBIAS2", NULL, "CLK_SYS" },
953
a2342ae3
MB		 954 { "IN1L PGA", "IN1LP Switch", "IN1LP" },
955 { "IN1L PGA", "IN1LN Switch", "IN1LN" },
956
4e04adaf
MB		 957 { "IN1L PGA", NULL, "VMID" },
958 { "IN1R PGA", NULL, "VMID" },
959 { "IN2L PGA", NULL, "VMID" },
960 { "IN2R PGA", NULL, "VMID" },
961
a2342ae3
MB		 962 { "IN1R PGA", "IN1RP Switch", "IN1RP" },
963 { "IN1R PGA", "IN1RN Switch", "IN1RN" },
964
34825948 965 { "IN2L PGA", "IN2LP Switch", "IN2LP:VXRN" },
a2342ae3
MB		 966 { "IN2L PGA", "IN2LN Switch", "IN2LN" },
967
34825948 968 { "IN2R PGA", "IN2RP Switch", "IN2RP:VXRP" },
a2342ae3
MB		 969 { "IN2R PGA", "IN2RN Switch", "IN2RN" },
970
34825948
JS		 971 { "Direct Voice", NULL, "IN2LP:VXRN" },
972 { "Direct Voice", NULL, "IN2RP:VXRP" },
a2342ae3
MB		 973
974 { "MIXINL", "IN1L Switch", "IN1L PGA" },
975 { "MIXINL", "IN2L Switch", "IN2L PGA" },
976 { "MIXINL", NULL, "Direct Voice" },
977 { "MIXINL", NULL, "IN1LP" },
978 { "MIXINL", NULL, "Left Output Mixer" },
4e04adaf 979 { "MIXINL", NULL, "VMID" },
a2342ae3
MB		 980
981 { "MIXINR", "IN1R Switch", "IN1R PGA" },
982 { "MIXINR", "IN2R Switch", "IN2R PGA" },
983 { "MIXINR", NULL, "Direct Voice" },
984 { "MIXINR", NULL, "IN1RP" },
985 { "MIXINR", NULL, "Right Output Mixer" },
4e04adaf 986 { "MIXINR", NULL, "VMID" },
a2342ae3
MB		 987
988 { "ADCL", NULL, "MIXINL" },
989 { "ADCR", NULL, "MIXINR" },
990
991 { "Left Output Mixer", "Left Input Switch", "MIXINL" },
992 { "Left Output Mixer", "Right Input Switch", "MIXINR" },
993 { "Left Output Mixer", "IN2RN Switch", "IN2RN" },
994 { "Left Output Mixer", "IN2LN Switch", "IN2LN" },
34825948 995 { "Left Output Mixer", "IN2LP Switch", "IN2LP:VXRN" },
a2342ae3
MB		 996 { "Left Output Mixer", "IN1L Switch", "IN1L PGA" },
997 { "Left Output Mixer", "IN1R Switch", "IN1R PGA" },
998
999 { "Right Output Mixer", "Left Input Switch", "MIXINL" },
1000 { "Right Output Mixer", "Right Input Switch", "MIXINR" },
1001 { "Right Output Mixer", "IN2LN Switch", "IN2LN" },
1002 { "Right Output Mixer", "IN2RN Switch", "IN2RN" },
34825948 1003 { "Right Output Mixer", "IN2RP Switch", "IN2RP:VXRP" },
a2342ae3
MB		 1004 { "Right Output Mixer", "IN1L Switch", "IN1L PGA" },
1005 { "Right Output Mixer", "IN1R Switch", "IN1R PGA" },
1006
1007 { "Left Output PGA", NULL, "Left Output Mixer" },
1008 { "Left Output PGA", NULL, "TOCLK" },
1009
1010 { "Right Output PGA", NULL, "Right Output Mixer" },
1011 { "Right Output PGA", NULL, "TOCLK" },
1012
1013 { "Earpiece Mixer", "Direct Voice Switch", "Direct Voice" },
1014 { "Earpiece Mixer", "Left Output Switch", "Left Output PGA" },
1015 { "Earpiece Mixer", "Right Output Switch", "Right Output PGA" },
1016
4e04adaf 1017 { "Earpiece Driver", NULL, "VMID" },
a2342ae3
MB		 1018 { "Earpiece Driver", NULL, "Earpiece Mixer" },
1019 { "HPOUT2N", NULL, "Earpiece Driver" },
1020 { "HPOUT2P", NULL, "Earpiece Driver" },
1021
1022 { "SPKL", "Input Switch", "MIXINL" },
1023 { "SPKL", "IN1LP Switch", "IN1LP" },
39cca168 1024 { "SPKL", "Output Switch", "Left Output PGA" },
a2342ae3
MB		 1025 { "SPKL", NULL, "TOCLK" },
1026
1027 { "SPKR", "Input Switch", "MIXINR" },
1028 { "SPKR", "IN1RP Switch", "IN1RP" },
39cca168 1029 { "SPKR", "Output Switch", "Right Output PGA" },
a2342ae3
MB		 1030 { "SPKR", NULL, "TOCLK" },
1031
1032 { "SPKL Boost", "Direct Voice Switch", "Direct Voice" },
1033 { "SPKL Boost", "SPKL Switch", "SPKL" },
1034 { "SPKL Boost", "SPKR Switch", "SPKR" },
1035
1036 { "SPKR Boost", "Direct Voice Switch", "Direct Voice" },
1037 { "SPKR Boost", "SPKR Switch", "SPKR" },
1038 { "SPKR Boost", "SPKL Switch", "SPKL" },
1039
4e04adaf 1040 { "SPKL Driver", NULL, "VMID" },
a2342ae3
MB		 1041 { "SPKL Driver", NULL, "SPKL Boost" },
1042 { "SPKL Driver", NULL, "CLK_SYS" },
03431972 1043 { "SPKL Driver", NULL, "TSHUT" },
a2342ae3 1044
4e04adaf 1045 { "SPKR Driver", NULL, "VMID" },
a2342ae3
MB		 1046 { "SPKR Driver", NULL, "SPKR Boost" },
1047 { "SPKR Driver", NULL, "CLK_SYS" },
03431972 1048 { "SPKR Driver", NULL, "TSHUT" },
a2342ae3
MB		 1049
1050 { "SPKOUTLP", NULL, "SPKL Driver" },
1051 { "SPKOUTLN", NULL, "SPKL Driver" },
1052 { "SPKOUTRP", NULL, "SPKR Driver" },
1053 { "SPKOUTRN", NULL, "SPKR Driver" },
1054
39cca168
MB		 1055 { "Left Headphone Mux", "Mixer", "Left Output PGA" },
1056 { "Right Headphone Mux", "Mixer", "Right Output PGA" },
a2342ae3
MB		 1057
1058 { "Headphone PGA", NULL, "Left Headphone Mux" },
1059 { "Headphone PGA", NULL, "Right Headphone Mux" },
4e04adaf 1060 { "Headphone PGA", NULL, "VMID" },
a2342ae3 1061 { "Headphone PGA", NULL, "CLK_SYS" },
3ed7074c 1062 { "Headphone PGA", NULL, "Headphone Supply" },
a2342ae3
MB		 1063
1064 { "HPOUT1L", NULL, "Headphone PGA" },
1065 { "HPOUT1R", NULL, "Headphone PGA" },
1066
4e04adaf
MB		 1067 { "LINEOUT1N Driver", NULL, "VMID" },
1068 { "LINEOUT1P Driver", NULL, "VMID" },
1069 { "LINEOUT2N Driver", NULL, "VMID" },
1070 { "LINEOUT2P Driver", NULL, "VMID" },
1071
a2342ae3
MB		 1072 { "LINEOUT1N", NULL, "LINEOUT1N Driver" },
1073 { "LINEOUT1P", NULL, "LINEOUT1P Driver" },
1074 { "LINEOUT2N", NULL, "LINEOUT2N Driver" },
1075 { "LINEOUT2P", NULL, "LINEOUT2P Driver" },
1076};
1077
1078static const struct snd_soc_dapm_route lineout1_diff_routes[] = {
1079 { "LINEOUT1 Mixer", "IN1L Switch", "IN1L PGA" },
1080 { "LINEOUT1 Mixer", "IN1R Switch", "IN1R PGA" },
d0b48af6 1081 { "LINEOUT1 Mixer", "Output Switch", "Left Output PGA" },
a2342ae3
MB		 1082
1083 { "LINEOUT1N Driver", NULL, "LINEOUT1 Mixer" },
1084 { "LINEOUT1P Driver", NULL, "LINEOUT1 Mixer" },
1085};
1086
1087static const struct snd_soc_dapm_route lineout1_se_routes[] = {
d0b48af6
MB		 1088 { "LINEOUT1N Mixer", "Left Output Switch", "Left Output PGA" },
1089 { "LINEOUT1N Mixer", "Right Output Switch", "Right Output PGA" },
a2342ae3 1090
d0b48af6 1091 { "LINEOUT1P Mixer", "Left Output Switch", "Left Output PGA" },
a2342ae3
MB		 1092
1093 { "LINEOUT1N Driver", NULL, "LINEOUT1N Mixer" },
1094 { "LINEOUT1P Driver", NULL, "LINEOUT1P Mixer" },
1095};
1096
1097static const struct snd_soc_dapm_route lineout2_diff_routes[] = {
ee76744c
MB		 1098 { "LINEOUT2 Mixer", "IN1L Switch", "IN1L PGA" },
1099 { "LINEOUT2 Mixer", "IN1R Switch", "IN1R PGA" },
d0b48af6 1100 { "LINEOUT2 Mixer", "Output Switch", "Right Output PGA" },
a2342ae3
MB		 1101
1102 { "LINEOUT2N Driver", NULL, "LINEOUT2 Mixer" },
1103 { "LINEOUT2P Driver", NULL, "LINEOUT2 Mixer" },
1104};
1105
1106static const struct snd_soc_dapm_route lineout2_se_routes[] = {
d0b48af6
MB		 1107 { "LINEOUT2N Mixer", "Left Output Switch", "Left Output PGA" },
1108 { "LINEOUT2N Mixer", "Right Output Switch", "Right Output PGA" },
a2342ae3 1109
d0b48af6 1110 { "LINEOUT2P Mixer", "Right Output Switch", "Right Output PGA" },
a2342ae3
MB		 1111
1112 { "LINEOUT2N Driver", NULL, "LINEOUT2N Mixer" },
1113 { "LINEOUT2P Driver", NULL, "LINEOUT2P Mixer" },
1114};
1115
1116int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec)
1117{
4a6c2aa1 1118 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
ce6120cc 1119
a2342ae3
MB		 1120 /* Latch volume update bits & default ZC on */
1121 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_1_2_VOLUME,
1122 WM8993_IN1_VU, WM8993_IN1_VU);
1123 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_1_2_VOLUME,
1124 WM8993_IN1_VU, WM8993_IN1_VU);
1125 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_3_4_VOLUME,
1126 WM8993_IN2_VU, WM8993_IN2_VU);
1127 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_3_4_VOLUME,
1128 WM8993_IN2_VU, WM8993_IN2_VU);
1129
fb5af53d
MB		 1130 snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_LEFT,
1131 WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
a2342ae3
MB		 1132 snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_RIGHT,
1133 WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
1134
1135 snd_soc_update_bits(codec, WM8993_LEFT_OUTPUT_VOLUME,
fb5af53d
MB		 1136 WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC,
1137 WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC);
a2342ae3
MB		 1138 snd_soc_update_bits(codec, WM8993_RIGHT_OUTPUT_VOLUME,
1139 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC,
1140 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC);
1141
1142 snd_soc_update_bits(codec, WM8993_LEFT_OPGA_VOLUME,
fb5af53d
MB		 1143 WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU,
1144 WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU);
a2342ae3
MB		 1145 snd_soc_update_bits(codec, WM8993_RIGHT_OPGA_VOLUME,
1146 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU,
1147 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU);
1148
022658be 1149 snd_soc_add_codec_controls(codec, analogue_snd_controls,
a2342ae3
MB		 1150 ARRAY_SIZE(analogue_snd_controls));
1151
ce6120cc 1152 snd_soc_dapm_new_controls(dapm, analogue_dapm_widgets,
a2342ae3
MB		 1153 ARRAY_SIZE(analogue_dapm_widgets));
1154 return 0;
1155}
1156EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_controls);
1157
1158int wm_hubs_add_analogue_routes(struct snd_soc_codec *codec,
1159 int lineout1_diff, int lineout2_diff)
1160{
d96ca3cd 1161 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
4a6c2aa1 1162 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
ce6120cc 1163
8cb8e83b
MB		 1164 hubs->codec = codec;
1165
94aa733a 1166 INIT_LIST_HEAD(&hubs->dcs_cache);
d96ca3cd
MB		 1167 init_completion(&hubs->dcs_done);
1168
ce6120cc 1169 snd_soc_dapm_add_routes(dapm, analogue_routes,
a2342ae3
MB		 1170 ARRAY_SIZE(analogue_routes));
1171
1172 if (lineout1_diff)
ce6120cc 1173 snd_soc_dapm_add_routes(dapm,
a2342ae3
MB		 1174 lineout1_diff_routes,
1175 ARRAY_SIZE(lineout1_diff_routes));
1176 else
ce6120cc 1177 snd_soc_dapm_add_routes(dapm,
a2342ae3
MB		 1178 lineout1_se_routes,
1179 ARRAY_SIZE(lineout1_se_routes));
1180
1181 if (lineout2_diff)
ce6120cc 1182 snd_soc_dapm_add_routes(dapm,
a2342ae3
MB		 1183 lineout2_diff_routes,
1184 ARRAY_SIZE(lineout2_diff_routes));
1185 else
ce6120cc 1186 snd_soc_dapm_add_routes(dapm,
a2342ae3
MB		 1187 lineout2_se_routes,
1188 ARRAY_SIZE(lineout2_se_routes));
1189
1190 return 0;
1191}
1192EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_routes);
1193
aa983d9d
MB		 1194int wm_hubs_handle_analogue_pdata(struct snd_soc_codec *codec,
1195 int lineout1_diff, int lineout2_diff,
1196 int lineout1fb, int lineout2fb,
02e79476
MB		 1197 int jd_scthr, int jd_thr,
1198 int micbias1_delay, int micbias2_delay,
1199 int micbias1_lvl, int micbias2_lvl)
aa983d9d 1200{
5f2f3890
MB		 1201 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
1202
1203 hubs->lineout1_se = !lineout1_diff;
1204 hubs->lineout2_se = !lineout2_diff;
02e79476
MB		 1205 hubs->micb1_delay = micbias1_delay;
1206 hubs->micb2_delay = micbias2_delay;
5f2f3890 1207
aa983d9d
MB		 1208 if (!lineout1_diff)
1209 snd_soc_update_bits(codec, WM8993_LINE_MIXER1,
1210 WM8993_LINEOUT1_MODE,
1211 WM8993_LINEOUT1_MODE);
1212 if (!lineout2_diff)
1213 snd_soc_update_bits(codec, WM8993_LINE_MIXER2,
1214 WM8993_LINEOUT2_MODE,
1215 WM8993_LINEOUT2_MODE);
1216
5472bbc9
MB		 1217 if (!lineout1_diff && !lineout2_diff)
1218 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1219 WM8993_LINEOUT_VMID_BUF_ENA,
1220 WM8993_LINEOUT_VMID_BUF_ENA);
1221
aa983d9d
MB		 1222 if (lineout1fb)
1223 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
1224 WM8993_LINEOUT1_FB, WM8993_LINEOUT1_FB);
1225
1226 if (lineout2fb)
1227 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
1228 WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB);
1229
1230 snd_soc_update_bits(codec, WM8993_MICBIAS,
1231 WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK |
1232 WM8993_MICB1_LVL | WM8993_MICB2_LVL,
1233 jd_scthr << WM8993_JD_SCTHR_SHIFT |
1234 jd_thr << WM8993_JD_THR_SHIFT |
1235 micbias1_lvl |
1236 micbias2_lvl << WM8993_MICB2_LVL_SHIFT);
1237
1238 return 0;
1239}
1240EXPORT_SYMBOL_GPL(wm_hubs_handle_analogue_pdata);
1241
5f2f3890
MB		 1242void wm_hubs_vmid_ena(struct snd_soc_codec *codec)
1243{
1244 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
1245 int val = 0;
1246
1247 if (hubs->lineout1_se)
1248 val |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA;
1249
1250 if (hubs->lineout2_se)
1251 val |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA;
1252
1253 /* Enable the line outputs while we power up */
1254 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_3, val, val);
1255}
1256EXPORT_SYMBOL_GPL(wm_hubs_vmid_ena);
1257
1258void wm_hubs_set_bias_level(struct snd_soc_codec *codec,
1259 enum snd_soc_bias_level level)
1260{
1261 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
de050aca 1262 int mask, val;
5f2f3890
MB		 1263
1264 switch (level) {
d60d6c3b
MB		 1265 case SND_SOC_BIAS_STANDBY:
1266 /* Clamp the inputs to VMID while we ramp to charge caps */
1267 snd_soc_update_bits(codec, WM8993_INPUTS_CLAMP_REG,
1268 WM8993_INPUTS_CLAMP, WM8993_INPUTS_CLAMP);
1269 break;
1270
5f2f3890
MB		 1271 case SND_SOC_BIAS_ON:
1272 /* Turn off any unneded single ended outputs */
1273 val = 0;
de050aca
MB		 1274 mask = 0;
1275
1276 if (hubs->lineout1_se)
1277 mask |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA;
1278
1279 if (hubs->lineout2_se)
1280 mask |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA;
5f2f3890
MB		 1281
1282 if (hubs->lineout1_se && hubs->lineout1n_ena)
1283 val |= WM8993_LINEOUT1N_ENA;
1284
1285 if (hubs->lineout1_se && hubs->lineout1p_ena)
1286 val |= WM8993_LINEOUT1P_ENA;
1287
1288 if (hubs->lineout2_se && hubs->lineout2n_ena)
1289 val |= WM8993_LINEOUT2N_ENA;
1290
1291 if (hubs->lineout2_se && hubs->lineout2p_ena)
1292 val |= WM8993_LINEOUT2P_ENA;
1293
1294 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_3,
de050aca 1295 mask, val);
5f2f3890 1296
d60d6c3b
MB		 1297 /* Remove the input clamps */
1298 snd_soc_update_bits(codec, WM8993_INPUTS_CLAMP_REG,
1299 WM8993_INPUTS_CLAMP, 0);
5f2f3890
MB		 1300 break;
1301
1302 default:
1303 break;
1304 }
1305}
1306EXPORT_SYMBOL_GPL(wm_hubs_set_bias_level);
1307
a2342ae3
MB		 1308MODULE_DESCRIPTION("Shared support for Wolfson hubs products");
1309MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1310MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.325166 seconds and 5 git commands to generate.