Commit | Line | Data |
---|---|---|
310355c1 VB |
1 | /* |
2 | * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor | |
3 | * | |
d6b52039 | 4 | * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> |
310355c1 VB |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/clk.h> | |
18 | ||
19 | #include <sound/core.h> | |
20 | #include <sound/pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/initval.h> | |
23 | #include <sound/soc.h> | |
24 | ||
ff7d04b1 MB |
25 | #include <mach/asp.h> |
26 | ||
310355c1 VB |
27 | #include "davinci-pcm.h" |
28 | ||
a62114cb DB |
29 | |
30 | /* | |
31 | * NOTE: terminology here is confusing. | |
32 | * | |
33 | * - This driver supports the "Audio Serial Port" (ASP), | |
34 | * found on dm6446, dm355, and other DaVinci chips. | |
35 | * | |
36 | * - But it labels it a "Multi-channel Buffered Serial Port" | |
37 | * (McBSP) as on older chips like the dm642 ... which was | |
38 | * backward-compatible, possibly explaining that confusion. | |
39 | * | |
40 | * - OMAP chips have a controller called McBSP, which is | |
41 | * incompatible with the DaVinci flavor of McBSP. | |
42 | * | |
43 | * - Newer DaVinci chips have a controller called McASP, | |
44 | * incompatible with ASP and with either McBSP. | |
45 | * | |
46 | * In short: this uses ASP to implement I2S, not McBSP. | |
47 | * And it won't be the only DaVinci implemention of I2S. | |
48 | */ | |
310355c1 VB |
49 | #define DAVINCI_MCBSP_DRR_REG 0x00 |
50 | #define DAVINCI_MCBSP_DXR_REG 0x04 | |
51 | #define DAVINCI_MCBSP_SPCR_REG 0x08 | |
52 | #define DAVINCI_MCBSP_RCR_REG 0x0c | |
53 | #define DAVINCI_MCBSP_XCR_REG 0x10 | |
54 | #define DAVINCI_MCBSP_SRGR_REG 0x14 | |
55 | #define DAVINCI_MCBSP_PCR_REG 0x24 | |
56 | ||
57 | #define DAVINCI_MCBSP_SPCR_RRST (1 << 0) | |
58 | #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4) | |
59 | #define DAVINCI_MCBSP_SPCR_XRST (1 << 16) | |
60 | #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20) | |
61 | #define DAVINCI_MCBSP_SPCR_GRST (1 << 22) | |
62 | #define DAVINCI_MCBSP_SPCR_FRST (1 << 23) | |
63 | #define DAVINCI_MCBSP_SPCR_FREE (1 << 25) | |
64 | ||
65 | #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5) | |
66 | #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8) | |
67 | #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) | |
f5cfa954 | 68 | #define DAVINCI_MCBSP_RCR_RFIG (1 << 18) |
310355c1 VB |
69 | #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) |
70 | ||
71 | #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) | |
72 | #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) | |
73 | #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) | |
74 | #define DAVINCI_MCBSP_XCR_XFIG (1 << 18) | |
75 | #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) | |
76 | ||
77 | #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) | |
78 | #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) | |
79 | #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) | |
80 | ||
81 | #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) | |
82 | #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) | |
83 | #define DAVINCI_MCBSP_PCR_FSRP (1 << 2) | |
84 | #define DAVINCI_MCBSP_PCR_FSXP (1 << 3) | |
b402dff8 | 85 | #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7) |
310355c1 VB |
86 | #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8) |
87 | #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9) | |
88 | #define DAVINCI_MCBSP_PCR_FSRM (1 << 10) | |
89 | #define DAVINCI_MCBSP_PCR_FSXM (1 << 11) | |
90 | ||
310355c1 VB |
91 | enum { |
92 | DAVINCI_MCBSP_WORD_8 = 0, | |
93 | DAVINCI_MCBSP_WORD_12, | |
94 | DAVINCI_MCBSP_WORD_16, | |
95 | DAVINCI_MCBSP_WORD_20, | |
96 | DAVINCI_MCBSP_WORD_24, | |
97 | DAVINCI_MCBSP_WORD_32, | |
98 | }; | |
99 | ||
310355c1 | 100 | struct davinci_mcbsp_dev { |
92e2a6f6 | 101 | struct davinci_pcm_dma_params dma_params[2]; |
310355c1 | 102 | void __iomem *base; |
f5cfa954 TK |
103 | #define MOD_DSP_A 0 |
104 | #define MOD_DSP_B 1 | |
105 | int mode; | |
c392bec7 | 106 | u32 pcr; |
310355c1 | 107 | struct clk *clk; |
310355c1 VB |
108 | }; |
109 | ||
110 | static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, | |
111 | int reg, u32 val) | |
112 | { | |
113 | __raw_writel(val, dev->base + reg); | |
114 | } | |
115 | ||
116 | static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg) | |
117 | { | |
118 | return __raw_readl(dev->base + reg); | |
119 | } | |
120 | ||
c392bec7 TK |
121 | static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback) |
122 | { | |
123 | u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP; | |
124 | /* The clock needs to toggle to complete reset. | |
125 | * So, fake it by toggling the clk polarity. | |
126 | */ | |
127 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m); | |
128 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr); | |
129 | } | |
130 | ||
f9af37cc TK |
131 | static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev, |
132 | struct snd_pcm_substream *substream) | |
310355c1 VB |
133 | { |
134 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
fb0ef645 | 135 | struct snd_soc_device *socdev = rtd->socdev; |
87689d56 | 136 | struct snd_soc_platform *platform = socdev->card->platform; |
c392bec7 | 137 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
35cf6358 | 138 | u32 spcr; |
c392bec7 | 139 | u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 140 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
c392bec7 TK |
141 | if (spcr & mask) { |
142 | /* start off disabled */ | |
143 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, | |
144 | spcr & ~mask); | |
145 | toggle_clock(dev, playback); | |
146 | } | |
1bef4499 TK |
147 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM | |
148 | DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) { | |
149 | /* Start the sample generator */ | |
150 | spcr |= DAVINCI_MCBSP_SPCR_GRST; | |
151 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
152 | } | |
fb0ef645 | 153 | |
1bef4499 | 154 | if (playback) { |
fb0ef645 NM |
155 | /* Stop the DMA to avoid data loss */ |
156 | /* while the transmitter is out of reset to handle XSYNCERR */ | |
157 | if (platform->pcm_ops->trigger) { | |
eba575c3 | 158 | int ret = platform->pcm_ops->trigger(substream, |
fb0ef645 NM |
159 | SNDRV_PCM_TRIGGER_STOP); |
160 | if (ret < 0) | |
161 | printk(KERN_DEBUG "Playback DMA stop failed\n"); | |
162 | } | |
163 | ||
164 | /* Enable the transmitter */ | |
35cf6358 TK |
165 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
166 | spcr |= DAVINCI_MCBSP_SPCR_XRST; | |
167 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
fb0ef645 NM |
168 | |
169 | /* wait for any unexpected frame sync error to occur */ | |
170 | udelay(100); | |
171 | ||
172 | /* Disable the transmitter to clear any outstanding XSYNCERR */ | |
35cf6358 TK |
173 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
174 | spcr &= ~DAVINCI_MCBSP_SPCR_XRST; | |
175 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
c392bec7 | 176 | toggle_clock(dev, playback); |
fb0ef645 NM |
177 | |
178 | /* Restart the DMA */ | |
179 | if (platform->pcm_ops->trigger) { | |
eba575c3 | 180 | int ret = platform->pcm_ops->trigger(substream, |
fb0ef645 NM |
181 | SNDRV_PCM_TRIGGER_START); |
182 | if (ret < 0) | |
183 | printk(KERN_DEBUG "Playback DMA start failed\n"); | |
184 | } | |
fb0ef645 NM |
185 | } |
186 | ||
1bef4499 | 187 | /* Enable transmitter or receiver */ |
35cf6358 | 188 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
1bef4499 TK |
189 | spcr |= mask; |
190 | ||
191 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) { | |
192 | /* Start frame sync */ | |
193 | spcr |= DAVINCI_MCBSP_SPCR_FRST; | |
194 | } | |
35cf6358 | 195 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
310355c1 VB |
196 | } |
197 | ||
f9af37cc | 198 | static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback) |
310355c1 | 199 | { |
35cf6358 | 200 | u32 spcr; |
310355c1 VB |
201 | |
202 | /* Reset transmitter/receiver and sample rate/frame sync generators */ | |
35cf6358 TK |
203 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
204 | spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST); | |
c392bec7 | 205 | spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 206 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
c392bec7 | 207 | toggle_clock(dev, playback); |
310355c1 VB |
208 | } |
209 | ||
21903c1c TK |
210 | #define DEFAULT_BITPERSAMPLE 16 |
211 | ||
9cb132d7 | 212 | static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
310355c1 VB |
213 | unsigned int fmt) |
214 | { | |
215 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; | |
21903c1c TK |
216 | unsigned int pcr; |
217 | unsigned int srgr; | |
21903c1c TK |
218 | srgr = DAVINCI_MCBSP_SRGR_FSGM | |
219 | DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | | |
220 | DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); | |
310355c1 | 221 | |
f5cfa954 | 222 | /* set master/slave audio interface */ |
310355c1 VB |
223 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
224 | case SND_SOC_DAIFMT_CBS_CFS: | |
21903c1c TK |
225 | /* cpu is master */ |
226 | pcr = DAVINCI_MCBSP_PCR_FSXM | | |
227 | DAVINCI_MCBSP_PCR_FSRM | | |
228 | DAVINCI_MCBSP_PCR_CLKXM | | |
229 | DAVINCI_MCBSP_PCR_CLKRM; | |
310355c1 | 230 | break; |
b402dff8 HV |
231 | case SND_SOC_DAIFMT_CBM_CFS: |
232 | /* McBSP CLKR pin is the input for the Sample Rate Generator. | |
233 | * McBSP FSR and FSX are driven by the Sample Rate Generator. */ | |
21903c1c TK |
234 | pcr = DAVINCI_MCBSP_PCR_SCLKME | |
235 | DAVINCI_MCBSP_PCR_FSXM | | |
236 | DAVINCI_MCBSP_PCR_FSRM; | |
b402dff8 | 237 | break; |
310355c1 | 238 | case SND_SOC_DAIFMT_CBM_CFM: |
21903c1c TK |
239 | /* codec is master */ |
240 | pcr = 0; | |
310355c1 VB |
241 | break; |
242 | default: | |
21903c1c | 243 | printk(KERN_ERR "%s:bad master\n", __func__); |
310355c1 VB |
244 | return -EINVAL; |
245 | } | |
246 | ||
f5cfa954 | 247 | /* interface format */ |
69ab820c | 248 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
69ab820c | 249 | case SND_SOC_DAIFMT_I2S: |
07d8d9dc TK |
250 | /* Davinci doesn't support TRUE I2S, but some codecs will have |
251 | * the left and right channels contiguous. This allows | |
252 | * dsp_a mode to be used with an inverted normal frame clk. | |
253 | * If your codec is master and does not have contiguous | |
254 | * channels, then you will have sound on only one channel. | |
255 | * Try using a different mode, or codec as slave. | |
256 | * | |
257 | * The TLV320AIC33 is an example of a codec where this works. | |
258 | * It has a variable bit clock frequency allowing it to have | |
259 | * valid data on every bit clock. | |
260 | * | |
261 | * The TLV320AIC23 is an example of a codec where this does not | |
262 | * work. It has a fixed bit clock frequency with progressively | |
263 | * more empty bit clock slots between channels as the sample | |
264 | * rate is lowered. | |
265 | */ | |
266 | fmt ^= SND_SOC_DAIFMT_NB_IF; | |
267 | case SND_SOC_DAIFMT_DSP_A: | |
f5cfa954 TK |
268 | dev->mode = MOD_DSP_A; |
269 | break; | |
270 | case SND_SOC_DAIFMT_DSP_B: | |
271 | dev->mode = MOD_DSP_B; | |
69ab820c TK |
272 | break; |
273 | default: | |
274 | printk(KERN_ERR "%s:bad format\n", __func__); | |
275 | return -EINVAL; | |
276 | } | |
277 | ||
310355c1 | 278 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
9e031624 | 279 | case SND_SOC_DAIFMT_NB_NF: |
664b4af8 TK |
280 | /* CLKRP Receive clock polarity, |
281 | * 1 - sampled on rising edge of CLKR | |
282 | * valid on rising edge | |
283 | * CLKXP Transmit clock polarity, | |
284 | * 1 - clocked on falling edge of CLKX | |
285 | * valid on rising edge | |
286 | * FSRP Receive frame sync pol, 0 - active high | |
287 | * FSXP Transmit frame sync pol, 0 - active high | |
288 | */ | |
21903c1c | 289 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP); |
310355c1 | 290 | break; |
9e031624 | 291 | case SND_SOC_DAIFMT_IB_IF: |
664b4af8 TK |
292 | /* CLKRP Receive clock polarity, |
293 | * 0 - sampled on falling edge of CLKR | |
294 | * valid on falling edge | |
295 | * CLKXP Transmit clock polarity, | |
296 | * 0 - clocked on rising edge of CLKX | |
297 | * valid on falling edge | |
298 | * FSRP Receive frame sync pol, 1 - active low | |
299 | * FSXP Transmit frame sync pol, 1 - active low | |
300 | */ | |
21903c1c | 301 | pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); |
310355c1 | 302 | break; |
9e031624 | 303 | case SND_SOC_DAIFMT_NB_IF: |
664b4af8 TK |
304 | /* CLKRP Receive clock polarity, |
305 | * 1 - sampled on rising edge of CLKR | |
306 | * valid on rising edge | |
307 | * CLKXP Transmit clock polarity, | |
308 | * 1 - clocked on falling edge of CLKX | |
309 | * valid on rising edge | |
310 | * FSRP Receive frame sync pol, 1 - active low | |
311 | * FSXP Transmit frame sync pol, 1 - active low | |
312 | */ | |
21903c1c TK |
313 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP | |
314 | DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); | |
310355c1 | 315 | break; |
9e031624 | 316 | case SND_SOC_DAIFMT_IB_NF: |
664b4af8 TK |
317 | /* CLKRP Receive clock polarity, |
318 | * 0 - sampled on falling edge of CLKR | |
319 | * valid on falling edge | |
320 | * CLKXP Transmit clock polarity, | |
321 | * 0 - clocked on rising edge of CLKX | |
322 | * valid on falling edge | |
323 | * FSRP Receive frame sync pol, 0 - active high | |
324 | * FSXP Transmit frame sync pol, 0 - active high | |
325 | */ | |
310355c1 VB |
326 | break; |
327 | default: | |
328 | return -EINVAL; | |
329 | } | |
21903c1c | 330 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); |
c392bec7 | 331 | dev->pcr = pcr; |
21903c1c | 332 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr); |
310355c1 VB |
333 | return 0; |
334 | } | |
335 | ||
336 | static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
337 | struct snd_pcm_hw_params *params, |
338 | struct snd_soc_dai *dai) | |
310355c1 | 339 | { |
9bb74150 | 340 | struct davinci_mcbsp_dev *dev = dai->private_data; |
81ac55aa | 341 | struct davinci_pcm_dma_params *dma_params = |
92e2a6f6 | 342 | &dev->dma_params[substream->stream]; |
310355c1 VB |
343 | struct snd_interval *i = NULL; |
344 | int mcbsp_word_length; | |
35cf6358 TK |
345 | unsigned int rcr, xcr, srgr; |
346 | u32 spcr; | |
310355c1 VB |
347 | |
348 | /* general line settings */ | |
35cf6358 | 349 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
cb6e2063 | 350 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
35cf6358 TK |
351 | spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
352 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 353 | } else { |
35cf6358 TK |
354 | spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
355 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 356 | } |
310355c1 VB |
357 | |
358 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); | |
35cf6358 TK |
359 | srgr = DAVINCI_MCBSP_SRGR_FSGM; |
360 | srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); | |
310355c1 VB |
361 | |
362 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); | |
35cf6358 TK |
363 | srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); |
364 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); | |
310355c1 | 365 | |
f5cfa954 TK |
366 | rcr = DAVINCI_MCBSP_RCR_RFIG; |
367 | xcr = DAVINCI_MCBSP_XCR_XFIG; | |
368 | if (dev->mode == MOD_DSP_B) { | |
369 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0); | |
370 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0); | |
371 | } else { | |
372 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1); | |
373 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1); | |
374 | } | |
310355c1 VB |
375 | /* Determine xfer data type */ |
376 | switch (params_format(params)) { | |
377 | case SNDRV_PCM_FORMAT_S8: | |
378 | dma_params->data_type = 1; | |
379 | mcbsp_word_length = DAVINCI_MCBSP_WORD_8; | |
380 | break; | |
381 | case SNDRV_PCM_FORMAT_S16_LE: | |
382 | dma_params->data_type = 2; | |
383 | mcbsp_word_length = DAVINCI_MCBSP_WORD_16; | |
384 | break; | |
385 | case SNDRV_PCM_FORMAT_S32_LE: | |
386 | dma_params->data_type = 4; | |
387 | mcbsp_word_length = DAVINCI_MCBSP_WORD_32; | |
388 | break; | |
389 | default: | |
9b6e12e4 | 390 | printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n"); |
310355c1 VB |
391 | return -EINVAL; |
392 | } | |
393 | ||
6a99fb5f | 394 | dma_params->acnt = dma_params->data_type; |
4fa9c1a5 C |
395 | dma_params->fifo_level = 0; |
396 | ||
f5cfa954 TK |
397 | rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(1); |
398 | xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(1); | |
310355c1 | 399 | |
f5cfa954 TK |
400 | rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | |
401 | DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); | |
402 | xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) | | |
403 | DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length); | |
310355c1 | 404 | |
f5cfa954 TK |
405 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
406 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); | |
407 | else | |
408 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); | |
310355c1 VB |
409 | return 0; |
410 | } | |
411 | ||
af0adf3e TK |
412 | static int davinci_i2s_prepare(struct snd_pcm_substream *substream, |
413 | struct snd_soc_dai *dai) | |
414 | { | |
9bb74150 | 415 | struct davinci_mcbsp_dev *dev = dai->private_data; |
af0adf3e TK |
416 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
417 | davinci_mcbsp_stop(dev, playback); | |
418 | if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) { | |
419 | /* codec is master */ | |
420 | davinci_mcbsp_start(dev, substream); | |
421 | } | |
422 | return 0; | |
423 | } | |
424 | ||
dee89c4d MB |
425 | static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
426 | struct snd_soc_dai *dai) | |
310355c1 | 427 | { |
9bb74150 | 428 | struct davinci_mcbsp_dev *dev = dai->private_data; |
310355c1 | 429 | int ret = 0; |
f9af37cc | 430 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
af0adf3e TK |
431 | if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) |
432 | return 0; /* return if codec is master */ | |
310355c1 VB |
433 | |
434 | switch (cmd) { | |
435 | case SNDRV_PCM_TRIGGER_START: | |
436 | case SNDRV_PCM_TRIGGER_RESUME: | |
437 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
f9af37cc | 438 | davinci_mcbsp_start(dev, substream); |
310355c1 VB |
439 | break; |
440 | case SNDRV_PCM_TRIGGER_STOP: | |
441 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
442 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
f9af37cc | 443 | davinci_mcbsp_stop(dev, playback); |
310355c1 VB |
444 | break; |
445 | default: | |
446 | ret = -EINVAL; | |
447 | } | |
310355c1 VB |
448 | return ret; |
449 | } | |
450 | ||
af0adf3e TK |
451 | static void davinci_i2s_shutdown(struct snd_pcm_substream *substream, |
452 | struct snd_soc_dai *dai) | |
453 | { | |
9bb74150 | 454 | struct davinci_mcbsp_dev *dev = dai->private_data; |
af0adf3e TK |
455 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
456 | davinci_mcbsp_stop(dev, playback); | |
457 | } | |
458 | ||
5204d496 C |
459 | #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 |
460 | ||
461 | static struct snd_soc_dai_ops davinci_i2s_dai_ops = { | |
3f405b46 MB |
462 | .shutdown = davinci_i2s_shutdown, |
463 | .prepare = davinci_i2s_prepare, | |
5204d496 C |
464 | .trigger = davinci_i2s_trigger, |
465 | .hw_params = davinci_i2s_hw_params, | |
466 | .set_fmt = davinci_i2s_set_dai_fmt, | |
467 | ||
468 | }; | |
469 | ||
470 | struct snd_soc_dai davinci_i2s_dai = { | |
471 | .name = "davinci-i2s", | |
472 | .id = 0, | |
473 | .playback = { | |
474 | .channels_min = 2, | |
475 | .channels_max = 2, | |
476 | .rates = DAVINCI_I2S_RATES, | |
477 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
478 | .capture = { | |
479 | .channels_min = 2, | |
480 | .channels_max = 2, | |
481 | .rates = DAVINCI_I2S_RATES, | |
482 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
483 | .ops = &davinci_i2s_dai_ops, | |
484 | ||
485 | }; | |
486 | EXPORT_SYMBOL_GPL(davinci_i2s_dai); | |
487 | ||
488 | static int davinci_i2s_probe(struct platform_device *pdev) | |
310355c1 | 489 | { |
5204d496 | 490 | struct snd_platform_data *pdata = pdev->dev.platform_data; |
310355c1 | 491 | struct davinci_mcbsp_dev *dev; |
5204d496 | 492 | struct resource *mem, *ioarea, *res; |
310355c1 VB |
493 | int ret; |
494 | ||
495 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
496 | if (!mem) { | |
497 | dev_err(&pdev->dev, "no mem resource?\n"); | |
498 | return -ENODEV; | |
499 | } | |
500 | ||
501 | ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1, | |
502 | pdev->name); | |
503 | if (!ioarea) { | |
504 | dev_err(&pdev->dev, "McBSP region already claimed\n"); | |
505 | return -EBUSY; | |
506 | } | |
507 | ||
508 | dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL); | |
509 | if (!dev) { | |
510 | ret = -ENOMEM; | |
511 | goto err_release_region; | |
512 | } | |
513 | ||
3e46a447 | 514 | dev->clk = clk_get(&pdev->dev, NULL); |
310355c1 VB |
515 | if (IS_ERR(dev->clk)) { |
516 | ret = -ENODEV; | |
517 | goto err_free_mem; | |
518 | } | |
519 | clk_enable(dev->clk); | |
520 | ||
521 | dev->base = (void __iomem *)IO_ADDRESS(mem->start); | |
310355c1 | 522 | |
92e2a6f6 | 523 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr = |
310355c1 VB |
524 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG); |
525 | ||
92e2a6f6 | 526 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr = |
310355c1 VB |
527 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG); |
528 | ||
5204d496 C |
529 | /* first TX, then RX */ |
530 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
531 | if (!res) { | |
532 | dev_err(&pdev->dev, "no DMA resource\n"); | |
efd13be0 | 533 | ret = -ENXIO; |
5204d496 C |
534 | goto err_free_mem; |
535 | } | |
92e2a6f6 | 536 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start; |
5204d496 C |
537 | |
538 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
539 | if (!res) { | |
540 | dev_err(&pdev->dev, "no DMA resource\n"); | |
efd13be0 | 541 | ret = -ENXIO; |
5204d496 C |
542 | goto err_free_mem; |
543 | } | |
92e2a6f6 | 544 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start; |
5204d496 C |
545 | |
546 | davinci_i2s_dai.private_data = dev; | |
57512c64 | 547 | davinci_i2s_dai.dma_data = dev->dma_params; |
5204d496 C |
548 | ret = snd_soc_register_dai(&davinci_i2s_dai); |
549 | if (ret != 0) | |
550 | goto err_free_mem; | |
551 | ||
310355c1 VB |
552 | return 0; |
553 | ||
554 | err_free_mem: | |
555 | kfree(dev); | |
556 | err_release_region: | |
557 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
558 | ||
559 | return ret; | |
560 | } | |
561 | ||
5204d496 | 562 | static int davinci_i2s_remove(struct platform_device *pdev) |
310355c1 | 563 | { |
5204d496 | 564 | struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data; |
310355c1 VB |
565 | struct resource *mem; |
566 | ||
5204d496 | 567 | snd_soc_unregister_dai(&davinci_i2s_dai); |
310355c1 VB |
568 | clk_disable(dev->clk); |
569 | clk_put(dev->clk); | |
570 | dev->clk = NULL; | |
310355c1 | 571 | kfree(dev); |
310355c1 VB |
572 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
573 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
310355c1 | 574 | |
5204d496 C |
575 | return 0; |
576 | } | |
6335d055 | 577 | |
5204d496 C |
578 | static struct platform_driver davinci_mcbsp_driver = { |
579 | .probe = davinci_i2s_probe, | |
580 | .remove = davinci_i2s_remove, | |
581 | .driver = { | |
582 | .name = "davinci-asp", | |
583 | .owner = THIS_MODULE, | |
584 | }, | |
310355c1 | 585 | }; |
310355c1 | 586 | |
c9b3a40f | 587 | static int __init davinci_i2s_init(void) |
3f4b783c | 588 | { |
5204d496 | 589 | return platform_driver_register(&davinci_mcbsp_driver); |
3f4b783c MB |
590 | } |
591 | module_init(davinci_i2s_init); | |
592 | ||
593 | static void __exit davinci_i2s_exit(void) | |
594 | { | |
5204d496 | 595 | platform_driver_unregister(&davinci_mcbsp_driver); |
3f4b783c MB |
596 | } |
597 | module_exit(davinci_i2s_exit); | |
598 | ||
310355c1 VB |
599 | MODULE_AUTHOR("Vladimir Barinov"); |
600 | MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface"); | |
601 | MODULE_LICENSE("GPL"); |