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ASoC: Constify snd_soc_dai_ops structs
[deliverable/linux.git] / sound / soc / davinci / davinci-i2s.c
CommitLineData
310355c1
VB		 1/*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
310355c1
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/device.h>
5a0e3ad6 15#include <linux/slab.h>
310355c1
VB		 16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/initval.h>
24#include <sound/soc.h>
25
ff7d04b1
MB		 26#include <mach/asp.h>
27
310355c1 28#include "davinci-pcm.h"
a4c8ea2d 29#include "davinci-i2s.h"
310355c1 30
a62114cb
DB		 31
32/*
33 * NOTE: terminology here is confusing.
34 *
35 * - This driver supports the "Audio Serial Port" (ASP),
36 * found on dm6446, dm355, and other DaVinci chips.
37 *
38 * - But it labels it a "Multi-channel Buffered Serial Port"
39 * (McBSP) as on older chips like the dm642 ... which was
40 * backward-compatible, possibly explaining that confusion.
41 *
42 * - OMAP chips have a controller called McBSP, which is
43 * incompatible with the DaVinci flavor of McBSP.
44 *
45 * - Newer DaVinci chips have a controller called McASP,
46 * incompatible with ASP and with either McBSP.
47 *
48 * In short: this uses ASP to implement I2S, not McBSP.
49 * And it won't be the only DaVinci implemention of I2S.
50 */
310355c1
VB		 51#define DAVINCI_MCBSP_DRR_REG 0x00
52#define DAVINCI_MCBSP_DXR_REG 0x04
53#define DAVINCI_MCBSP_SPCR_REG 0x08
54#define DAVINCI_MCBSP_RCR_REG 0x0c
55#define DAVINCI_MCBSP_XCR_REG 0x10
56#define DAVINCI_MCBSP_SRGR_REG 0x14
57#define DAVINCI_MCBSP_PCR_REG 0x24
58
59#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
60#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
61#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
62#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
63#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
64#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
65#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
66
67#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
68#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
69#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
f5cfa954 70#define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
310355c1 71#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
a4c8ea2d
RR		 72#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
73#define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
310355c1
VB		 74
75#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
76#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
77#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
78#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
79#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
a4c8ea2d
RR		 80#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
81#define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
310355c1
VB		 82
83#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
84#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
85#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
a4c8ea2d 86#define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
310355c1
VB		 87
88#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
89#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
90#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
91#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
b402dff8 92#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
310355c1
VB		 93#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
94#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
95#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
96#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
97
310355c1
VB		 98enum {
99 DAVINCI_MCBSP_WORD_8 = 0,
100 DAVINCI_MCBSP_WORD_12,
101 DAVINCI_MCBSP_WORD_16,
102 DAVINCI_MCBSP_WORD_20,
103 DAVINCI_MCBSP_WORD_24,
104 DAVINCI_MCBSP_WORD_32,
105};
106
0d6c9774
TK		 107static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
108 [SNDRV_PCM_FORMAT_S8] = 1,
109 [SNDRV_PCM_FORMAT_S16_LE] = 2,
110 [SNDRV_PCM_FORMAT_S32_LE] = 4,
111};
112
113static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
114 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
115 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
116 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
117};
118
119static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
120 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
121 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
122};
123
310355c1 124struct davinci_mcbsp_dev {
ec637553 125 struct device *dev;
92e2a6f6 126 struct davinci_pcm_dma_params dma_params[2];
310355c1 127 void __iomem *base;
f5cfa954
TK		 128#define MOD_DSP_A 0
129#define MOD_DSP_B 1
130 int mode;
c392bec7 131 u32 pcr;
310355c1 132 struct clk *clk;
0d6c9774
TK		 133 /*
134 * Combining both channels into 1 element will at least double the
135 * amount of time between servicing the dma channel, increase
136 * effiency, and reduce the chance of overrun/underrun. But,
137 * it will result in the left & right channels being swapped.
138 *
139 * If relabeling the left and right channels is not possible,
140 * you may want to let the codec know to swap them back.
141 *
142 * It may allow x10 the amount of time to service dma requests,
143 * if the codec is master and is using an unnecessarily fast bit clock
144 * (ie. tlvaic23b), independent of the sample rate. So, having an
145 * entire frame at once means it can be serviced at the sample rate
146 * instead of the bit clock rate.
147 *
148 * In the now unlikely case that an underrun still
149 * occurs, both the left and right samples will be repeated
150 * so that no pops are heard, and the left and right channels
151 * won't end up being swapped because of the underrun.
152 */
153 unsigned enable_channel_combine:1;
a4c8ea2d
RR		 154
155 unsigned int fmt;
156 int clk_div;
ec637553 157 int clk_input_pin;
d9823ed9 158 bool i2s_accurate_sck;
310355c1
VB		 159};
160
161static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
162 int reg, u32 val)
163{
164 __raw_writel(val, dev->base + reg);
165}
166
167static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
168{
169 return __raw_readl(dev->base + reg);
170}
171
c392bec7
TK		 172static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
173{
174 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
175 /* The clock needs to toggle to complete reset.
176 * So, fake it by toggling the clk polarity.
177 */
178 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
179 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
180}
181
f9af37cc
TK		 182static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
183 struct snd_pcm_substream *substream)
310355c1
VB		 184{
185 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 186 struct snd_soc_platform *platform = rtd->platform;
c392bec7 187 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
35cf6358 188 u32 spcr;
c392bec7 189 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
35cf6358 190 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
c392bec7
TK		 191 if (spcr & mask) {
192 /* start off disabled */
193 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
194 spcr & ~mask);
195 toggle_clock(dev, playback);
196 }
1bef4499
TK		 197 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
198 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
199 /* Start the sample generator */
200 spcr |= DAVINCI_MCBSP_SPCR_GRST;
201 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
202 }
fb0ef645 203
1bef4499 204 if (playback) {
fb0ef645
NM		 205 /* Stop the DMA to avoid data loss */
206 /* while the transmitter is out of reset to handle XSYNCERR */
f0fba2ad
LG		 207 if (platform->driver->ops->trigger) {
208 int ret = platform->driver->ops->trigger(substream,
fb0ef645
NM		 209 SNDRV_PCM_TRIGGER_STOP);
210 if (ret < 0)
211 printk(KERN_DEBUG "Playback DMA stop failed\n");
212 }
213
214 /* Enable the transmitter */
35cf6358
TK		 215 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
216 spcr |= DAVINCI_MCBSP_SPCR_XRST;
217 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
fb0ef645
NM		 218
219 /* wait for any unexpected frame sync error to occur */
220 udelay(100);
221
222 /* Disable the transmitter to clear any outstanding XSYNCERR */
35cf6358
TK		 223 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
224 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
225 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
c392bec7 226 toggle_clock(dev, playback);
fb0ef645
NM		 227
228 /* Restart the DMA */
f0fba2ad
LG		 229 if (platform->driver->ops->trigger) {
230 int ret = platform->driver->ops->trigger(substream,
fb0ef645
NM		 231 SNDRV_PCM_TRIGGER_START);
232 if (ret < 0)
233 printk(KERN_DEBUG "Playback DMA start failed\n");
234 }
fb0ef645
NM		 235 }
236
1bef4499 237 /* Enable transmitter or receiver */
35cf6358 238 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
1bef4499
TK		 239 spcr |= mask;
240
241 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
242 /* Start frame sync */
243 spcr |= DAVINCI_MCBSP_SPCR_FRST;
244 }
35cf6358 245 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
310355c1
VB		 246}
247
f9af37cc 248static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
310355c1 249{
35cf6358 250 u32 spcr;
310355c1
VB		 251
252 /* Reset transmitter/receiver and sample rate/frame sync generators */
35cf6358
TK		 253 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
254 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
c392bec7 255 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
35cf6358 256 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
c392bec7 257 toggle_clock(dev, playback);
310355c1
VB		 258}
259
21903c1c
TK		 260#define DEFAULT_BITPERSAMPLE 16
261
9cb132d7 262static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
310355c1
VB		 263 unsigned int fmt)
264{
f0fba2ad 265 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
21903c1c
TK		 266 unsigned int pcr;
267 unsigned int srgr;
ad51f765 268 bool inv_fs = false;
a4c8ea2d 269 /* Attention srgr is updated by hw_params! */
21903c1c
TK		 270 srgr = DAVINCI_MCBSP_SRGR_FSGM |
271 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
272 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
310355c1 273
a4c8ea2d 274 dev->fmt = fmt;
f5cfa954 275 /* set master/slave audio interface */
310355c1
VB		 276 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
277 case SND_SOC_DAIFMT_CBS_CFS:
21903c1c
TK		 278 /* cpu is master */
279 pcr = DAVINCI_MCBSP_PCR_FSXM |
280 DAVINCI_MCBSP_PCR_FSRM |
281 DAVINCI_MCBSP_PCR_CLKXM |
282 DAVINCI_MCBSP_PCR_CLKRM;
310355c1 283 break;
b402dff8 284 case SND_SOC_DAIFMT_CBM_CFS:
ec637553
RR		 285 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
286 /*
287 * Selection of the clock input pin that is the
288 * input for the Sample Rate Generator.
289 * McBSP FSR and FSX are driven by the Sample Rate
290 * Generator.
291 */
292 switch (dev->clk_input_pin) {
293 case MCBSP_CLKS:
294 pcr |= DAVINCI_MCBSP_PCR_CLKXM |
295 DAVINCI_MCBSP_PCR_CLKRM;
296 break;
297 case MCBSP_CLKR:
298 pcr |= DAVINCI_MCBSP_PCR_SCLKME;
299 break;
300 default:
301 dev_err(dev->dev, "bad clk_input_pin\n");
302 return -EINVAL;
303 }
304
b402dff8 305 break;
310355c1 306 case SND_SOC_DAIFMT_CBM_CFM:
21903c1c
TK		 307 /* codec is master */
308 pcr = 0;
310355c1
VB		 309 break;
310 default:
21903c1c 311 printk(KERN_ERR "%s:bad master\n", __func__);
310355c1
VB		 312 return -EINVAL;
313 }
314
f5cfa954 315 /* interface format */
69ab820c 316 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
69ab820c 317 case SND_SOC_DAIFMT_I2S:
07d8d9dc
TK		 318 /* Davinci doesn't support TRUE I2S, but some codecs will have
319 * the left and right channels contiguous. This allows
320 * dsp_a mode to be used with an inverted normal frame clk.
321 * If your codec is master and does not have contiguous
322 * channels, then you will have sound on only one channel.
323 * Try using a different mode, or codec as slave.
324 *
325 * The TLV320AIC33 is an example of a codec where this works.
326 * It has a variable bit clock frequency allowing it to have
327 * valid data on every bit clock.
328 *
329 * The TLV320AIC23 is an example of a codec where this does not
330 * work. It has a fixed bit clock frequency with progressively
331 * more empty bit clock slots between channels as the sample
332 * rate is lowered.
333 */
ad51f765 334 inv_fs = true;
07d8d9dc 335 case SND_SOC_DAIFMT_DSP_A:
f5cfa954
TK		 336 dev->mode = MOD_DSP_A;
337 break;
338 case SND_SOC_DAIFMT_DSP_B:
339 dev->mode = MOD_DSP_B;
69ab820c
TK		 340 break;
341 default:
342 printk(KERN_ERR "%s:bad format\n", __func__);
343 return -EINVAL;
344 }
345
310355c1 346 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
9e031624 347 case SND_SOC_DAIFMT_NB_NF:
664b4af8
TK		 348 /* CLKRP Receive clock polarity,
349 * 1 - sampled on rising edge of CLKR
350 * valid on rising edge
351 * CLKXP Transmit clock polarity,
352 * 1 - clocked on falling edge of CLKX
353 * valid on rising edge
354 * FSRP Receive frame sync pol, 0 - active high
355 * FSXP Transmit frame sync pol, 0 - active high
356 */
21903c1c 357 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
310355c1 358 break;
9e031624 359 case SND_SOC_DAIFMT_IB_IF:
664b4af8
TK		 360 /* CLKRP Receive clock polarity,
361 * 0 - sampled on falling edge of CLKR
362 * valid on falling edge
363 * CLKXP Transmit clock polarity,
364 * 0 - clocked on rising edge of CLKX
365 * valid on falling edge
366 * FSRP Receive frame sync pol, 1 - active low
367 * FSXP Transmit frame sync pol, 1 - active low
368 */
21903c1c 369 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
310355c1 370 break;
9e031624 371 case SND_SOC_DAIFMT_NB_IF:
664b4af8
TK		 372 /* CLKRP Receive clock polarity,
373 * 1 - sampled on rising edge of CLKR
374 * valid on rising edge
375 * CLKXP Transmit clock polarity,
376 * 1 - clocked on falling edge of CLKX
377 * valid on rising edge
378 * FSRP Receive frame sync pol, 1 - active low
379 * FSXP Transmit frame sync pol, 1 - active low
380 */
21903c1c
TK		 381 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
382 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
310355c1 383 break;
9e031624 384 case SND_SOC_DAIFMT_IB_NF:
664b4af8
TK		 385 /* CLKRP Receive clock polarity,
386 * 0 - sampled on falling edge of CLKR
387 * valid on falling edge
388 * CLKXP Transmit clock polarity,
389 * 0 - clocked on rising edge of CLKX
390 * valid on falling edge
391 * FSRP Receive frame sync pol, 0 - active high
392 * FSXP Transmit frame sync pol, 0 - active high
393 */
310355c1
VB		 394 break;
395 default:
396 return -EINVAL;
397 }
ad51f765
JN		 398 if (inv_fs == true)
399 pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
21903c1c 400 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
c392bec7 401 dev->pcr = pcr;
21903c1c 402 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
310355c1
VB		 403 return 0;
404}
405
a4c8ea2d
RR		 406static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
407 int div_id, int div)
408{
f0fba2ad 409 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
a4c8ea2d
RR		 410
411 if (div_id != DAVINCI_MCBSP_CLKGDV)
412 return -ENODEV;
413
414 dev->clk_div = div;
415 return 0;
416}
417
310355c1 418static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 419 struct snd_pcm_hw_params *params,
420 struct snd_soc_dai *dai)
310355c1 421{
f0fba2ad 422 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
81ac55aa 423 struct davinci_pcm_dma_params *dma_params =
92e2a6f6 424 &dev->dma_params[substream->stream];
310355c1 425 struct snd_interval *i = NULL;
a4c8ea2d
RR		 426 int mcbsp_word_length, master;
427 unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
35cf6358 428 u32 spcr;
0d6c9774
TK		 429 snd_pcm_format_t fmt;
430 unsigned element_cnt = 1;
310355c1
VB		 431
432 /* general line settings */
35cf6358 433 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
cb6e2063 434 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
35cf6358
TK		 435 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
436 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
cb6e2063 437 } else {
35cf6358
TK		 438 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
439 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
cb6e2063 440 }
310355c1 441
a4c8ea2d
RR		 442 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
443 fmt = params_format(params);
444 mcbsp_word_length = asp_word_length[fmt];
310355c1 445
a4c8ea2d
RR		 446 switch (master) {
447 case SND_SOC_DAIFMT_CBS_CFS:
448 freq = clk_get_rate(dev->clk);
449 srgr = DAVINCI_MCBSP_SRGR_FSGM |
450 DAVINCI_MCBSP_SRGR_CLKSM;
451 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
452 8 - 1);
d9823ed9
RR		 453 if (dev->i2s_accurate_sck) {
454 clk_div = 256;
455 do {
456 framesize = (freq / (--clk_div)) /
457 params->rate_num *
458 params->rate_den;
459 } while (((framesize < 33) || (framesize > 4095)) &&
460 (clk_div));
461 clk_div--;
462 srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
463 } else {
464 /* symmetric waveforms */
465 clk_div = freq / (mcbsp_word_length * 16) /
466 params->rate_num * params->rate_den;
467 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
468 16 - 1);
469 }
a4c8ea2d
RR		 470 clk_div &= 0xFF;
471 srgr |= clk_div;
472 break;
473 case SND_SOC_DAIFMT_CBM_CFS:
474 srgr = DAVINCI_MCBSP_SRGR_FSGM;
475 clk_div = dev->clk_div - 1;
476 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
477 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
478 clk_div &= 0xFF;
479 srgr |= clk_div;
480 break;
481 case SND_SOC_DAIFMT_CBM_CFM:
482 /* Clock and frame sync given from external sources */
483 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
484 srgr = DAVINCI_MCBSP_SRGR_FSGM;
485 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
486 pr_debug("%s - %d FWID set: re-read srgr = %X\n",
487 __func__, __LINE__, snd_interval_value(i) - 1);
488
489 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
490 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
491 break;
492 default:
493 return -EINVAL;
494 }
35cf6358 495 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
310355c1 496
f5cfa954
TK		 497 rcr = DAVINCI_MCBSP_RCR_RFIG;
498 xcr = DAVINCI_MCBSP_XCR_XFIG;
499 if (dev->mode == MOD_DSP_B) {
500 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
501 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
502 } else {
503 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
504 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
505 }
310355c1 506 /* Determine xfer data type */
0d6c9774
TK		 507 fmt = params_format(params);
508 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
9b6e12e4 509 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
310355c1
VB		 510 return -EINVAL;
511 }
512
0d6c9774
TK		 513 if (params_channels(params) == 2) {
514 element_cnt = 2;
515 if (double_fmt[fmt] && dev->enable_channel_combine) {
516 element_cnt = 1;
517 fmt = double_fmt[fmt];
518 }
a4c8ea2d
RR		 519 switch (master) {
520 case SND_SOC_DAIFMT_CBS_CFS:
521 case SND_SOC_DAIFMT_CBS_CFM:
522 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
523 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
524 rcr |= DAVINCI_MCBSP_RCR_RPHASE;
525 xcr |= DAVINCI_MCBSP_XCR_XPHASE;
526 break;
527 case SND_SOC_DAIFMT_CBM_CFM:
528 case SND_SOC_DAIFMT_CBM_CFS:
529 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
530 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
531 break;
532 default:
533 return -EINVAL;
534 }
0d6c9774
TK		 535 }
536 dma_params->acnt = dma_params->data_type = data_type[fmt];
4fa9c1a5 537 dma_params->fifo_level = 0;
0d6c9774 538 mcbsp_word_length = asp_word_length[fmt];
a4c8ea2d
RR		 539
540 switch (master) {
541 case SND_SOC_DAIFMT_CBS_CFS:
542 case SND_SOC_DAIFMT_CBS_CFM:
543 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
544 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
545 break;
546 case SND_SOC_DAIFMT_CBM_CFM:
547 case SND_SOC_DAIFMT_CBM_CFS:
548 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
549 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
550 break;
551 default:
552 return -EINVAL;
553 }
310355c1 554
f5cfa954
TK		 555 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
556 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
557 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
558 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
310355c1 559
f5cfa954
TK		 560 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
561 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
562 else
563 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
a4c8ea2d
RR		 564
565 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
566 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
567 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
310355c1
VB		 568 return 0;
569}
570
af0adf3e
TK		 571static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
572 struct snd_soc_dai *dai)
573{
f0fba2ad 574 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
af0adf3e
TK		 575 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
576 davinci_mcbsp_stop(dev, playback);
af0adf3e
TK		 577 return 0;
578}
579
dee89c4d
MB		 580static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
581 struct snd_soc_dai *dai)
310355c1 582{
f0fba2ad 583 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
310355c1 584 int ret = 0;
f9af37cc 585 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
310355c1
VB		 586
587 switch (cmd) {
588 case SNDRV_PCM_TRIGGER_START:
589 case SNDRV_PCM_TRIGGER_RESUME:
590 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
f9af37cc 591 davinci_mcbsp_start(dev, substream);
310355c1
VB		 592 break;
593 case SNDRV_PCM_TRIGGER_STOP:
594 case SNDRV_PCM_TRIGGER_SUSPEND:
595 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
f9af37cc 596 davinci_mcbsp_stop(dev, playback);
310355c1
VB		 597 break;
598 default:
599 ret = -EINVAL;
600 }
310355c1
VB		 601 return ret;
602}
603
bedad0ca
CPE		 604static int davinci_i2s_startup(struct snd_pcm_substream *substream,
605 struct snd_soc_dai *dai)
606{
607 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
608
609 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
610 return 0;
611}
612
af0adf3e
TK		 613static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
614 struct snd_soc_dai *dai)
615{
f0fba2ad 616 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
af0adf3e
TK		 617 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
618 davinci_mcbsp_stop(dev, playback);
619}
620
5204d496
C		 621#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
622
85e7652d 623static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
bedad0ca 624 .startup = davinci_i2s_startup,
3f405b46
MB		 625 .shutdown = davinci_i2s_shutdown,
626 .prepare = davinci_i2s_prepare,
5204d496
C		 627 .trigger = davinci_i2s_trigger,
628 .hw_params = davinci_i2s_hw_params,
629 .set_fmt = davinci_i2s_set_dai_fmt,
a4c8ea2d 630 .set_clkdiv = davinci_i2s_dai_set_clkdiv,
5204d496
C		 631
632};
633
f0fba2ad 634static struct snd_soc_dai_driver davinci_i2s_dai = {
5204d496
C		 635 .playback = {
636 .channels_min = 2,
637 .channels_max = 2,
638 .rates = DAVINCI_I2S_RATES,
639 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
640 .capture = {
641 .channels_min = 2,
642 .channels_max = 2,
643 .rates = DAVINCI_I2S_RATES,
644 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
645 .ops = &davinci_i2s_dai_ops,
646
647};
5204d496
C		 648
649static int davinci_i2s_probe(struct platform_device *pdev)
310355c1 650{
5204d496 651 struct snd_platform_data *pdata = pdev->dev.platform_data;
310355c1 652 struct davinci_mcbsp_dev *dev;
5204d496 653 struct resource *mem, *ioarea, *res;
48519f0a
SN		 654 enum dma_event_q asp_chan_q = EVENTQ_0;
655 enum dma_event_q ram_chan_q = EVENTQ_1;
310355c1
VB		 656 int ret;
657
658 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
659 if (!mem) {
660 dev_err(&pdev->dev, "no mem resource?\n");
661 return -ENODEV;
662 }
663
d852f446 664 ioarea = request_mem_region(mem->start, resource_size(mem),
310355c1
VB		 665 pdev->name);
666 if (!ioarea) {
667 dev_err(&pdev->dev, "McBSP region already claimed\n");
668 return -EBUSY;
669 }
670
671 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
672 if (!dev) {
673 ret = -ENOMEM;
674 goto err_release_region;
675 }
1e224f32 676 if (pdata) {
0d6c9774 677 dev->enable_channel_combine = pdata->enable_channel_combine;
1e224f32
TK		 678 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
679 pdata->sram_size_playback;
680 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
681 pdata->sram_size_capture;
ec637553 682 dev->clk_input_pin = pdata->clk_input_pin;
d9823ed9 683 dev->i2s_accurate_sck = pdata->i2s_accurate_sck;
48519f0a
SN		 684 asp_chan_q = pdata->asp_chan_q;
685 ram_chan_q = pdata->ram_chan_q;
1e224f32 686 }
48519f0a
SN		 687
688 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].asp_chan_q = asp_chan_q;
689 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].ram_chan_q = ram_chan_q;
690 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].asp_chan_q = asp_chan_q;
691 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].ram_chan_q = ram_chan_q;
692
3e46a447 693 dev->clk = clk_get(&pdev->dev, NULL);
310355c1
VB		 694 if (IS_ERR(dev->clk)) {
695 ret = -ENODEV;
696 goto err_free_mem;
697 }
698 clk_enable(dev->clk);
699
4f82f028
VB		 700 dev->base = ioremap(mem->start, resource_size(mem));
701 if (!dev->base) {
702 dev_err(&pdev->dev, "ioremap failed\n");
703 ret = -ENOMEM;
704 goto err_release_clk;
705 }
310355c1 706
92e2a6f6 707 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr =
4f82f028 708 (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
310355c1 709
92e2a6f6 710 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr =
4f82f028 711 (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
310355c1 712
5204d496
C		 713 /* first TX, then RX */
714 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
715 if (!res) {
716 dev_err(&pdev->dev, "no DMA resource\n");
efd13be0 717 ret = -ENXIO;
4f82f028 718 goto err_iounmap;
5204d496 719 }
92e2a6f6 720 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start;
5204d496
C		 721
722 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
723 if (!res) {
724 dev_err(&pdev->dev, "no DMA resource\n");
efd13be0 725 ret = -ENXIO;
4f82f028 726 goto err_iounmap;
5204d496 727 }
92e2a6f6 728 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start;
ec637553 729 dev->dev = &pdev->dev;
5204d496 730
f0fba2ad
LG		 731 dev_set_drvdata(&pdev->dev, dev);
732
733 ret = snd_soc_register_dai(&pdev->dev, &davinci_i2s_dai);
5204d496 734 if (ret != 0)
4f82f028 735 goto err_iounmap;
5204d496 736
310355c1
VB		 737 return 0;
738
4f82f028
VB		 739err_iounmap:
740 iounmap(dev->base);
eef6d7b8
VB		 741err_release_clk:
742 clk_disable(dev->clk);
743 clk_put(dev->clk);
310355c1
VB		 744err_free_mem:
745 kfree(dev);
746err_release_region:
d852f446 747 release_mem_region(mem->start, resource_size(mem));
310355c1
VB		 748
749 return ret;
750}
751
5204d496 752static int davinci_i2s_remove(struct platform_device *pdev)
310355c1 753{
f0fba2ad 754 struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
310355c1
VB		 755 struct resource *mem;
756
f0fba2ad 757 snd_soc_unregister_dai(&pdev->dev);
310355c1
VB		 758 clk_disable(dev->clk);
759 clk_put(dev->clk);
760 dev->clk = NULL;
310355c1 761 kfree(dev);
310355c1 762 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d852f446 763 release_mem_region(mem->start, resource_size(mem));
310355c1 764
5204d496
C		 765 return 0;
766}
6335d055 767
5204d496
C		 768static struct platform_driver davinci_mcbsp_driver = {
769 .probe = davinci_i2s_probe,
770 .remove = davinci_i2s_remove,
771 .driver = {
bedad0ca 772 .name = "davinci-mcbsp",
5204d496
C		 773 .owner = THIS_MODULE,
774 },
310355c1 775};
310355c1 776
c9b3a40f 777static int __init davinci_i2s_init(void)
3f4b783c 778{
5204d496 779 return platform_driver_register(&davinci_mcbsp_driver);
3f4b783c
MB		 780}
781module_init(davinci_i2s_init);
782
783static void __exit davinci_i2s_exit(void)
784{
5204d496 785 platform_driver_unregister(&davinci_mcbsp_driver);
3f4b783c
MB		 786}
787module_exit(davinci_i2s_exit);
788
310355c1
VB		 789MODULE_AUTHOR("Vladimir Barinov");
790MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
791MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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