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310355c1 VB |
1 | /* |
2 | * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor | |
3 | * | |
d6b52039 | 4 | * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> |
310355c1 VB |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/clk.h> | |
18 | ||
19 | #include <sound/core.h> | |
20 | #include <sound/pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/initval.h> | |
23 | #include <sound/soc.h> | |
24 | ||
25 | #include "davinci-pcm.h" | |
26 | ||
27 | #define DAVINCI_MCBSP_DRR_REG 0x00 | |
28 | #define DAVINCI_MCBSP_DXR_REG 0x04 | |
29 | #define DAVINCI_MCBSP_SPCR_REG 0x08 | |
30 | #define DAVINCI_MCBSP_RCR_REG 0x0c | |
31 | #define DAVINCI_MCBSP_XCR_REG 0x10 | |
32 | #define DAVINCI_MCBSP_SRGR_REG 0x14 | |
33 | #define DAVINCI_MCBSP_PCR_REG 0x24 | |
34 | ||
35 | #define DAVINCI_MCBSP_SPCR_RRST (1 << 0) | |
36 | #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4) | |
37 | #define DAVINCI_MCBSP_SPCR_XRST (1 << 16) | |
38 | #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20) | |
39 | #define DAVINCI_MCBSP_SPCR_GRST (1 << 22) | |
40 | #define DAVINCI_MCBSP_SPCR_FRST (1 << 23) | |
41 | #define DAVINCI_MCBSP_SPCR_FREE (1 << 25) | |
42 | ||
43 | #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5) | |
44 | #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8) | |
45 | #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) | |
46 | #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) | |
47 | ||
48 | #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) | |
49 | #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) | |
50 | #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) | |
51 | #define DAVINCI_MCBSP_XCR_XFIG (1 << 18) | |
52 | #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) | |
53 | ||
54 | #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) | |
55 | #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) | |
56 | #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) | |
57 | ||
58 | #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) | |
59 | #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) | |
60 | #define DAVINCI_MCBSP_PCR_FSRP (1 << 2) | |
61 | #define DAVINCI_MCBSP_PCR_FSXP (1 << 3) | |
b402dff8 | 62 | #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7) |
310355c1 VB |
63 | #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8) |
64 | #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9) | |
65 | #define DAVINCI_MCBSP_PCR_FSRM (1 << 10) | |
66 | #define DAVINCI_MCBSP_PCR_FSXM (1 << 11) | |
67 | ||
68 | #define MOD_REG_BIT(val, mask, set) do { \ | |
69 | if (set) { \ | |
70 | val |= mask; \ | |
71 | } else { \ | |
72 | val &= ~mask; \ | |
73 | } \ | |
74 | } while (0) | |
75 | ||
76 | enum { | |
77 | DAVINCI_MCBSP_WORD_8 = 0, | |
78 | DAVINCI_MCBSP_WORD_12, | |
79 | DAVINCI_MCBSP_WORD_16, | |
80 | DAVINCI_MCBSP_WORD_20, | |
81 | DAVINCI_MCBSP_WORD_24, | |
82 | DAVINCI_MCBSP_WORD_32, | |
83 | }; | |
84 | ||
85 | static struct davinci_pcm_dma_params davinci_i2s_pcm_out = { | |
86 | .name = "I2S PCM Stereo out", | |
87 | }; | |
88 | ||
89 | static struct davinci_pcm_dma_params davinci_i2s_pcm_in = { | |
90 | .name = "I2S PCM Stereo in", | |
91 | }; | |
92 | ||
93 | struct davinci_mcbsp_dev { | |
94 | void __iomem *base; | |
95 | struct clk *clk; | |
96 | struct davinci_pcm_dma_params *dma_params[2]; | |
97 | }; | |
98 | ||
99 | static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, | |
100 | int reg, u32 val) | |
101 | { | |
102 | __raw_writel(val, dev->base + reg); | |
103 | } | |
104 | ||
105 | static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg) | |
106 | { | |
107 | return __raw_readl(dev->base + reg); | |
108 | } | |
109 | ||
110 | static void davinci_mcbsp_start(struct snd_pcm_substream *substream) | |
111 | { | |
112 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
113 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | |
fb0ef645 NM |
114 | struct snd_soc_device *socdev = rtd->socdev; |
115 | struct snd_soc_platform *platform = socdev->platform; | |
310355c1 | 116 | u32 w; |
fb0ef645 | 117 | int ret; |
310355c1 VB |
118 | |
119 | /* Start the sample generator and enable transmitter/receiver */ | |
120 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | |
121 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1); | |
fb0ef645 NM |
122 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); |
123 | ||
124 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
125 | /* Stop the DMA to avoid data loss */ | |
126 | /* while the transmitter is out of reset to handle XSYNCERR */ | |
127 | if (platform->pcm_ops->trigger) { | |
128 | ret = platform->pcm_ops->trigger(substream, | |
129 | SNDRV_PCM_TRIGGER_STOP); | |
130 | if (ret < 0) | |
131 | printk(KERN_DEBUG "Playback DMA stop failed\n"); | |
132 | } | |
133 | ||
134 | /* Enable the transmitter */ | |
135 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | |
310355c1 | 136 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1); |
fb0ef645 NM |
137 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); |
138 | ||
139 | /* wait for any unexpected frame sync error to occur */ | |
140 | udelay(100); | |
141 | ||
142 | /* Disable the transmitter to clear any outstanding XSYNCERR */ | |
143 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | |
144 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0); | |
145 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | |
146 | ||
147 | /* Restart the DMA */ | |
148 | if (platform->pcm_ops->trigger) { | |
149 | ret = platform->pcm_ops->trigger(substream, | |
150 | SNDRV_PCM_TRIGGER_START); | |
151 | if (ret < 0) | |
152 | printk(KERN_DEBUG "Playback DMA start failed\n"); | |
153 | } | |
154 | /* Enable the transmitter */ | |
155 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | |
156 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1); | |
157 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | |
158 | ||
159 | } else { | |
160 | ||
161 | /* Enable the reciever */ | |
162 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | |
310355c1 | 163 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1); |
fb0ef645 NM |
164 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); |
165 | } | |
166 | ||
310355c1 VB |
167 | |
168 | /* Start frame sync */ | |
169 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | |
170 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1); | |
171 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | |
172 | } | |
173 | ||
174 | static void davinci_mcbsp_stop(struct snd_pcm_substream *substream) | |
175 | { | |
176 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
177 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | |
178 | u32 w; | |
179 | ||
180 | /* Reset transmitter/receiver and sample rate/frame sync generators */ | |
181 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); | |
182 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST | | |
183 | DAVINCI_MCBSP_SPCR_FRST, 0); | |
184 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
185 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0); | |
186 | else | |
187 | MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0); | |
188 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | |
189 | } | |
190 | ||
191 | static int davinci_i2s_startup(struct snd_pcm_substream *substream) | |
192 | { | |
193 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
9cb132d7 | 194 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
310355c1 VB |
195 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; |
196 | ||
197 | cpu_dai->dma_data = dev->dma_params[substream->stream]; | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
9cb132d7 | 202 | static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
310355c1 VB |
203 | unsigned int fmt) |
204 | { | |
205 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; | |
206 | u32 w; | |
207 | ||
208 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
209 | case SND_SOC_DAIFMT_CBS_CFS: | |
210 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, | |
211 | DAVINCI_MCBSP_PCR_FSXM | | |
212 | DAVINCI_MCBSP_PCR_FSRM | | |
213 | DAVINCI_MCBSP_PCR_CLKXM | | |
214 | DAVINCI_MCBSP_PCR_CLKRM); | |
215 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, | |
216 | DAVINCI_MCBSP_SRGR_FSGM); | |
217 | break; | |
b402dff8 HV |
218 | case SND_SOC_DAIFMT_CBM_CFS: |
219 | /* McBSP CLKR pin is the input for the Sample Rate Generator. | |
220 | * McBSP FSR and FSX are driven by the Sample Rate Generator. */ | |
221 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, | |
222 | DAVINCI_MCBSP_PCR_SCLKME | | |
223 | DAVINCI_MCBSP_PCR_FSXM | | |
224 | DAVINCI_MCBSP_PCR_FSRM); | |
225 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, | |
226 | DAVINCI_MCBSP_SRGR_FSGM); | |
227 | break; | |
310355c1 VB |
228 | case SND_SOC_DAIFMT_CBM_CFM: |
229 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0); | |
230 | break; | |
231 | default: | |
232 | return -EINVAL; | |
233 | } | |
234 | ||
235 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
236 | case SND_SOC_DAIFMT_IB_NF: | |
237 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); | |
238 | MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP | | |
239 | DAVINCI_MCBSP_PCR_CLKRP, 1); | |
240 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); | |
241 | break; | |
242 | case SND_SOC_DAIFMT_NB_IF: | |
243 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); | |
244 | MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP | | |
245 | DAVINCI_MCBSP_PCR_FSRP, 1); | |
246 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); | |
247 | break; | |
248 | case SND_SOC_DAIFMT_IB_IF: | |
249 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); | |
250 | MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP | | |
251 | DAVINCI_MCBSP_PCR_CLKRP | | |
252 | DAVINCI_MCBSP_PCR_FSXP | | |
253 | DAVINCI_MCBSP_PCR_FSRP, 1); | |
254 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); | |
255 | break; | |
256 | case SND_SOC_DAIFMT_NB_NF: | |
257 | break; | |
258 | default: | |
259 | return -EINVAL; | |
260 | } | |
261 | ||
b402dff8 HV |
262 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
263 | case SND_SOC_DAIFMT_RIGHT_J: | |
264 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, | |
265 | DAVINCI_MCBSP_RCR_RFRLEN1(1) | | |
266 | DAVINCI_MCBSP_RCR_RDATDLY(0)); | |
267 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, | |
268 | DAVINCI_MCBSP_XCR_XFRLEN1(1) | | |
269 | DAVINCI_MCBSP_XCR_XDATDLY(0) | | |
270 | DAVINCI_MCBSP_XCR_XFIG); | |
271 | break; | |
272 | case SND_SOC_DAIFMT_I2S: | |
273 | default: | |
274 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, | |
275 | DAVINCI_MCBSP_RCR_RFRLEN1(1) | | |
276 | DAVINCI_MCBSP_RCR_RDATDLY(1)); | |
277 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, | |
278 | DAVINCI_MCBSP_XCR_XFRLEN1(1) | | |
279 | DAVINCI_MCBSP_XCR_XDATDLY(1) | | |
280 | DAVINCI_MCBSP_XCR_XFIG); | |
281 | break; | |
282 | } | |
283 | ||
310355c1 VB |
284 | return 0; |
285 | } | |
286 | ||
287 | static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, | |
288 | struct snd_pcm_hw_params *params) | |
289 | { | |
290 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
291 | struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data; | |
292 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | |
293 | struct snd_interval *i = NULL; | |
294 | int mcbsp_word_length; | |
295 | u32 w; | |
296 | ||
297 | /* general line settings */ | |
cb6e2063 NM |
298 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
299 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { | |
300 | w |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE; | |
301 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | |
302 | } else { | |
303 | w |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE; | |
304 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w); | |
305 | } | |
310355c1 VB |
306 | |
307 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); | |
308 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG); | |
309 | MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1); | |
310 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w); | |
311 | ||
312 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); | |
313 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG); | |
314 | MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1); | |
315 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w); | |
316 | ||
317 | /* Determine xfer data type */ | |
318 | switch (params_format(params)) { | |
319 | case SNDRV_PCM_FORMAT_S8: | |
320 | dma_params->data_type = 1; | |
321 | mcbsp_word_length = DAVINCI_MCBSP_WORD_8; | |
322 | break; | |
323 | case SNDRV_PCM_FORMAT_S16_LE: | |
324 | dma_params->data_type = 2; | |
325 | mcbsp_word_length = DAVINCI_MCBSP_WORD_16; | |
326 | break; | |
327 | case SNDRV_PCM_FORMAT_S32_LE: | |
328 | dma_params->data_type = 4; | |
329 | mcbsp_word_length = DAVINCI_MCBSP_WORD_32; | |
330 | break; | |
331 | default: | |
9b6e12e4 | 332 | printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n"); |
310355c1 VB |
333 | return -EINVAL; |
334 | } | |
335 | ||
cb6e2063 NM |
336 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
337 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG); | |
338 | MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | | |
339 | DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1); | |
340 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w); | |
310355c1 | 341 | |
cb6e2063 NM |
342 | } else { |
343 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG); | |
344 | MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) | | |
345 | DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1); | |
346 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w); | |
310355c1 | 347 | |
cb6e2063 | 348 | } |
310355c1 VB |
349 | return 0; |
350 | } | |
351 | ||
352 | static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd) | |
353 | { | |
354 | int ret = 0; | |
355 | ||
356 | switch (cmd) { | |
357 | case SNDRV_PCM_TRIGGER_START: | |
358 | case SNDRV_PCM_TRIGGER_RESUME: | |
359 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
360 | davinci_mcbsp_start(substream); | |
361 | break; | |
362 | case SNDRV_PCM_TRIGGER_STOP: | |
363 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
364 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
365 | davinci_mcbsp_stop(substream); | |
366 | break; | |
367 | default: | |
368 | ret = -EINVAL; | |
369 | } | |
370 | ||
371 | return ret; | |
372 | } | |
373 | ||
bdb92876 | 374 | static int davinci_i2s_probe(struct platform_device *pdev, |
9cb132d7 | 375 | struct snd_soc_dai *dai) |
310355c1 VB |
376 | { |
377 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
87506549 MB |
378 | struct snd_soc_card *card = socdev->card; |
379 | struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai; | |
310355c1 VB |
380 | struct davinci_mcbsp_dev *dev; |
381 | struct resource *mem, *ioarea; | |
382 | struct evm_snd_platform_data *pdata; | |
383 | int ret; | |
384 | ||
385 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
386 | if (!mem) { | |
387 | dev_err(&pdev->dev, "no mem resource?\n"); | |
388 | return -ENODEV; | |
389 | } | |
390 | ||
391 | ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1, | |
392 | pdev->name); | |
393 | if (!ioarea) { | |
394 | dev_err(&pdev->dev, "McBSP region already claimed\n"); | |
395 | return -EBUSY; | |
396 | } | |
397 | ||
398 | dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL); | |
399 | if (!dev) { | |
400 | ret = -ENOMEM; | |
401 | goto err_release_region; | |
402 | } | |
403 | ||
404 | cpu_dai->private_data = dev; | |
405 | ||
406 | dev->clk = clk_get(&pdev->dev, "McBSPCLK"); | |
407 | if (IS_ERR(dev->clk)) { | |
408 | ret = -ENODEV; | |
409 | goto err_free_mem; | |
410 | } | |
411 | clk_enable(dev->clk); | |
412 | ||
413 | dev->base = (void __iomem *)IO_ADDRESS(mem->start); | |
414 | pdata = pdev->dev.platform_data; | |
415 | ||
416 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out; | |
417 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch; | |
418 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr = | |
419 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG); | |
420 | ||
421 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in; | |
422 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch; | |
423 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr = | |
424 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG); | |
425 | ||
426 | return 0; | |
427 | ||
428 | err_free_mem: | |
429 | kfree(dev); | |
430 | err_release_region: | |
431 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
432 | ||
433 | return ret; | |
434 | } | |
435 | ||
bdb92876 | 436 | static void davinci_i2s_remove(struct platform_device *pdev, |
9cb132d7 | 437 | struct snd_soc_dai *dai) |
310355c1 VB |
438 | { |
439 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
87506549 MB |
440 | struct snd_soc_card *card = socdev->card; |
441 | struct snd_soc_dai *cpu_dai = card->dai_link[pdev->id].cpu_dai; | |
310355c1 VB |
442 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; |
443 | struct resource *mem; | |
444 | ||
445 | clk_disable(dev->clk); | |
446 | clk_put(dev->clk); | |
447 | dev->clk = NULL; | |
448 | ||
449 | kfree(dev); | |
450 | ||
451 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
452 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
453 | } | |
454 | ||
455 | #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 | |
456 | ||
9cb132d7 | 457 | struct snd_soc_dai davinci_i2s_dai = { |
310355c1 VB |
458 | .name = "davinci-i2s", |
459 | .id = 0, | |
460 | .type = SND_SOC_DAI_I2S, | |
461 | .probe = davinci_i2s_probe, | |
462 | .remove = davinci_i2s_remove, | |
463 | .playback = { | |
464 | .channels_min = 2, | |
465 | .channels_max = 2, | |
466 | .rates = DAVINCI_I2S_RATES, | |
467 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
468 | .capture = { | |
469 | .channels_min = 2, | |
470 | .channels_max = 2, | |
471 | .rates = DAVINCI_I2S_RATES, | |
472 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
473 | .ops = { | |
474 | .startup = davinci_i2s_startup, | |
475 | .trigger = davinci_i2s_trigger, | |
476 | .hw_params = davinci_i2s_hw_params,}, | |
477 | .dai_ops = { | |
478 | .set_fmt = davinci_i2s_set_dai_fmt, | |
479 | }, | |
480 | }; | |
481 | EXPORT_SYMBOL_GPL(davinci_i2s_dai); | |
482 | ||
483 | MODULE_AUTHOR("Vladimir Barinov"); | |
484 | MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface"); | |
485 | MODULE_LICENSE("GPL"); |