[deliverable/linux.git] / sound / soc / davinci / davinci-i2s.c

/*
 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
 *
 * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
 * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include "davinci-pcm.h"

#define DAVINCI_MCBSP_DRR_REG	0x00
#define DAVINCI_MCBSP_DXR_REG	0x04
#define DAVINCI_MCBSP_SPCR_REG	0x08
#define DAVINCI_MCBSP_RCR_REG	0x0c
#define DAVINCI_MCBSP_XCR_REG	0x10
#define DAVINCI_MCBSP_SRGR_REG	0x14
#define DAVINCI_MCBSP_PCR_REG	0x24

#define DAVINCI_MCBSP_SPCR_RRST		(1 << 0)
#define DAVINCI_MCBSP_SPCR_RINTM(v)	((v) << 4)
#define DAVINCI_MCBSP_SPCR_XRST		(1 << 16)
#define DAVINCI_MCBSP_SPCR_XINTM(v)	((v) << 20)
#define DAVINCI_MCBSP_SPCR_GRST		(1 << 22)
#define DAVINCI_MCBSP_SPCR_FRST		(1 << 23)
#define DAVINCI_MCBSP_SPCR_FREE		(1 << 25)

#define DAVINCI_MCBSP_RCR_RWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_RCR_RFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_RCR_RDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_RCR_RWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_XCR_XWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_XCR_XFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_XCR_XDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_XCR_XFIG		(1 << 18)
#define DAVINCI_MCBSP_XCR_XWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_SRGR_FWID(v)	((v) << 8)
#define DAVINCI_MCBSP_SRGR_FPER(v)	((v) << 16)
#define DAVINCI_MCBSP_SRGR_FSGM		(1 << 28)

#define DAVINCI_MCBSP_PCR_CLKRP		(1 << 0)
#define DAVINCI_MCBSP_PCR_CLKXP		(1 << 1)
#define DAVINCI_MCBSP_PCR_FSRP		(1 << 2)
#define DAVINCI_MCBSP_PCR_FSXP		(1 << 3)
#define DAVINCI_MCBSP_PCR_SCLKME	(1 << 7)
#define DAVINCI_MCBSP_PCR_CLKRM		(1 << 8)
#define DAVINCI_MCBSP_PCR_CLKXM		(1 << 9)
#define DAVINCI_MCBSP_PCR_FSRM		(1 << 10)
#define DAVINCI_MCBSP_PCR_FSXM		(1 << 11)

#define MOD_REG_BIT(val, mask, set) do { \
	if (set) { \
		val |= mask; \
	} else { \
		val &= ~mask; \
	} \
} while (0)

enum {
	DAVINCI_MCBSP_WORD_8 = 0,
	DAVINCI_MCBSP_WORD_12,
	DAVINCI_MCBSP_WORD_16,
	DAVINCI_MCBSP_WORD_20,
	DAVINCI_MCBSP_WORD_24,
	DAVINCI_MCBSP_WORD_32,
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	.name = "I2S PCM Stereo out",
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	.name = "I2S PCM Stereo in",
};

struct davinci_mcbsp_dev {
	void __iomem			*base;
	struct clk			*clk;
	struct davinci_pcm_dma_params	*dma_params[2];
};

static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
					   int reg, u32 val)
{
	__raw_writel(val, dev->base + reg);
}

static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
{
	return __raw_readl(dev->base + reg);
}

static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	u32 w;

	/* Start the sample generator and enable transmitter/receiver */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
	else
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);

	/* Start frame sync */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
}

static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	u32 w;

	/* Reset transmitter/receiver and sample rate/frame sync generators */
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST |
		       DAVINCI_MCBSP_SPCR_FRST, 0);
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
	else
		MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
}

static int davinci_i2s_startup(struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;

	cpu_dai->dma_data = dev->dma_params[substream->stream];

	return 0;
}

static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				   unsigned int fmt)
{
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	u32 w;

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
					DAVINCI_MCBSP_PCR_FSXM |
					DAVINCI_MCBSP_PCR_FSRM |
					DAVINCI_MCBSP_PCR_CLKXM |
					DAVINCI_MCBSP_PCR_CLKRM);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
					DAVINCI_MCBSP_SRGR_FSGM);
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		/* McBSP CLKR pin is the input for the Sample Rate Generator.
		 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
					DAVINCI_MCBSP_PCR_SCLKME |
					DAVINCI_MCBSP_PCR_FSXM |
					DAVINCI_MCBSP_PCR_FSRM);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
					DAVINCI_MCBSP_SRGR_FSGM);
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0);
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_NF:
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
			       DAVINCI_MCBSP_PCR_CLKRP, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
		break;
	case SND_SOC_DAIFMT_NB_IF:
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP |
			       DAVINCI_MCBSP_PCR_FSRP, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
		break;
	case SND_SOC_DAIFMT_IB_IF:
		w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
		MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP |
			       DAVINCI_MCBSP_PCR_CLKRP |
			       DAVINCI_MCBSP_PCR_FSXP |
			       DAVINCI_MCBSP_PCR_FSRP, 1);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
		break;
	case SND_SOC_DAIFMT_NB_NF:
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
					DAVINCI_MCBSP_RCR_RFRLEN1(1) |
					DAVINCI_MCBSP_RCR_RDATDLY(0));
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
					DAVINCI_MCBSP_XCR_XFRLEN1(1) |
					DAVINCI_MCBSP_XCR_XDATDLY(0) |
					DAVINCI_MCBSP_XCR_XFIG);
		break;
	case SND_SOC_DAIFMT_I2S:
	default:
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
					DAVINCI_MCBSP_RCR_RFRLEN1(1) |
					DAVINCI_MCBSP_RCR_RDATDLY(1));
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
					DAVINCI_MCBSP_XCR_XFRLEN1(1) |
					DAVINCI_MCBSP_XCR_XDATDLY(1) |
					DAVINCI_MCBSP_XCR_XFIG);
		break;
	}

	return 0;
}

static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	struct snd_interval *i = NULL;
	int mcbsp_word_length;
	u32 w;

	/* general line settings */
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
				DAVINCI_MCBSP_SPCR_RINTM(3) |
				DAVINCI_MCBSP_SPCR_XINTM(3) |
				DAVINCI_MCBSP_SPCR_FREE);

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);

	/* Determine xfer data type */
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		dma_params->data_type = 1;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		dma_params->data_type = 2;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		dma_params->data_type = 4;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
		break;
	default:
		printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
		return -EINVAL;
	}

	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
		       DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);

	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
	MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
		       DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);

	return 0;
}

static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
{
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		davinci_mcbsp_start(substream);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		davinci_mcbsp_stop(substream);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static int davinci_i2s_probe(struct platform_device *pdev,
			     struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_machine *machine = socdev->machine;
	struct snd_soc_dai *cpu_dai = machine->dai_link[pdev->id].cpu_dai;
	struct davinci_mcbsp_dev *dev;
	struct resource *mem, *ioarea;
	struct evm_snd_platform_data *pdata;
	int ret;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "no mem resource?\n");
		return -ENODEV;
	}

	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
				    pdev->name);
	if (!ioarea) {
		dev_err(&pdev->dev, "McBSP region already claimed\n");
		return -EBUSY;
	}

	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	if (!dev) {
		ret = -ENOMEM;
		goto err_release_region;
	}

	cpu_dai->private_data = dev;

	dev->clk = clk_get(&pdev->dev, "McBSPCLK");
	if (IS_ERR(dev->clk)) {
		ret = -ENODEV;
		goto err_free_mem;
	}
	clk_enable(dev->clk);

	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	pdata = pdev->dev.platform_data;

	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);

	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);

	return 0;

err_free_mem:
	kfree(dev);
err_release_region:
	release_mem_region(mem->start, (mem->end - mem->start) + 1);

	return ret;
}

static void davinci_i2s_remove(struct platform_device *pdev,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_machine *machine = socdev->machine;
	struct snd_soc_dai *cpu_dai = machine->dai_link[pdev->id].cpu_dai;
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	struct resource *mem;

	clk_disable(dev->clk);
	clk_put(dev->clk);
	dev->clk = NULL;

	kfree(dev);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(mem->start, (mem->end - mem->start) + 1);
}

#define DAVINCI_I2S_RATES	SNDRV_PCM_RATE_8000_96000

struct snd_soc_dai davinci_i2s_dai = {
	.name = "davinci-i2s",
	.id = 0,
	.type = SND_SOC_DAI_I2S,
	.probe = davinci_i2s_probe,
	.remove = davinci_i2s_remove,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = {
		.startup = davinci_i2s_startup,
		.trigger = davinci_i2s_trigger,
		.hw_params = davinci_i2s_hw_params,},
	.dai_ops = {
		.set_fmt = davinci_i2s_set_dai_fmt,
	},
};
EXPORT_SYMBOL_GPL(davinci_i2s_dai);

MODULE_AUTHOR("Vladimir Barinov");
MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
310355c1 VB	1	/*
	2	* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
	3	*
d6b52039	4	* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
310355c1 VB	5	* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/module.h>
	14	#include <linux/device.h>
	15	#include <linux/delay.h>
	16	#include <linux/io.h>
	17	#include <linux/clk.h>
	18
	19	#include <sound/core.h>
	20	#include <sound/pcm.h>
	21	#include <sound/pcm_params.h>
	22	#include <sound/initval.h>
	23	#include <sound/soc.h>
	24
	25	#include "davinci-pcm.h"
	26
	27	#define DAVINCI_MCBSP_DRR_REG 0x00
	28	#define DAVINCI_MCBSP_DXR_REG 0x04
	29	#define DAVINCI_MCBSP_SPCR_REG 0x08
	30	#define DAVINCI_MCBSP_RCR_REG 0x0c
	31	#define DAVINCI_MCBSP_XCR_REG 0x10
	32	#define DAVINCI_MCBSP_SRGR_REG 0x14
	33	#define DAVINCI_MCBSP_PCR_REG 0x24
	34
	35	#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
	36	#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
	37	#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
	38	#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
	39	#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
	40	#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
	41	#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
	42
	43	#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
	44	#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
	45	#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
	46	#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
	47
	48	#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
	49	#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
	50	#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
	51	#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
	52	#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
	53
	54	#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
	55	#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
	56	#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
	57
	58	#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
	59	#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
	60	#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
	61	#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
b402dff8	62	#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
310355c1 VB	63	#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
	64	#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
	65	#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
	66	#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
	67
	68	#define MOD_REG_BIT(val, mask, set) do { \
	69	if (set) { \
	70	val \|= mask; \
	71	} else { \
	72	val &= ~mask; \
	73	} \
	74	} while (0)
	75
	76	enum {
	77	DAVINCI_MCBSP_WORD_8 = 0,
	78	DAVINCI_MCBSP_WORD_12,
	79	DAVINCI_MCBSP_WORD_16,
	80	DAVINCI_MCBSP_WORD_20,
	81	DAVINCI_MCBSP_WORD_24,
	82	DAVINCI_MCBSP_WORD_32,
	83	};
	84
	85	static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	86	.name = "I2S PCM Stereo out",
	87	};
	88
	89	static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	90	.name = "I2S PCM Stereo in",
	91	};
	92
	93	struct davinci_mcbsp_dev {
	94	void __iomem *base;
	95	struct clk *clk;
	96	struct davinci_pcm_dma_params *dma_params[2];
	97	};
	98
	99	static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
	100	int reg, u32 val)
	101	{
	102	__raw_writel(val, dev->base + reg);
	103	}
	104
	105	static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
	106	{
	107	return __raw_readl(dev->base + reg);
	108	}
	109
	110	static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
	111	{
	112	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	113	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	114	u32 w;
	115
	116	/* Start the sample generator and enable transmitter/receiver */
	117	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	118	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
	119	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	120	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
	121	else
	122	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
	123	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
	124
	125	/* Start frame sync */
	126	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
127	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
128	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
129	}
130
131	static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
132	{
133	struct snd_soc_pcm_runtime *rtd = substream->private_data;
134	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
135	u32 w;
136
137	/* Reset transmitter/receiver and sample rate/frame sync generators */
138	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
139	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST \|
140	DAVINCI_MCBSP_SPCR_FRST, 0);
141	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
142	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
143	else
144	MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
145	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
146	}
147
148	static int davinci_i2s_startup(struct snd_pcm_substream *substream)
149	{
150	struct snd_soc_pcm_runtime *rtd = substream->private_data;
9cb132d7	151	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
310355c1 VB	152	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	153
	154	cpu_dai->dma_data = dev->dma_params[substream->stream];
	155
	156	return 0;
	157	}
	158
9cb132d7	159	static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
310355c1 VB	160	unsigned int fmt)
	161	{
	162	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	163	u32 w;
	164
	165	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	166	case SND_SOC_DAIFMT_CBS_CFS:
	167	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
	168	DAVINCI_MCBSP_PCR_FSXM \|
	169	DAVINCI_MCBSP_PCR_FSRM \|
	170	DAVINCI_MCBSP_PCR_CLKXM \|
	171	DAVINCI_MCBSP_PCR_CLKRM);
	172	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
	173	DAVINCI_MCBSP_SRGR_FSGM);
	174	break;
b402dff8 HV	175	case SND_SOC_DAIFMT_CBM_CFS:
	176	/* McBSP CLKR pin is the input for the Sample Rate Generator.
	177	* McBSP FSR and FSX are driven by the Sample Rate Generator. */
	178	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG,
	179	DAVINCI_MCBSP_PCR_SCLKME \|
	180	DAVINCI_MCBSP_PCR_FSXM \|
	181	DAVINCI_MCBSP_PCR_FSRM);
	182	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG,
	183	DAVINCI_MCBSP_SRGR_FSGM);
	184	break;
310355c1 VB	185	case SND_SOC_DAIFMT_CBM_CFM:
	186	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, 0);
	187	break;
	188	default:
	189	return -EINVAL;
	190	}
	191
	192	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	193	case SND_SOC_DAIFMT_IB_NF:
	194	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
	195	MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP \|
	196	DAVINCI_MCBSP_PCR_CLKRP, 1);
	197	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
	198	break;
	199	case SND_SOC_DAIFMT_NB_IF:
	200	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
	201	MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP \|
	202	DAVINCI_MCBSP_PCR_FSRP, 1);
	203	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
	204	break;
	205	case SND_SOC_DAIFMT_IB_IF:
	206	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG);
	207	MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP \|
	208	DAVINCI_MCBSP_PCR_CLKRP \|
	209	DAVINCI_MCBSP_PCR_FSXP \|
	210	DAVINCI_MCBSP_PCR_FSRP, 1);
	211	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w);
	212	break;
	213	case SND_SOC_DAIFMT_NB_NF:
	214	break;
	215	default:
	216	return -EINVAL;
	217	}
	218
b402dff8 HV	219	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	220	case SND_SOC_DAIFMT_RIGHT_J:
	221	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
	222	DAVINCI_MCBSP_RCR_RFRLEN1(1) \|
	223	DAVINCI_MCBSP_RCR_RDATDLY(0));
	224	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
	225	DAVINCI_MCBSP_XCR_XFRLEN1(1) \|
	226	DAVINCI_MCBSP_XCR_XDATDLY(0) \|
	227	DAVINCI_MCBSP_XCR_XFIG);
	228	break;
	229	case SND_SOC_DAIFMT_I2S:
	230	default:
	231	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG,
	232	DAVINCI_MCBSP_RCR_RFRLEN1(1) \|
	233	DAVINCI_MCBSP_RCR_RDATDLY(1));
	234	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG,
	235	DAVINCI_MCBSP_XCR_XFRLEN1(1) \|
	236	DAVINCI_MCBSP_XCR_XDATDLY(1) \|
	237	DAVINCI_MCBSP_XCR_XFIG);
	238	break;
	239	}
	240
310355c1 VB	241	return 0;
	242	}
	243
	244	static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
	245	struct snd_pcm_hw_params *params)
	246	{
	247	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	248	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	249	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	250	struct snd_interval *i = NULL;
	251	int mcbsp_word_length;
	252	u32 w;
	253
	254	/* general line settings */
	255	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
	256	DAVINCI_MCBSP_SPCR_RINTM(3) \|
	257	DAVINCI_MCBSP_SPCR_XINTM(3) \|
	258	DAVINCI_MCBSP_SPCR_FREE);
310355c1 VB	259
	260	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
	261	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
	262	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
	263	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
	264
	265	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
	266	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SRGR_REG);
	267	MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
	268	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
	269
	270	/* Determine xfer data type */
	271	switch (params_format(params)) {
	272	case SNDRV_PCM_FORMAT_S8:
	273	dma_params->data_type = 1;
	274	mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
	275	break;
	276	case SNDRV_PCM_FORMAT_S16_LE:
	277	dma_params->data_type = 2;
	278	mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
	279	break;
	280	case SNDRV_PCM_FORMAT_S32_LE:
	281	dma_params->data_type = 4;
	282	mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
	283	break;
	284	default:
9b6e12e4	285	printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
310355c1 VB	286	return -EINVAL;
	287	}
	288
	289	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
	290	MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) \|
	291	DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
	292	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);
	293
	294	w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
	295	MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) \|
	296	DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
	297	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);
	298
	299	return 0;
	300	}
	301
	302	static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
	303	{
	304	int ret = 0;
	305
	306	switch (cmd) {
	307	case SNDRV_PCM_TRIGGER_START:
	308	case SNDRV_PCM_TRIGGER_RESUME:
	309	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	310	davinci_mcbsp_start(substream);
	311	break;
	312	case SNDRV_PCM_TRIGGER_STOP:
	313	case SNDRV_PCM_TRIGGER_SUSPEND:
	314	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	315	davinci_mcbsp_stop(substream);
	316	break;
	317	default:
	318	ret = -EINVAL;
	319	}
	320
	321	return ret;
	322	}
	323
bdb92876	324	static int davinci_i2s_probe(struct platform_device *pdev,
9cb132d7	325	struct snd_soc_dai *dai)
310355c1 VB	326	{
	327	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	328	struct snd_soc_machine *machine = socdev->machine;
9cb132d7	329	struct snd_soc_dai *cpu_dai = machine->dai_link[pdev->id].cpu_dai;
310355c1 VB	330	struct davinci_mcbsp_dev *dev;
	331	struct resource mem, ioarea;
	332	struct evm_snd_platform_data *pdata;
	333	int ret;
	334
	335	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	336	if (!mem) {
	337	dev_err(&pdev->dev, "no mem resource?\n");
	338	return -ENODEV;
	339	}
	340
	341	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
	342	pdev->name);
	343	if (!ioarea) {
	344	dev_err(&pdev->dev, "McBSP region already claimed\n");
	345	return -EBUSY;
	346	}
	347
	348	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	349	if (!dev) {
	350	ret = -ENOMEM;
	351	goto err_release_region;
	352	}
	353
	354	cpu_dai->private_data = dev;
	355
	356	dev->clk = clk_get(&pdev->dev, "McBSPCLK");
	357	if (IS_ERR(dev->clk)) {
	358	ret = -ENODEV;
	359	goto err_free_mem;
	360	}
	361	clk_enable(dev->clk);
	362
	363	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	364	pdata = pdev->dev.platform_data;
	365
	366	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	367	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	368	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	369	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
	370
	371	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	372	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	373	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	374	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
	375
	376	return 0;
	377
	378	err_free_mem:
	379	kfree(dev);
	380	err_release_region:
	381	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	382
	383	return ret;
	384	}
	385
bdb92876	386	static void davinci_i2s_remove(struct platform_device *pdev,
9cb132d7	387	struct snd_soc_dai *dai)
310355c1 VB	388	{
	389	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	390	struct snd_soc_machine *machine = socdev->machine;
9cb132d7	391	struct snd_soc_dai *cpu_dai = machine->dai_link[pdev->id].cpu_dai;
310355c1 VB	392	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	393	struct resource *mem;
	394
	395	clk_disable(dev->clk);
	396	clk_put(dev->clk);
	397	dev->clk = NULL;
	398
	399	kfree(dev);
	400
	401	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	402	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	403	}
	404
	405	#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
	406
9cb132d7	407	struct snd_soc_dai davinci_i2s_dai = {
310355c1 VB	408	.name = "davinci-i2s",
	409	.id = 0,
	410	.type = SND_SOC_DAI_I2S,
	411	.probe = davinci_i2s_probe,
	412	.remove = davinci_i2s_remove,
	413	.playback = {
	414	.channels_min = 2,
	415	.channels_max = 2,
	416	.rates = DAVINCI_I2S_RATES,
	417	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	418	.capture = {
	419	.channels_min = 2,
	420	.channels_max = 2,
	421	.rates = DAVINCI_I2S_RATES,
	422	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	423	.ops = {
	424	.startup = davinci_i2s_startup,
	425	.trigger = davinci_i2s_trigger,
	426	.hw_params = davinci_i2s_hw_params,},
	427	.dai_ops = {
	428	.set_fmt = davinci_i2s_set_dai_fmt,
	429	},
	430	};
	431	EXPORT_SYMBOL_GPL(davinci_i2s_dai);
	432
	433	MODULE_AUTHOR("Vladimir Barinov");
	434	MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
	435	MODULE_LICENSE("GPL");