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310355c1 VB |
1 | /* |
2 | * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor | |
3 | * | |
d6b52039 | 4 | * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> |
310355c1 VB |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/clk.h> | |
18 | ||
19 | #include <sound/core.h> | |
20 | #include <sound/pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/initval.h> | |
23 | #include <sound/soc.h> | |
24 | ||
25 | #include "davinci-pcm.h" | |
26 | ||
a62114cb DB |
27 | |
28 | /* | |
29 | * NOTE: terminology here is confusing. | |
30 | * | |
31 | * - This driver supports the "Audio Serial Port" (ASP), | |
32 | * found on dm6446, dm355, and other DaVinci chips. | |
33 | * | |
34 | * - But it labels it a "Multi-channel Buffered Serial Port" | |
35 | * (McBSP) as on older chips like the dm642 ... which was | |
36 | * backward-compatible, possibly explaining that confusion. | |
37 | * | |
38 | * - OMAP chips have a controller called McBSP, which is | |
39 | * incompatible with the DaVinci flavor of McBSP. | |
40 | * | |
41 | * - Newer DaVinci chips have a controller called McASP, | |
42 | * incompatible with ASP and with either McBSP. | |
43 | * | |
44 | * In short: this uses ASP to implement I2S, not McBSP. | |
45 | * And it won't be the only DaVinci implemention of I2S. | |
46 | */ | |
310355c1 VB |
47 | #define DAVINCI_MCBSP_DRR_REG 0x00 |
48 | #define DAVINCI_MCBSP_DXR_REG 0x04 | |
49 | #define DAVINCI_MCBSP_SPCR_REG 0x08 | |
50 | #define DAVINCI_MCBSP_RCR_REG 0x0c | |
51 | #define DAVINCI_MCBSP_XCR_REG 0x10 | |
52 | #define DAVINCI_MCBSP_SRGR_REG 0x14 | |
53 | #define DAVINCI_MCBSP_PCR_REG 0x24 | |
54 | ||
55 | #define DAVINCI_MCBSP_SPCR_RRST (1 << 0) | |
56 | #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4) | |
57 | #define DAVINCI_MCBSP_SPCR_XRST (1 << 16) | |
58 | #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20) | |
59 | #define DAVINCI_MCBSP_SPCR_GRST (1 << 22) | |
60 | #define DAVINCI_MCBSP_SPCR_FRST (1 << 23) | |
61 | #define DAVINCI_MCBSP_SPCR_FREE (1 << 25) | |
62 | ||
63 | #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5) | |
64 | #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8) | |
65 | #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) | |
66 | #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) | |
67 | ||
68 | #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) | |
69 | #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) | |
70 | #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) | |
71 | #define DAVINCI_MCBSP_XCR_XFIG (1 << 18) | |
72 | #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) | |
73 | ||
74 | #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) | |
75 | #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) | |
76 | #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) | |
77 | ||
78 | #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) | |
79 | #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) | |
80 | #define DAVINCI_MCBSP_PCR_FSRP (1 << 2) | |
81 | #define DAVINCI_MCBSP_PCR_FSXP (1 << 3) | |
b402dff8 | 82 | #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7) |
310355c1 VB |
83 | #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8) |
84 | #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9) | |
85 | #define DAVINCI_MCBSP_PCR_FSRM (1 << 10) | |
86 | #define DAVINCI_MCBSP_PCR_FSXM (1 << 11) | |
87 | ||
310355c1 VB |
88 | enum { |
89 | DAVINCI_MCBSP_WORD_8 = 0, | |
90 | DAVINCI_MCBSP_WORD_12, | |
91 | DAVINCI_MCBSP_WORD_16, | |
92 | DAVINCI_MCBSP_WORD_20, | |
93 | DAVINCI_MCBSP_WORD_24, | |
94 | DAVINCI_MCBSP_WORD_32, | |
95 | }; | |
96 | ||
97 | static struct davinci_pcm_dma_params davinci_i2s_pcm_out = { | |
98 | .name = "I2S PCM Stereo out", | |
99 | }; | |
100 | ||
101 | static struct davinci_pcm_dma_params davinci_i2s_pcm_in = { | |
102 | .name = "I2S PCM Stereo in", | |
103 | }; | |
104 | ||
105 | struct davinci_mcbsp_dev { | |
106 | void __iomem *base; | |
c392bec7 | 107 | u32 pcr; |
310355c1 VB |
108 | struct clk *clk; |
109 | struct davinci_pcm_dma_params *dma_params[2]; | |
110 | }; | |
111 | ||
112 | static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, | |
113 | int reg, u32 val) | |
114 | { | |
115 | __raw_writel(val, dev->base + reg); | |
116 | } | |
117 | ||
118 | static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg) | |
119 | { | |
120 | return __raw_readl(dev->base + reg); | |
121 | } | |
122 | ||
c392bec7 TK |
123 | static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback) |
124 | { | |
125 | u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP; | |
126 | /* The clock needs to toggle to complete reset. | |
127 | * So, fake it by toggling the clk polarity. | |
128 | */ | |
129 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m); | |
130 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr); | |
131 | } | |
132 | ||
310355c1 VB |
133 | static void davinci_mcbsp_start(struct snd_pcm_substream *substream) |
134 | { | |
135 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
136 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | |
fb0ef645 | 137 | struct snd_soc_device *socdev = rtd->socdev; |
87689d56 | 138 | struct snd_soc_platform *platform = socdev->card->platform; |
c392bec7 | 139 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
35cf6358 | 140 | u32 spcr; |
fb0ef645 | 141 | int ret; |
c392bec7 | 142 | u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 143 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
c392bec7 TK |
144 | if (spcr & mask) { |
145 | /* start off disabled */ | |
146 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, | |
147 | spcr & ~mask); | |
148 | toggle_clock(dev, playback); | |
149 | } | |
150 | /* Start the sample generator and enable transmitter/receiver */ | |
35cf6358 TK |
151 | spcr |= DAVINCI_MCBSP_SPCR_GRST; |
152 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
fb0ef645 NM |
153 | |
154 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
155 | /* Stop the DMA to avoid data loss */ | |
156 | /* while the transmitter is out of reset to handle XSYNCERR */ | |
157 | if (platform->pcm_ops->trigger) { | |
158 | ret = platform->pcm_ops->trigger(substream, | |
159 | SNDRV_PCM_TRIGGER_STOP); | |
160 | if (ret < 0) | |
161 | printk(KERN_DEBUG "Playback DMA stop failed\n"); | |
162 | } | |
163 | ||
164 | /* Enable the transmitter */ | |
35cf6358 TK |
165 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
166 | spcr |= DAVINCI_MCBSP_SPCR_XRST; | |
167 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
fb0ef645 NM |
168 | |
169 | /* wait for any unexpected frame sync error to occur */ | |
170 | udelay(100); | |
171 | ||
172 | /* Disable the transmitter to clear any outstanding XSYNCERR */ | |
35cf6358 TK |
173 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
174 | spcr &= ~DAVINCI_MCBSP_SPCR_XRST; | |
175 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
c392bec7 | 176 | toggle_clock(dev, playback); |
fb0ef645 NM |
177 | |
178 | /* Restart the DMA */ | |
179 | if (platform->pcm_ops->trigger) { | |
180 | ret = platform->pcm_ops->trigger(substream, | |
181 | SNDRV_PCM_TRIGGER_START); | |
182 | if (ret < 0) | |
183 | printk(KERN_DEBUG "Playback DMA start failed\n"); | |
184 | } | |
185 | /* Enable the transmitter */ | |
35cf6358 TK |
186 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
187 | spcr |= DAVINCI_MCBSP_SPCR_XRST; | |
188 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
fb0ef645 NM |
189 | |
190 | } else { | |
191 | ||
192 | /* Enable the reciever */ | |
35cf6358 TK |
193 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
194 | spcr |= DAVINCI_MCBSP_SPCR_RRST; | |
195 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
fb0ef645 NM |
196 | } |
197 | ||
310355c1 VB |
198 | |
199 | /* Start frame sync */ | |
35cf6358 TK |
200 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
201 | spcr |= DAVINCI_MCBSP_SPCR_FRST; | |
202 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
310355c1 VB |
203 | } |
204 | ||
205 | static void davinci_mcbsp_stop(struct snd_pcm_substream *substream) | |
206 | { | |
207 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
208 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | |
35cf6358 | 209 | u32 spcr; |
c392bec7 | 210 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
310355c1 VB |
211 | |
212 | /* Reset transmitter/receiver and sample rate/frame sync generators */ | |
35cf6358 TK |
213 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
214 | spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST); | |
c392bec7 | 215 | spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 216 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
c392bec7 | 217 | toggle_clock(dev, playback); |
310355c1 VB |
218 | } |
219 | ||
dee89c4d MB |
220 | static int davinci_i2s_startup(struct snd_pcm_substream *substream, |
221 | struct snd_soc_dai *dai) | |
310355c1 VB |
222 | { |
223 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
9cb132d7 | 224 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
310355c1 VB |
225 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; |
226 | ||
227 | cpu_dai->dma_data = dev->dma_params[substream->stream]; | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
21903c1c TK |
232 | #define DEFAULT_BITPERSAMPLE 16 |
233 | ||
9cb132d7 | 234 | static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
310355c1 VB |
235 | unsigned int fmt) |
236 | { | |
237 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; | |
21903c1c TK |
238 | unsigned int pcr; |
239 | unsigned int srgr; | |
240 | unsigned int rcr; | |
241 | unsigned int xcr; | |
242 | srgr = DAVINCI_MCBSP_SRGR_FSGM | | |
243 | DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | | |
244 | DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); | |
310355c1 VB |
245 | |
246 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
247 | case SND_SOC_DAIFMT_CBS_CFS: | |
21903c1c TK |
248 | /* cpu is master */ |
249 | pcr = DAVINCI_MCBSP_PCR_FSXM | | |
250 | DAVINCI_MCBSP_PCR_FSRM | | |
251 | DAVINCI_MCBSP_PCR_CLKXM | | |
252 | DAVINCI_MCBSP_PCR_CLKRM; | |
310355c1 | 253 | break; |
b402dff8 HV |
254 | case SND_SOC_DAIFMT_CBM_CFS: |
255 | /* McBSP CLKR pin is the input for the Sample Rate Generator. | |
256 | * McBSP FSR and FSX are driven by the Sample Rate Generator. */ | |
21903c1c TK |
257 | pcr = DAVINCI_MCBSP_PCR_SCLKME | |
258 | DAVINCI_MCBSP_PCR_FSXM | | |
259 | DAVINCI_MCBSP_PCR_FSRM; | |
b402dff8 | 260 | break; |
310355c1 | 261 | case SND_SOC_DAIFMT_CBM_CFM: |
21903c1c TK |
262 | /* codec is master */ |
263 | pcr = 0; | |
310355c1 VB |
264 | break; |
265 | default: | |
21903c1c | 266 | printk(KERN_ERR "%s:bad master\n", __func__); |
310355c1 VB |
267 | return -EINVAL; |
268 | } | |
269 | ||
69ab820c TK |
270 | rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1); |
271 | xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1); | |
272 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
07d8d9dc | 273 | case SND_SOC_DAIFMT_DSP_B: |
69ab820c TK |
274 | break; |
275 | case SND_SOC_DAIFMT_I2S: | |
07d8d9dc TK |
276 | /* Davinci doesn't support TRUE I2S, but some codecs will have |
277 | * the left and right channels contiguous. This allows | |
278 | * dsp_a mode to be used with an inverted normal frame clk. | |
279 | * If your codec is master and does not have contiguous | |
280 | * channels, then you will have sound on only one channel. | |
281 | * Try using a different mode, or codec as slave. | |
282 | * | |
283 | * The TLV320AIC33 is an example of a codec where this works. | |
284 | * It has a variable bit clock frequency allowing it to have | |
285 | * valid data on every bit clock. | |
286 | * | |
287 | * The TLV320AIC23 is an example of a codec where this does not | |
288 | * work. It has a fixed bit clock frequency with progressively | |
289 | * more empty bit clock slots between channels as the sample | |
290 | * rate is lowered. | |
291 | */ | |
292 | fmt ^= SND_SOC_DAIFMT_NB_IF; | |
293 | case SND_SOC_DAIFMT_DSP_A: | |
69ab820c TK |
294 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1); |
295 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1); | |
296 | break; | |
297 | default: | |
298 | printk(KERN_ERR "%s:bad format\n", __func__); | |
299 | return -EINVAL; | |
300 | } | |
301 | ||
310355c1 | 302 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
9e031624 | 303 | case SND_SOC_DAIFMT_NB_NF: |
664b4af8 TK |
304 | /* CLKRP Receive clock polarity, |
305 | * 1 - sampled on rising edge of CLKR | |
306 | * valid on rising edge | |
307 | * CLKXP Transmit clock polarity, | |
308 | * 1 - clocked on falling edge of CLKX | |
309 | * valid on rising edge | |
310 | * FSRP Receive frame sync pol, 0 - active high | |
311 | * FSXP Transmit frame sync pol, 0 - active high | |
312 | */ | |
21903c1c | 313 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP); |
310355c1 | 314 | break; |
9e031624 | 315 | case SND_SOC_DAIFMT_IB_IF: |
664b4af8 TK |
316 | /* CLKRP Receive clock polarity, |
317 | * 0 - sampled on falling edge of CLKR | |
318 | * valid on falling edge | |
319 | * CLKXP Transmit clock polarity, | |
320 | * 0 - clocked on rising edge of CLKX | |
321 | * valid on falling edge | |
322 | * FSRP Receive frame sync pol, 1 - active low | |
323 | * FSXP Transmit frame sync pol, 1 - active low | |
324 | */ | |
21903c1c | 325 | pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); |
310355c1 | 326 | break; |
9e031624 | 327 | case SND_SOC_DAIFMT_NB_IF: |
664b4af8 TK |
328 | /* CLKRP Receive clock polarity, |
329 | * 1 - sampled on rising edge of CLKR | |
330 | * valid on rising edge | |
331 | * CLKXP Transmit clock polarity, | |
332 | * 1 - clocked on falling edge of CLKX | |
333 | * valid on rising edge | |
334 | * FSRP Receive frame sync pol, 1 - active low | |
335 | * FSXP Transmit frame sync pol, 1 - active low | |
336 | */ | |
21903c1c TK |
337 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP | |
338 | DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); | |
310355c1 | 339 | break; |
9e031624 | 340 | case SND_SOC_DAIFMT_IB_NF: |
664b4af8 TK |
341 | /* CLKRP Receive clock polarity, |
342 | * 0 - sampled on falling edge of CLKR | |
343 | * valid on falling edge | |
344 | * CLKXP Transmit clock polarity, | |
345 | * 0 - clocked on rising edge of CLKX | |
346 | * valid on falling edge | |
347 | * FSRP Receive frame sync pol, 0 - active high | |
348 | * FSXP Transmit frame sync pol, 0 - active high | |
349 | */ | |
310355c1 VB |
350 | break; |
351 | default: | |
352 | return -EINVAL; | |
353 | } | |
21903c1c | 354 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); |
c392bec7 | 355 | dev->pcr = pcr; |
21903c1c TK |
356 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr); |
357 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); | |
358 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); | |
310355c1 VB |
359 | return 0; |
360 | } | |
361 | ||
362 | static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
363 | struct snd_pcm_hw_params *params, |
364 | struct snd_soc_dai *dai) | |
310355c1 VB |
365 | { |
366 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
367 | struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data; | |
368 | struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data; | |
369 | struct snd_interval *i = NULL; | |
370 | int mcbsp_word_length; | |
35cf6358 TK |
371 | unsigned int rcr, xcr, srgr; |
372 | u32 spcr; | |
310355c1 VB |
373 | |
374 | /* general line settings */ | |
35cf6358 | 375 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
cb6e2063 | 376 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
35cf6358 TK |
377 | spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
378 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 379 | } else { |
35cf6358 TK |
380 | spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
381 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 382 | } |
310355c1 VB |
383 | |
384 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); | |
35cf6358 TK |
385 | srgr = DAVINCI_MCBSP_SRGR_FSGM; |
386 | srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); | |
310355c1 VB |
387 | |
388 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); | |
35cf6358 TK |
389 | srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); |
390 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); | |
310355c1 VB |
391 | |
392 | /* Determine xfer data type */ | |
393 | switch (params_format(params)) { | |
394 | case SNDRV_PCM_FORMAT_S8: | |
395 | dma_params->data_type = 1; | |
396 | mcbsp_word_length = DAVINCI_MCBSP_WORD_8; | |
397 | break; | |
398 | case SNDRV_PCM_FORMAT_S16_LE: | |
399 | dma_params->data_type = 2; | |
400 | mcbsp_word_length = DAVINCI_MCBSP_WORD_16; | |
401 | break; | |
402 | case SNDRV_PCM_FORMAT_S32_LE: | |
403 | dma_params->data_type = 4; | |
404 | mcbsp_word_length = DAVINCI_MCBSP_WORD_32; | |
405 | break; | |
406 | default: | |
9b6e12e4 | 407 | printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n"); |
310355c1 VB |
408 | return -EINVAL; |
409 | } | |
410 | ||
cb6e2063 | 411 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
35cf6358 TK |
412 | rcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG); |
413 | rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | | |
414 | DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); | |
415 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); | |
310355c1 | 416 | |
cb6e2063 | 417 | } else { |
35cf6358 TK |
418 | xcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG); |
419 | xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) | | |
420 | DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length); | |
421 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); | |
310355c1 | 422 | |
cb6e2063 | 423 | } |
310355c1 VB |
424 | return 0; |
425 | } | |
426 | ||
dee89c4d MB |
427 | static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
428 | struct snd_soc_dai *dai) | |
310355c1 VB |
429 | { |
430 | int ret = 0; | |
431 | ||
432 | switch (cmd) { | |
433 | case SNDRV_PCM_TRIGGER_START: | |
434 | case SNDRV_PCM_TRIGGER_RESUME: | |
435 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
436 | davinci_mcbsp_start(substream); | |
437 | break; | |
438 | case SNDRV_PCM_TRIGGER_STOP: | |
439 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
440 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
441 | davinci_mcbsp_stop(substream); | |
442 | break; | |
443 | default: | |
444 | ret = -EINVAL; | |
445 | } | |
446 | ||
447 | return ret; | |
448 | } | |
449 | ||
bdb92876 | 450 | static int davinci_i2s_probe(struct platform_device *pdev, |
9cb132d7 | 451 | struct snd_soc_dai *dai) |
310355c1 VB |
452 | { |
453 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
87506549 | 454 | struct snd_soc_card *card = socdev->card; |
a62114cb | 455 | struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai; |
310355c1 VB |
456 | struct davinci_mcbsp_dev *dev; |
457 | struct resource *mem, *ioarea; | |
458 | struct evm_snd_platform_data *pdata; | |
459 | int ret; | |
460 | ||
461 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
462 | if (!mem) { | |
463 | dev_err(&pdev->dev, "no mem resource?\n"); | |
464 | return -ENODEV; | |
465 | } | |
466 | ||
467 | ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1, | |
468 | pdev->name); | |
469 | if (!ioarea) { | |
470 | dev_err(&pdev->dev, "McBSP region already claimed\n"); | |
471 | return -EBUSY; | |
472 | } | |
473 | ||
474 | dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL); | |
475 | if (!dev) { | |
476 | ret = -ENOMEM; | |
477 | goto err_release_region; | |
478 | } | |
479 | ||
480 | cpu_dai->private_data = dev; | |
481 | ||
a62114cb | 482 | dev->clk = clk_get(&pdev->dev, NULL); |
310355c1 VB |
483 | if (IS_ERR(dev->clk)) { |
484 | ret = -ENODEV; | |
485 | goto err_free_mem; | |
486 | } | |
487 | clk_enable(dev->clk); | |
488 | ||
489 | dev->base = (void __iomem *)IO_ADDRESS(mem->start); | |
490 | pdata = pdev->dev.platform_data; | |
491 | ||
492 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out; | |
493 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch; | |
494 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr = | |
495 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG); | |
496 | ||
497 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in; | |
498 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch; | |
499 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr = | |
500 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG); | |
501 | ||
502 | return 0; | |
503 | ||
504 | err_free_mem: | |
505 | kfree(dev); | |
506 | err_release_region: | |
507 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
508 | ||
509 | return ret; | |
510 | } | |
511 | ||
bdb92876 | 512 | static void davinci_i2s_remove(struct platform_device *pdev, |
9cb132d7 | 513 | struct snd_soc_dai *dai) |
310355c1 VB |
514 | { |
515 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
87506549 | 516 | struct snd_soc_card *card = socdev->card; |
a62114cb | 517 | struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai; |
310355c1 VB |
518 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; |
519 | struct resource *mem; | |
520 | ||
521 | clk_disable(dev->clk); | |
522 | clk_put(dev->clk); | |
523 | dev->clk = NULL; | |
524 | ||
525 | kfree(dev); | |
526 | ||
527 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
528 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
529 | } | |
530 | ||
531 | #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 | |
532 | ||
6335d055 EM |
533 | static struct snd_soc_dai_ops davinci_i2s_dai_ops = { |
534 | .startup = davinci_i2s_startup, | |
535 | .trigger = davinci_i2s_trigger, | |
536 | .hw_params = davinci_i2s_hw_params, | |
537 | .set_fmt = davinci_i2s_set_dai_fmt, | |
538 | }; | |
539 | ||
9cb132d7 | 540 | struct snd_soc_dai davinci_i2s_dai = { |
310355c1 VB |
541 | .name = "davinci-i2s", |
542 | .id = 0, | |
310355c1 VB |
543 | .probe = davinci_i2s_probe, |
544 | .remove = davinci_i2s_remove, | |
545 | .playback = { | |
546 | .channels_min = 2, | |
547 | .channels_max = 2, | |
548 | .rates = DAVINCI_I2S_RATES, | |
549 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
550 | .capture = { | |
551 | .channels_min = 2, | |
552 | .channels_max = 2, | |
553 | .rates = DAVINCI_I2S_RATES, | |
554 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
6335d055 | 555 | .ops = &davinci_i2s_dai_ops, |
310355c1 VB |
556 | }; |
557 | EXPORT_SYMBOL_GPL(davinci_i2s_dai); | |
558 | ||
c9b3a40f | 559 | static int __init davinci_i2s_init(void) |
3f4b783c MB |
560 | { |
561 | return snd_soc_register_dai(&davinci_i2s_dai); | |
562 | } | |
563 | module_init(davinci_i2s_init); | |
564 | ||
565 | static void __exit davinci_i2s_exit(void) | |
566 | { | |
567 | snd_soc_unregister_dai(&davinci_i2s_dai); | |
568 | } | |
569 | module_exit(davinci_i2s_exit); | |
570 | ||
310355c1 VB |
571 | MODULE_AUTHOR("Vladimir Barinov"); |
572 | MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface"); | |
573 | MODULE_LICENSE("GPL"); |