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310355c1 VB |
1 | /* |
2 | * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor | |
3 | * | |
d6b52039 | 4 | * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> |
310355c1 VB |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/clk.h> | |
18 | ||
19 | #include <sound/core.h> | |
20 | #include <sound/pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/initval.h> | |
23 | #include <sound/soc.h> | |
24 | ||
ff7d04b1 MB |
25 | #include <mach/asp.h> |
26 | ||
310355c1 VB |
27 | #include "davinci-pcm.h" |
28 | ||
a62114cb DB |
29 | |
30 | /* | |
31 | * NOTE: terminology here is confusing. | |
32 | * | |
33 | * - This driver supports the "Audio Serial Port" (ASP), | |
34 | * found on dm6446, dm355, and other DaVinci chips. | |
35 | * | |
36 | * - But it labels it a "Multi-channel Buffered Serial Port" | |
37 | * (McBSP) as on older chips like the dm642 ... which was | |
38 | * backward-compatible, possibly explaining that confusion. | |
39 | * | |
40 | * - OMAP chips have a controller called McBSP, which is | |
41 | * incompatible with the DaVinci flavor of McBSP. | |
42 | * | |
43 | * - Newer DaVinci chips have a controller called McASP, | |
44 | * incompatible with ASP and with either McBSP. | |
45 | * | |
46 | * In short: this uses ASP to implement I2S, not McBSP. | |
47 | * And it won't be the only DaVinci implemention of I2S. | |
48 | */ | |
310355c1 VB |
49 | #define DAVINCI_MCBSP_DRR_REG 0x00 |
50 | #define DAVINCI_MCBSP_DXR_REG 0x04 | |
51 | #define DAVINCI_MCBSP_SPCR_REG 0x08 | |
52 | #define DAVINCI_MCBSP_RCR_REG 0x0c | |
53 | #define DAVINCI_MCBSP_XCR_REG 0x10 | |
54 | #define DAVINCI_MCBSP_SRGR_REG 0x14 | |
55 | #define DAVINCI_MCBSP_PCR_REG 0x24 | |
56 | ||
57 | #define DAVINCI_MCBSP_SPCR_RRST (1 << 0) | |
58 | #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4) | |
59 | #define DAVINCI_MCBSP_SPCR_XRST (1 << 16) | |
60 | #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20) | |
61 | #define DAVINCI_MCBSP_SPCR_GRST (1 << 22) | |
62 | #define DAVINCI_MCBSP_SPCR_FRST (1 << 23) | |
63 | #define DAVINCI_MCBSP_SPCR_FREE (1 << 25) | |
64 | ||
65 | #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5) | |
66 | #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8) | |
67 | #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) | |
f5cfa954 | 68 | #define DAVINCI_MCBSP_RCR_RFIG (1 << 18) |
310355c1 VB |
69 | #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) |
70 | ||
71 | #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) | |
72 | #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) | |
73 | #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) | |
74 | #define DAVINCI_MCBSP_XCR_XFIG (1 << 18) | |
75 | #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) | |
76 | ||
77 | #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) | |
78 | #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) | |
79 | #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) | |
80 | ||
81 | #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) | |
82 | #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) | |
83 | #define DAVINCI_MCBSP_PCR_FSRP (1 << 2) | |
84 | #define DAVINCI_MCBSP_PCR_FSXP (1 << 3) | |
b402dff8 | 85 | #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7) |
310355c1 VB |
86 | #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8) |
87 | #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9) | |
88 | #define DAVINCI_MCBSP_PCR_FSRM (1 << 10) | |
89 | #define DAVINCI_MCBSP_PCR_FSXM (1 << 11) | |
90 | ||
310355c1 VB |
91 | enum { |
92 | DAVINCI_MCBSP_WORD_8 = 0, | |
93 | DAVINCI_MCBSP_WORD_12, | |
94 | DAVINCI_MCBSP_WORD_16, | |
95 | DAVINCI_MCBSP_WORD_20, | |
96 | DAVINCI_MCBSP_WORD_24, | |
97 | DAVINCI_MCBSP_WORD_32, | |
98 | }; | |
99 | ||
0d6c9774 TK |
100 | static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = { |
101 | [SNDRV_PCM_FORMAT_S8] = 1, | |
102 | [SNDRV_PCM_FORMAT_S16_LE] = 2, | |
103 | [SNDRV_PCM_FORMAT_S32_LE] = 4, | |
104 | }; | |
105 | ||
106 | static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = { | |
107 | [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8, | |
108 | [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16, | |
109 | [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32, | |
110 | }; | |
111 | ||
112 | static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = { | |
113 | [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE, | |
114 | [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE, | |
115 | }; | |
116 | ||
310355c1 | 117 | struct davinci_mcbsp_dev { |
92e2a6f6 | 118 | struct davinci_pcm_dma_params dma_params[2]; |
310355c1 | 119 | void __iomem *base; |
f5cfa954 TK |
120 | #define MOD_DSP_A 0 |
121 | #define MOD_DSP_B 1 | |
122 | int mode; | |
c392bec7 | 123 | u32 pcr; |
310355c1 | 124 | struct clk *clk; |
0d6c9774 TK |
125 | /* |
126 | * Combining both channels into 1 element will at least double the | |
127 | * amount of time between servicing the dma channel, increase | |
128 | * effiency, and reduce the chance of overrun/underrun. But, | |
129 | * it will result in the left & right channels being swapped. | |
130 | * | |
131 | * If relabeling the left and right channels is not possible, | |
132 | * you may want to let the codec know to swap them back. | |
133 | * | |
134 | * It may allow x10 the amount of time to service dma requests, | |
135 | * if the codec is master and is using an unnecessarily fast bit clock | |
136 | * (ie. tlvaic23b), independent of the sample rate. So, having an | |
137 | * entire frame at once means it can be serviced at the sample rate | |
138 | * instead of the bit clock rate. | |
139 | * | |
140 | * In the now unlikely case that an underrun still | |
141 | * occurs, both the left and right samples will be repeated | |
142 | * so that no pops are heard, and the left and right channels | |
143 | * won't end up being swapped because of the underrun. | |
144 | */ | |
145 | unsigned enable_channel_combine:1; | |
310355c1 VB |
146 | }; |
147 | ||
148 | static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, | |
149 | int reg, u32 val) | |
150 | { | |
151 | __raw_writel(val, dev->base + reg); | |
152 | } | |
153 | ||
154 | static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg) | |
155 | { | |
156 | return __raw_readl(dev->base + reg); | |
157 | } | |
158 | ||
c392bec7 TK |
159 | static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback) |
160 | { | |
161 | u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP; | |
162 | /* The clock needs to toggle to complete reset. | |
163 | * So, fake it by toggling the clk polarity. | |
164 | */ | |
165 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m); | |
166 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr); | |
167 | } | |
168 | ||
f9af37cc TK |
169 | static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev, |
170 | struct snd_pcm_substream *substream) | |
310355c1 VB |
171 | { |
172 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
fb0ef645 | 173 | struct snd_soc_device *socdev = rtd->socdev; |
87689d56 | 174 | struct snd_soc_platform *platform = socdev->card->platform; |
c392bec7 | 175 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
35cf6358 | 176 | u32 spcr; |
c392bec7 | 177 | u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 178 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
c392bec7 TK |
179 | if (spcr & mask) { |
180 | /* start off disabled */ | |
181 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, | |
182 | spcr & ~mask); | |
183 | toggle_clock(dev, playback); | |
184 | } | |
1bef4499 TK |
185 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM | |
186 | DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) { | |
187 | /* Start the sample generator */ | |
188 | spcr |= DAVINCI_MCBSP_SPCR_GRST; | |
189 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
190 | } | |
fb0ef645 | 191 | |
1bef4499 | 192 | if (playback) { |
fb0ef645 NM |
193 | /* Stop the DMA to avoid data loss */ |
194 | /* while the transmitter is out of reset to handle XSYNCERR */ | |
195 | if (platform->pcm_ops->trigger) { | |
eba575c3 | 196 | int ret = platform->pcm_ops->trigger(substream, |
fb0ef645 NM |
197 | SNDRV_PCM_TRIGGER_STOP); |
198 | if (ret < 0) | |
199 | printk(KERN_DEBUG "Playback DMA stop failed\n"); | |
200 | } | |
201 | ||
202 | /* Enable the transmitter */ | |
35cf6358 TK |
203 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
204 | spcr |= DAVINCI_MCBSP_SPCR_XRST; | |
205 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
fb0ef645 NM |
206 | |
207 | /* wait for any unexpected frame sync error to occur */ | |
208 | udelay(100); | |
209 | ||
210 | /* Disable the transmitter to clear any outstanding XSYNCERR */ | |
35cf6358 TK |
211 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
212 | spcr &= ~DAVINCI_MCBSP_SPCR_XRST; | |
213 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
c392bec7 | 214 | toggle_clock(dev, playback); |
fb0ef645 NM |
215 | |
216 | /* Restart the DMA */ | |
217 | if (platform->pcm_ops->trigger) { | |
eba575c3 | 218 | int ret = platform->pcm_ops->trigger(substream, |
fb0ef645 NM |
219 | SNDRV_PCM_TRIGGER_START); |
220 | if (ret < 0) | |
221 | printk(KERN_DEBUG "Playback DMA start failed\n"); | |
222 | } | |
fb0ef645 NM |
223 | } |
224 | ||
1bef4499 | 225 | /* Enable transmitter or receiver */ |
35cf6358 | 226 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
1bef4499 TK |
227 | spcr |= mask; |
228 | ||
229 | if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) { | |
230 | /* Start frame sync */ | |
231 | spcr |= DAVINCI_MCBSP_SPCR_FRST; | |
232 | } | |
35cf6358 | 233 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
310355c1 VB |
234 | } |
235 | ||
f9af37cc | 236 | static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback) |
310355c1 | 237 | { |
35cf6358 | 238 | u32 spcr; |
310355c1 VB |
239 | |
240 | /* Reset transmitter/receiver and sample rate/frame sync generators */ | |
35cf6358 TK |
241 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
242 | spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST); | |
c392bec7 | 243 | spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST; |
35cf6358 | 244 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); |
c392bec7 | 245 | toggle_clock(dev, playback); |
310355c1 VB |
246 | } |
247 | ||
21903c1c TK |
248 | #define DEFAULT_BITPERSAMPLE 16 |
249 | ||
9cb132d7 | 250 | static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
310355c1 VB |
251 | unsigned int fmt) |
252 | { | |
253 | struct davinci_mcbsp_dev *dev = cpu_dai->private_data; | |
21903c1c TK |
254 | unsigned int pcr; |
255 | unsigned int srgr; | |
21903c1c TK |
256 | srgr = DAVINCI_MCBSP_SRGR_FSGM | |
257 | DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | | |
258 | DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); | |
310355c1 | 259 | |
f5cfa954 | 260 | /* set master/slave audio interface */ |
310355c1 VB |
261 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
262 | case SND_SOC_DAIFMT_CBS_CFS: | |
21903c1c TK |
263 | /* cpu is master */ |
264 | pcr = DAVINCI_MCBSP_PCR_FSXM | | |
265 | DAVINCI_MCBSP_PCR_FSRM | | |
266 | DAVINCI_MCBSP_PCR_CLKXM | | |
267 | DAVINCI_MCBSP_PCR_CLKRM; | |
310355c1 | 268 | break; |
b402dff8 HV |
269 | case SND_SOC_DAIFMT_CBM_CFS: |
270 | /* McBSP CLKR pin is the input for the Sample Rate Generator. | |
271 | * McBSP FSR and FSX are driven by the Sample Rate Generator. */ | |
21903c1c TK |
272 | pcr = DAVINCI_MCBSP_PCR_SCLKME | |
273 | DAVINCI_MCBSP_PCR_FSXM | | |
274 | DAVINCI_MCBSP_PCR_FSRM; | |
b402dff8 | 275 | break; |
310355c1 | 276 | case SND_SOC_DAIFMT_CBM_CFM: |
21903c1c TK |
277 | /* codec is master */ |
278 | pcr = 0; | |
310355c1 VB |
279 | break; |
280 | default: | |
21903c1c | 281 | printk(KERN_ERR "%s:bad master\n", __func__); |
310355c1 VB |
282 | return -EINVAL; |
283 | } | |
284 | ||
f5cfa954 | 285 | /* interface format */ |
69ab820c | 286 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
69ab820c | 287 | case SND_SOC_DAIFMT_I2S: |
07d8d9dc TK |
288 | /* Davinci doesn't support TRUE I2S, but some codecs will have |
289 | * the left and right channels contiguous. This allows | |
290 | * dsp_a mode to be used with an inverted normal frame clk. | |
291 | * If your codec is master and does not have contiguous | |
292 | * channels, then you will have sound on only one channel. | |
293 | * Try using a different mode, or codec as slave. | |
294 | * | |
295 | * The TLV320AIC33 is an example of a codec where this works. | |
296 | * It has a variable bit clock frequency allowing it to have | |
297 | * valid data on every bit clock. | |
298 | * | |
299 | * The TLV320AIC23 is an example of a codec where this does not | |
300 | * work. It has a fixed bit clock frequency with progressively | |
301 | * more empty bit clock slots between channels as the sample | |
302 | * rate is lowered. | |
303 | */ | |
304 | fmt ^= SND_SOC_DAIFMT_NB_IF; | |
305 | case SND_SOC_DAIFMT_DSP_A: | |
f5cfa954 TK |
306 | dev->mode = MOD_DSP_A; |
307 | break; | |
308 | case SND_SOC_DAIFMT_DSP_B: | |
309 | dev->mode = MOD_DSP_B; | |
69ab820c TK |
310 | break; |
311 | default: | |
312 | printk(KERN_ERR "%s:bad format\n", __func__); | |
313 | return -EINVAL; | |
314 | } | |
315 | ||
310355c1 | 316 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
9e031624 | 317 | case SND_SOC_DAIFMT_NB_NF: |
664b4af8 TK |
318 | /* CLKRP Receive clock polarity, |
319 | * 1 - sampled on rising edge of CLKR | |
320 | * valid on rising edge | |
321 | * CLKXP Transmit clock polarity, | |
322 | * 1 - clocked on falling edge of CLKX | |
323 | * valid on rising edge | |
324 | * FSRP Receive frame sync pol, 0 - active high | |
325 | * FSXP Transmit frame sync pol, 0 - active high | |
326 | */ | |
21903c1c | 327 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP); |
310355c1 | 328 | break; |
9e031624 | 329 | case SND_SOC_DAIFMT_IB_IF: |
664b4af8 TK |
330 | /* CLKRP Receive clock polarity, |
331 | * 0 - sampled on falling edge of CLKR | |
332 | * valid on falling edge | |
333 | * CLKXP Transmit clock polarity, | |
334 | * 0 - clocked on rising edge of CLKX | |
335 | * valid on falling edge | |
336 | * FSRP Receive frame sync pol, 1 - active low | |
337 | * FSXP Transmit frame sync pol, 1 - active low | |
338 | */ | |
21903c1c | 339 | pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); |
310355c1 | 340 | break; |
9e031624 | 341 | case SND_SOC_DAIFMT_NB_IF: |
664b4af8 TK |
342 | /* CLKRP Receive clock polarity, |
343 | * 1 - sampled on rising edge of CLKR | |
344 | * valid on rising edge | |
345 | * CLKXP Transmit clock polarity, | |
346 | * 1 - clocked on falling edge of CLKX | |
347 | * valid on rising edge | |
348 | * FSRP Receive frame sync pol, 1 - active low | |
349 | * FSXP Transmit frame sync pol, 1 - active low | |
350 | */ | |
21903c1c TK |
351 | pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP | |
352 | DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); | |
310355c1 | 353 | break; |
9e031624 | 354 | case SND_SOC_DAIFMT_IB_NF: |
664b4af8 TK |
355 | /* CLKRP Receive clock polarity, |
356 | * 0 - sampled on falling edge of CLKR | |
357 | * valid on falling edge | |
358 | * CLKXP Transmit clock polarity, | |
359 | * 0 - clocked on rising edge of CLKX | |
360 | * valid on falling edge | |
361 | * FSRP Receive frame sync pol, 0 - active high | |
362 | * FSXP Transmit frame sync pol, 0 - active high | |
363 | */ | |
310355c1 VB |
364 | break; |
365 | default: | |
366 | return -EINVAL; | |
367 | } | |
21903c1c | 368 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); |
c392bec7 | 369 | dev->pcr = pcr; |
21903c1c | 370 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr); |
310355c1 VB |
371 | return 0; |
372 | } | |
373 | ||
374 | static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
375 | struct snd_pcm_hw_params *params, |
376 | struct snd_soc_dai *dai) | |
310355c1 | 377 | { |
9bb74150 | 378 | struct davinci_mcbsp_dev *dev = dai->private_data; |
81ac55aa | 379 | struct davinci_pcm_dma_params *dma_params = |
92e2a6f6 | 380 | &dev->dma_params[substream->stream]; |
310355c1 VB |
381 | struct snd_interval *i = NULL; |
382 | int mcbsp_word_length; | |
35cf6358 TK |
383 | unsigned int rcr, xcr, srgr; |
384 | u32 spcr; | |
0d6c9774 TK |
385 | snd_pcm_format_t fmt; |
386 | unsigned element_cnt = 1; | |
310355c1 VB |
387 | |
388 | /* general line settings */ | |
35cf6358 | 389 | spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); |
cb6e2063 | 390 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
35cf6358 TK |
391 | spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
392 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 393 | } else { |
35cf6358 TK |
394 | spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE; |
395 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); | |
cb6e2063 | 396 | } |
310355c1 VB |
397 | |
398 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); | |
35cf6358 TK |
399 | srgr = DAVINCI_MCBSP_SRGR_FSGM; |
400 | srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); | |
310355c1 VB |
401 | |
402 | i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); | |
35cf6358 TK |
403 | srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); |
404 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); | |
310355c1 | 405 | |
f5cfa954 TK |
406 | rcr = DAVINCI_MCBSP_RCR_RFIG; |
407 | xcr = DAVINCI_MCBSP_XCR_XFIG; | |
408 | if (dev->mode == MOD_DSP_B) { | |
409 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0); | |
410 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0); | |
411 | } else { | |
412 | rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1); | |
413 | xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1); | |
414 | } | |
310355c1 | 415 | /* Determine xfer data type */ |
0d6c9774 TK |
416 | fmt = params_format(params); |
417 | if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) { | |
9b6e12e4 | 418 | printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n"); |
310355c1 VB |
419 | return -EINVAL; |
420 | } | |
421 | ||
0d6c9774 TK |
422 | if (params_channels(params) == 2) { |
423 | element_cnt = 2; | |
424 | if (double_fmt[fmt] && dev->enable_channel_combine) { | |
425 | element_cnt = 1; | |
426 | fmt = double_fmt[fmt]; | |
427 | } | |
428 | } | |
429 | dma_params->acnt = dma_params->data_type = data_type[fmt]; | |
4fa9c1a5 | 430 | dma_params->fifo_level = 0; |
0d6c9774 TK |
431 | mcbsp_word_length = asp_word_length[fmt]; |
432 | rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1); | |
433 | xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1); | |
310355c1 | 434 | |
f5cfa954 TK |
435 | rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | |
436 | DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); | |
437 | xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) | | |
438 | DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length); | |
310355c1 | 439 | |
f5cfa954 TK |
440 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
441 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); | |
442 | else | |
443 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); | |
310355c1 VB |
444 | return 0; |
445 | } | |
446 | ||
af0adf3e TK |
447 | static int davinci_i2s_prepare(struct snd_pcm_substream *substream, |
448 | struct snd_soc_dai *dai) | |
449 | { | |
9bb74150 | 450 | struct davinci_mcbsp_dev *dev = dai->private_data; |
af0adf3e TK |
451 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
452 | davinci_mcbsp_stop(dev, playback); | |
453 | if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) { | |
454 | /* codec is master */ | |
455 | davinci_mcbsp_start(dev, substream); | |
456 | } | |
457 | return 0; | |
458 | } | |
459 | ||
dee89c4d MB |
460 | static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
461 | struct snd_soc_dai *dai) | |
310355c1 | 462 | { |
9bb74150 | 463 | struct davinci_mcbsp_dev *dev = dai->private_data; |
310355c1 | 464 | int ret = 0; |
f9af37cc | 465 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
af0adf3e TK |
466 | if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) |
467 | return 0; /* return if codec is master */ | |
310355c1 VB |
468 | |
469 | switch (cmd) { | |
470 | case SNDRV_PCM_TRIGGER_START: | |
471 | case SNDRV_PCM_TRIGGER_RESUME: | |
472 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
f9af37cc | 473 | davinci_mcbsp_start(dev, substream); |
310355c1 VB |
474 | break; |
475 | case SNDRV_PCM_TRIGGER_STOP: | |
476 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
477 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
f9af37cc | 478 | davinci_mcbsp_stop(dev, playback); |
310355c1 VB |
479 | break; |
480 | default: | |
481 | ret = -EINVAL; | |
482 | } | |
310355c1 VB |
483 | return ret; |
484 | } | |
485 | ||
af0adf3e TK |
486 | static void davinci_i2s_shutdown(struct snd_pcm_substream *substream, |
487 | struct snd_soc_dai *dai) | |
488 | { | |
9bb74150 | 489 | struct davinci_mcbsp_dev *dev = dai->private_data; |
af0adf3e TK |
490 | int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
491 | davinci_mcbsp_stop(dev, playback); | |
492 | } | |
493 | ||
5204d496 C |
494 | #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 |
495 | ||
496 | static struct snd_soc_dai_ops davinci_i2s_dai_ops = { | |
3f405b46 MB |
497 | .shutdown = davinci_i2s_shutdown, |
498 | .prepare = davinci_i2s_prepare, | |
5204d496 C |
499 | .trigger = davinci_i2s_trigger, |
500 | .hw_params = davinci_i2s_hw_params, | |
501 | .set_fmt = davinci_i2s_set_dai_fmt, | |
502 | ||
503 | }; | |
504 | ||
505 | struct snd_soc_dai davinci_i2s_dai = { | |
506 | .name = "davinci-i2s", | |
507 | .id = 0, | |
508 | .playback = { | |
509 | .channels_min = 2, | |
510 | .channels_max = 2, | |
511 | .rates = DAVINCI_I2S_RATES, | |
512 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
513 | .capture = { | |
514 | .channels_min = 2, | |
515 | .channels_max = 2, | |
516 | .rates = DAVINCI_I2S_RATES, | |
517 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
518 | .ops = &davinci_i2s_dai_ops, | |
519 | ||
520 | }; | |
521 | EXPORT_SYMBOL_GPL(davinci_i2s_dai); | |
522 | ||
523 | static int davinci_i2s_probe(struct platform_device *pdev) | |
310355c1 | 524 | { |
5204d496 | 525 | struct snd_platform_data *pdata = pdev->dev.platform_data; |
310355c1 | 526 | struct davinci_mcbsp_dev *dev; |
5204d496 | 527 | struct resource *mem, *ioarea, *res; |
310355c1 VB |
528 | int ret; |
529 | ||
530 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
531 | if (!mem) { | |
532 | dev_err(&pdev->dev, "no mem resource?\n"); | |
533 | return -ENODEV; | |
534 | } | |
535 | ||
536 | ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1, | |
537 | pdev->name); | |
538 | if (!ioarea) { | |
539 | dev_err(&pdev->dev, "McBSP region already claimed\n"); | |
540 | return -EBUSY; | |
541 | } | |
542 | ||
543 | dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL); | |
544 | if (!dev) { | |
545 | ret = -ENOMEM; | |
546 | goto err_release_region; | |
547 | } | |
1e224f32 | 548 | if (pdata) { |
0d6c9774 | 549 | dev->enable_channel_combine = pdata->enable_channel_combine; |
1e224f32 TK |
550 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size = |
551 | pdata->sram_size_playback; | |
552 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size = | |
553 | pdata->sram_size_capture; | |
554 | } | |
3e46a447 | 555 | dev->clk = clk_get(&pdev->dev, NULL); |
310355c1 VB |
556 | if (IS_ERR(dev->clk)) { |
557 | ret = -ENODEV; | |
558 | goto err_free_mem; | |
559 | } | |
560 | clk_enable(dev->clk); | |
561 | ||
562 | dev->base = (void __iomem *)IO_ADDRESS(mem->start); | |
310355c1 | 563 | |
92e2a6f6 | 564 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr = |
310355c1 VB |
565 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG); |
566 | ||
92e2a6f6 | 567 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr = |
310355c1 VB |
568 | (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG); |
569 | ||
5204d496 C |
570 | /* first TX, then RX */ |
571 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
572 | if (!res) { | |
573 | dev_err(&pdev->dev, "no DMA resource\n"); | |
efd13be0 | 574 | ret = -ENXIO; |
5204d496 C |
575 | goto err_free_mem; |
576 | } | |
92e2a6f6 | 577 | dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start; |
5204d496 C |
578 | |
579 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
580 | if (!res) { | |
581 | dev_err(&pdev->dev, "no DMA resource\n"); | |
efd13be0 | 582 | ret = -ENXIO; |
5204d496 C |
583 | goto err_free_mem; |
584 | } | |
92e2a6f6 | 585 | dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start; |
5204d496 C |
586 | |
587 | davinci_i2s_dai.private_data = dev; | |
57512c64 | 588 | davinci_i2s_dai.dma_data = dev->dma_params; |
5204d496 C |
589 | ret = snd_soc_register_dai(&davinci_i2s_dai); |
590 | if (ret != 0) | |
591 | goto err_free_mem; | |
592 | ||
310355c1 VB |
593 | return 0; |
594 | ||
595 | err_free_mem: | |
596 | kfree(dev); | |
597 | err_release_region: | |
598 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
599 | ||
600 | return ret; | |
601 | } | |
602 | ||
5204d496 | 603 | static int davinci_i2s_remove(struct platform_device *pdev) |
310355c1 | 604 | { |
5204d496 | 605 | struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data; |
310355c1 VB |
606 | struct resource *mem; |
607 | ||
5204d496 | 608 | snd_soc_unregister_dai(&davinci_i2s_dai); |
310355c1 VB |
609 | clk_disable(dev->clk); |
610 | clk_put(dev->clk); | |
611 | dev->clk = NULL; | |
310355c1 | 612 | kfree(dev); |
310355c1 VB |
613 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
614 | release_mem_region(mem->start, (mem->end - mem->start) + 1); | |
310355c1 | 615 | |
5204d496 C |
616 | return 0; |
617 | } | |
6335d055 | 618 | |
5204d496 C |
619 | static struct platform_driver davinci_mcbsp_driver = { |
620 | .probe = davinci_i2s_probe, | |
621 | .remove = davinci_i2s_remove, | |
622 | .driver = { | |
623 | .name = "davinci-asp", | |
624 | .owner = THIS_MODULE, | |
625 | }, | |
310355c1 | 626 | }; |
310355c1 | 627 | |
c9b3a40f | 628 | static int __init davinci_i2s_init(void) |
3f4b783c | 629 | { |
5204d496 | 630 | return platform_driver_register(&davinci_mcbsp_driver); |
3f4b783c MB |
631 | } |
632 | module_init(davinci_i2s_init); | |
633 | ||
634 | static void __exit davinci_i2s_exit(void) | |
635 | { | |
5204d496 | 636 | platform_driver_unregister(&davinci_mcbsp_driver); |
3f4b783c MB |
637 | } |
638 | module_exit(davinci_i2s_exit); | |
639 | ||
310355c1 VB |
640 | MODULE_AUTHOR("Vladimir Barinov"); |
641 | MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface"); | |
642 | MODULE_LICENSE("GPL"); |