[deliverable/linux.git] / sound / soc / davinci / davinci-i2s.c

/*
 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
 *
 * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
 * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include "davinci-pcm.h"


/*
 * NOTE:  terminology here is confusing.
 *
 *  - This driver supports the "Audio Serial Port" (ASP),
 *    found on dm6446, dm355, and other DaVinci chips.
 *
 *  - But it labels it a "Multi-channel Buffered Serial Port"
 *    (McBSP) as on older chips like the dm642 ... which was
 *    backward-compatible, possibly explaining that confusion.
 *
 *  - OMAP chips have a controller called McBSP, which is
 *    incompatible with the DaVinci flavor of McBSP.
 *
 *  - Newer DaVinci chips have a controller called McASP,
 *    incompatible with ASP and with either McBSP.
 *
 * In short:  this uses ASP to implement I2S, not McBSP.
 * And it won't be the only DaVinci implemention of I2S.
 */
#define DAVINCI_MCBSP_DRR_REG	0x00
#define DAVINCI_MCBSP_DXR_REG	0x04
#define DAVINCI_MCBSP_SPCR_REG	0x08
#define DAVINCI_MCBSP_RCR_REG	0x0c
#define DAVINCI_MCBSP_XCR_REG	0x10
#define DAVINCI_MCBSP_SRGR_REG	0x14
#define DAVINCI_MCBSP_PCR_REG	0x24

#define DAVINCI_MCBSP_SPCR_RRST		(1 << 0)
#define DAVINCI_MCBSP_SPCR_RINTM(v)	((v) << 4)
#define DAVINCI_MCBSP_SPCR_XRST		(1 << 16)
#define DAVINCI_MCBSP_SPCR_XINTM(v)	((v) << 20)
#define DAVINCI_MCBSP_SPCR_GRST		(1 << 22)
#define DAVINCI_MCBSP_SPCR_FRST		(1 << 23)
#define DAVINCI_MCBSP_SPCR_FREE		(1 << 25)

#define DAVINCI_MCBSP_RCR_RWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_RCR_RFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_RCR_RDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_RCR_RWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_XCR_XWDLEN1(v)	((v) << 5)
#define DAVINCI_MCBSP_XCR_XFRLEN1(v)	((v) << 8)
#define DAVINCI_MCBSP_XCR_XDATDLY(v)	((v) << 16)
#define DAVINCI_MCBSP_XCR_XFIG		(1 << 18)
#define DAVINCI_MCBSP_XCR_XWDLEN2(v)	((v) << 21)

#define DAVINCI_MCBSP_SRGR_FWID(v)	((v) << 8)
#define DAVINCI_MCBSP_SRGR_FPER(v)	((v) << 16)
#define DAVINCI_MCBSP_SRGR_FSGM		(1 << 28)

#define DAVINCI_MCBSP_PCR_CLKRP		(1 << 0)
#define DAVINCI_MCBSP_PCR_CLKXP		(1 << 1)
#define DAVINCI_MCBSP_PCR_FSRP		(1 << 2)
#define DAVINCI_MCBSP_PCR_FSXP		(1 << 3)
#define DAVINCI_MCBSP_PCR_SCLKME	(1 << 7)
#define DAVINCI_MCBSP_PCR_CLKRM		(1 << 8)
#define DAVINCI_MCBSP_PCR_CLKXM		(1 << 9)
#define DAVINCI_MCBSP_PCR_FSRM		(1 << 10)
#define DAVINCI_MCBSP_PCR_FSXM		(1 << 11)

enum {
	DAVINCI_MCBSP_WORD_8 = 0,
	DAVINCI_MCBSP_WORD_12,
	DAVINCI_MCBSP_WORD_16,
	DAVINCI_MCBSP_WORD_20,
	DAVINCI_MCBSP_WORD_24,
	DAVINCI_MCBSP_WORD_32,
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	.name = "I2S PCM Stereo out",
};

static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	.name = "I2S PCM Stereo in",
};

struct davinci_mcbsp_dev {
	void __iomem			*base;
	u32				pcr;
	struct clk			*clk;
	struct davinci_pcm_dma_params	*dma_params[2];
};

static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
					   int reg, u32 val)
{
	__raw_writel(val, dev->base + reg);
}

static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
{
	return __raw_readl(dev->base + reg);
}

static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
{
	u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
	/* The clock needs to toggle to complete reset.
	 * So, fake it by toggling the clk polarity.
	 */
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
}

static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
		struct snd_pcm_substream *substream)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_device *socdev = rtd->socdev;
	struct snd_soc_platform *platform = socdev->card->platform;
	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
	u32 spcr;
	u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	if (spcr & mask) {
		/* start off disabled */
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
				spcr & ~mask);
		toggle_clock(dev, playback);
	}
	/* Start the sample generator and enable transmitter/receiver */
	spcr |= DAVINCI_MCBSP_SPCR_GRST;
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		/* Stop the DMA to avoid data loss */
		/* while the transmitter is out of reset to handle XSYNCERR */
		if (platform->pcm_ops->trigger) {
			int ret = platform->pcm_ops->trigger(substream,
				SNDRV_PCM_TRIGGER_STOP);
			if (ret < 0)
				printk(KERN_DEBUG "Playback DMA stop failed\n");
		}

		/* Enable the transmitter */
		spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		spcr |= DAVINCI_MCBSP_SPCR_XRST;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);

		/* wait for any unexpected frame sync error to occur */
		udelay(100);

		/* Disable the transmitter to clear any outstanding XSYNCERR */
		spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
		toggle_clock(dev, playback);

		/* Restart the DMA */
		if (platform->pcm_ops->trigger) {
			int ret = platform->pcm_ops->trigger(substream,
				SNDRV_PCM_TRIGGER_START);
			if (ret < 0)
				printk(KERN_DEBUG "Playback DMA start failed\n");
		}
		/* Enable the transmitter */
		spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		spcr |= DAVINCI_MCBSP_SPCR_XRST;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);

	} else {

		/* Enable the reciever */
		spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
		spcr |= DAVINCI_MCBSP_SPCR_RRST;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
	}


	/* Start frame sync */
	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	spcr |= DAVINCI_MCBSP_SPCR_FRST;
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
}

static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
{
	u32 spcr;

	/* Reset transmitter/receiver and sample rate/frame sync generators */
	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
	spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
	toggle_clock(dev, playback);
}

static int davinci_i2s_startup(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;

	cpu_dai->dma_data = dev->dma_params[substream->stream];

	return 0;
}

#define DEFAULT_BITPERSAMPLE	16

static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				   unsigned int fmt)
{
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	unsigned int pcr;
	unsigned int srgr;
	unsigned int rcr;
	unsigned int xcr;
	srgr = DAVINCI_MCBSP_SRGR_FSGM |
		DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
		DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* cpu is master */
		pcr = DAVINCI_MCBSP_PCR_FSXM |
			DAVINCI_MCBSP_PCR_FSRM |
			DAVINCI_MCBSP_PCR_CLKXM |
			DAVINCI_MCBSP_PCR_CLKRM;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		/* McBSP CLKR pin is the input for the Sample Rate Generator.
		 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
		pcr = DAVINCI_MCBSP_PCR_SCLKME |
			DAVINCI_MCBSP_PCR_FSXM |
			DAVINCI_MCBSP_PCR_FSRM;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		/* codec is master */
		pcr = 0;
		break;
	default:
		printk(KERN_ERR "%s:bad master\n", __func__);
		return -EINVAL;
	}

	rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
	xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1);
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_DSP_B:
		break;
	case SND_SOC_DAIFMT_I2S:
		/* Davinci doesn't support TRUE I2S, but some codecs will have
		 * the left and right channels contiguous. This allows
		 * dsp_a mode to be used with an inverted normal frame clk.
		 * If your codec is master and does not have contiguous
		 * channels, then you will have sound on only one channel.
		 * Try using a different mode, or codec as slave.
		 *
		 * The TLV320AIC33 is an example of a codec where this works.
		 * It has a variable bit clock frequency allowing it to have
		 * valid data on every bit clock.
		 *
		 * The TLV320AIC23 is an example of a codec where this does not
		 * work. It has a fixed bit clock frequency with progressively
		 * more empty bit clock slots between channels as the sample
		 * rate is lowered.
		 */
		fmt ^= SND_SOC_DAIFMT_NB_IF;
	case SND_SOC_DAIFMT_DSP_A:
		rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
		xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
		break;
	default:
		printk(KERN_ERR "%s:bad format\n", __func__);
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		/* CLKRP Receive clock polarity,
		 *	1 - sampled on rising edge of CLKR
		 *	valid on rising edge
		 * CLKXP Transmit clock polarity,
		 *	1 - clocked on falling edge of CLKX
		 *	valid on rising edge
		 * FSRP  Receive frame sync pol, 0 - active high
		 * FSXP  Transmit frame sync pol, 0 - active high
		 */
		pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
		break;
	case SND_SOC_DAIFMT_IB_IF:
		/* CLKRP Receive clock polarity,
		 *	0 - sampled on falling edge of CLKR
		 *	valid on falling edge
		 * CLKXP Transmit clock polarity,
		 *	0 - clocked on rising edge of CLKX
		 *	valid on falling edge
		 * FSRP  Receive frame sync pol, 1 - active low
		 * FSXP  Transmit frame sync pol, 1 - active low
		 */
		pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
		break;
	case SND_SOC_DAIFMT_NB_IF:
		/* CLKRP Receive clock polarity,
		 *	1 - sampled on rising edge of CLKR
		 *	valid on rising edge
		 * CLKXP Transmit clock polarity,
		 *	1 - clocked on falling edge of CLKX
		 *	valid on rising edge
		 * FSRP  Receive frame sync pol, 1 - active low
		 * FSXP  Transmit frame sync pol, 1 - active low
		 */
		pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
			DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
		break;
	case SND_SOC_DAIFMT_IB_NF:
		/* CLKRP Receive clock polarity,
		 *	0 - sampled on falling edge of CLKR
		 *	valid on falling edge
		 * CLKXP Transmit clock polarity,
		 *	0 - clocked on rising edge of CLKX
		 *	valid on falling edge
		 * FSRP  Receive frame sync pol, 0 - active high
		 * FSXP  Transmit frame sync pol, 0 - active high
		 */
		break;
	default:
		return -EINVAL;
	}
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
	dev->pcr = pcr;
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
	return 0;
}

static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	struct snd_interval *i = NULL;
	int mcbsp_word_length;
	unsigned int rcr, xcr, srgr;
	u32 spcr;

	/* general line settings */
	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
		spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
	} else {
		spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
	}

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
	srgr = DAVINCI_MCBSP_SRGR_FSGM;
	srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);

	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
	srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);

	/* Determine xfer data type */
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		dma_params->data_type = 1;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		dma_params->data_type = 2;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		dma_params->data_type = 4;
		mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
		break;
	default:
		printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
		rcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
		rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
			       DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);

	} else {
		xcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
		xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
				DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);

	}
	return 0;
}

static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	int ret = 0;
	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		davinci_mcbsp_start(dev, substream);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		davinci_mcbsp_stop(dev, playback);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static int davinci_i2s_probe(struct platform_device *pdev,
			     struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_card *card = socdev->card;
	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
	struct davinci_mcbsp_dev *dev;
	struct resource *mem, *ioarea;
	struct evm_snd_platform_data *pdata;
	int ret;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "no mem resource?\n");
		return -ENODEV;
	}

	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
				    pdev->name);
	if (!ioarea) {
		dev_err(&pdev->dev, "McBSP region already claimed\n");
		return -EBUSY;
	}

	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	if (!dev) {
		ret = -ENOMEM;
		goto err_release_region;
	}

	cpu_dai->private_data = dev;

	dev->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(dev->clk)) {
		ret = -ENODEV;
		goto err_free_mem;
	}
	clk_enable(dev->clk);

	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	pdata = pdev->dev.platform_data;

	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);

	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	    (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);

	return 0;

err_free_mem:
	kfree(dev);
err_release_region:
	release_mem_region(mem->start, (mem->end - mem->start) + 1);

	return ret;
}

static void davinci_i2s_remove(struct platform_device *pdev,
			       struct snd_soc_dai *dai)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_card *card = socdev->card;
	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	struct resource *mem;

	clk_disable(dev->clk);
	clk_put(dev->clk);
	dev->clk = NULL;

	kfree(dev);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(mem->start, (mem->end - mem->start) + 1);
}

#define DAVINCI_I2S_RATES	SNDRV_PCM_RATE_8000_96000

static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
	.startup	= davinci_i2s_startup,
	.trigger	= davinci_i2s_trigger,
	.hw_params	= davinci_i2s_hw_params,
	.set_fmt	= davinci_i2s_set_dai_fmt,
};

struct snd_soc_dai davinci_i2s_dai = {
	.name = "davinci-i2s",
	.id = 0,
	.probe = davinci_i2s_probe,
	.remove = davinci_i2s_remove,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates = DAVINCI_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	.ops = &davinci_i2s_dai_ops,
};
EXPORT_SYMBOL_GPL(davinci_i2s_dai);

static int __init davinci_i2s_init(void)
{
	return snd_soc_register_dai(&davinci_i2s_dai);
}
module_init(davinci_i2s_init);

static void __exit davinci_i2s_exit(void)
{
	snd_soc_unregister_dai(&davinci_i2s_dai);
}
module_exit(davinci_i2s_exit);

MODULE_AUTHOR("Vladimir Barinov");
MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
310355c1 VB	1	/*
	2	* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
	3	*
d6b52039	4	* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
310355c1 VB	5	* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/module.h>
	14	#include <linux/device.h>
	15	#include <linux/delay.h>
	16	#include <linux/io.h>
	17	#include <linux/clk.h>
	18
	19	#include <sound/core.h>
	20	#include <sound/pcm.h>
	21	#include <sound/pcm_params.h>
	22	#include <sound/initval.h>
	23	#include <sound/soc.h>
	24
	25	#include "davinci-pcm.h"
	26
a62114cb DB	27
	28	/*
	29	* NOTE: terminology here is confusing.
	30	*
	31	* - This driver supports the "Audio Serial Port" (ASP),
	32	* found on dm6446, dm355, and other DaVinci chips.
	33	*
	34	* - But it labels it a "Multi-channel Buffered Serial Port"
	35	* (McBSP) as on older chips like the dm642 ... which was
	36	* backward-compatible, possibly explaining that confusion.
	37	*
	38	* - OMAP chips have a controller called McBSP, which is
	39	* incompatible with the DaVinci flavor of McBSP.
	40	*
	41	* - Newer DaVinci chips have a controller called McASP,
	42	* incompatible with ASP and with either McBSP.
	43	*
	44	* In short: this uses ASP to implement I2S, not McBSP.
	45	* And it won't be the only DaVinci implemention of I2S.
	46	*/
310355c1 VB	47	#define DAVINCI_MCBSP_DRR_REG 0x00
	48	#define DAVINCI_MCBSP_DXR_REG 0x04
	49	#define DAVINCI_MCBSP_SPCR_REG 0x08
	50	#define DAVINCI_MCBSP_RCR_REG 0x0c
	51	#define DAVINCI_MCBSP_XCR_REG 0x10
	52	#define DAVINCI_MCBSP_SRGR_REG 0x14
	53	#define DAVINCI_MCBSP_PCR_REG 0x24
	54
	55	#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
	56	#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
	57	#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
	58	#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
	59	#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
	60	#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
	61	#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
	62
	63	#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
	64	#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
	65	#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
	66	#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
	67
	68	#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
	69	#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
	70	#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
	71	#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
	72	#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
	73
	74	#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
	75	#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
	76	#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
	77
	78	#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
	79	#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
	80	#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
	81	#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
b402dff8	82	#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
310355c1 VB	83	#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
	84	#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
	85	#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
	86	#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
	87
310355c1 VB	88	enum {
	89	DAVINCI_MCBSP_WORD_8 = 0,
	90	DAVINCI_MCBSP_WORD_12,
	91	DAVINCI_MCBSP_WORD_16,
	92	DAVINCI_MCBSP_WORD_20,
	93	DAVINCI_MCBSP_WORD_24,
	94	DAVINCI_MCBSP_WORD_32,
	95	};
	96
	97	static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
	98	.name = "I2S PCM Stereo out",
	99	};
	100
	101	static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
	102	.name = "I2S PCM Stereo in",
	103	};
	104
	105	struct davinci_mcbsp_dev {
	106	void __iomem *base;
c392bec7	107	u32 pcr;
310355c1 VB	108	struct clk *clk;
	109	struct davinci_pcm_dma_params *dma_params[2];
	110	};
	111
	112	static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
	113	int reg, u32 val)
	114	{
	115	__raw_writel(val, dev->base + reg);
	116	}
	117
	118	static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
	119	{
	120	return __raw_readl(dev->base + reg);
	121	}
	122
c392bec7 TK	123	static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
	124	{
	125	u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
	126	/* The clock needs to toggle to complete reset.
	127	* So, fake it by toggling the clk polarity.
	128	*/
	129	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
	130	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
	131	}
	132
f9af37cc TK	133	static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
f9af37cc TK	134	struct snd_pcm_substream *substream)
310355c1 VB	135	{
310355c1 VB	136	struct snd_soc_pcm_runtime *rtd = substream->private_data;
fb0ef645	137	struct snd_soc_device *socdev = rtd->socdev;
87689d56	138	struct snd_soc_platform *platform = socdev->card->platform;
c392bec7	139	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
35cf6358	140	u32 spcr;
c392bec7	141	u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
35cf6358	142	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
c392bec7 TK	143	if (spcr & mask) {
	144	/* start off disabled */
	145	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
	146	spcr & ~mask);
	147	toggle_clock(dev, playback);
	148	}
	149	/* Start the sample generator and enable transmitter/receiver */
35cf6358 TK	150	spcr \|= DAVINCI_MCBSP_SPCR_GRST;
35cf6358 TK	151	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
fb0ef645 NM	152
	153	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	154	/* Stop the DMA to avoid data loss */
	155	/* while the transmitter is out of reset to handle XSYNCERR */
	156	if (platform->pcm_ops->trigger) {
eba575c3	157	int ret = platform->pcm_ops->trigger(substream,
fb0ef645 NM	158	SNDRV_PCM_TRIGGER_STOP);
	159	if (ret < 0)
	160	printk(KERN_DEBUG "Playback DMA stop failed\n");
	161	}
	162
	163	/* Enable the transmitter */
35cf6358 TK	164	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	165	spcr \|= DAVINCI_MCBSP_SPCR_XRST;
	166	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
fb0ef645 NM	167
	168	/* wait for any unexpected frame sync error to occur */
	169	udelay(100);
	170
	171	/* Disable the transmitter to clear any outstanding XSYNCERR */
35cf6358 TK	172	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	173	spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
	174	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
c392bec7	175	toggle_clock(dev, playback);
fb0ef645 NM	176
	177	/* Restart the DMA */
	178	if (platform->pcm_ops->trigger) {
eba575c3	179	int ret = platform->pcm_ops->trigger(substream,
fb0ef645 NM	180	SNDRV_PCM_TRIGGER_START);
	181	if (ret < 0)
	182	printk(KERN_DEBUG "Playback DMA start failed\n");
	183	}
	184	/* Enable the transmitter */
35cf6358 TK	185	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	186	spcr \|= DAVINCI_MCBSP_SPCR_XRST;
	187	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
fb0ef645 NM	188
	189	} else {
	190
	191	/* Enable the reciever */
35cf6358 TK	192	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	193	spcr \|= DAVINCI_MCBSP_SPCR_RRST;
	194	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
fb0ef645 NM	195	}
fb0ef645 NM	196
310355c1 VB	197
310355c1 VB	198	/* Start frame sync */
35cf6358 TK	199	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
	200	spcr \|= DAVINCI_MCBSP_SPCR_FRST;
	201	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
310355c1 VB	202	}
310355c1 VB	203
f9af37cc	204	static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
310355c1	205	{
35cf6358	206	u32 spcr;
310355c1 VB	207
310355c1 VB	208	/* Reset transmitter/receiver and sample rate/frame sync generators */
35cf6358 TK	209	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
35cf6358 TK	210	spcr &= ~(DAVINCI_MCBSP_SPCR_GRST \| DAVINCI_MCBSP_SPCR_FRST);
c392bec7	211	spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
35cf6358	212	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
c392bec7	213	toggle_clock(dev, playback);
310355c1 VB	214	}
310355c1 VB	215
dee89c4d MB	216	static int davinci_i2s_startup(struct snd_pcm_substream *substream,
dee89c4d MB	217	struct snd_soc_dai *dai)
310355c1 VB	218	{
310355c1 VB	219	struct snd_soc_pcm_runtime *rtd = substream->private_data;
9cb132d7	220	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
310355c1 VB	221	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	222
	223	cpu_dai->dma_data = dev->dma_params[substream->stream];
	224
	225	return 0;
	226	}
	227
21903c1c TK	228	#define DEFAULT_BITPERSAMPLE 16
21903c1c TK	229
9cb132d7	230	static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
310355c1 VB	231	unsigned int fmt)
	232	{
	233	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
21903c1c TK	234	unsigned int pcr;
	235	unsigned int srgr;
	236	unsigned int rcr;
	237	unsigned int xcr;
	238	srgr = DAVINCI_MCBSP_SRGR_FSGM \|
	239	DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) \|
	240	DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
310355c1 VB	241
	242	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	243	case SND_SOC_DAIFMT_CBS_CFS:
21903c1c TK	244	/* cpu is master */
	245	pcr = DAVINCI_MCBSP_PCR_FSXM \|
	246	DAVINCI_MCBSP_PCR_FSRM \|
	247	DAVINCI_MCBSP_PCR_CLKXM \|
	248	DAVINCI_MCBSP_PCR_CLKRM;
310355c1	249	break;
b402dff8 HV	250	case SND_SOC_DAIFMT_CBM_CFS:
	251	/* McBSP CLKR pin is the input for the Sample Rate Generator.
	252	* McBSP FSR and FSX are driven by the Sample Rate Generator. */
21903c1c TK	253	pcr = DAVINCI_MCBSP_PCR_SCLKME \|
	254	DAVINCI_MCBSP_PCR_FSXM \|
	255	DAVINCI_MCBSP_PCR_FSRM;
b402dff8	256	break;
310355c1	257	case SND_SOC_DAIFMT_CBM_CFM:
21903c1c TK	258	/* codec is master */
21903c1c TK	259	pcr = 0;
310355c1 VB	260	break;
310355c1 VB	261	default:
21903c1c	262	printk(KERN_ERR "%s:bad master\n", __func__);
310355c1 VB	263	return -EINVAL;
	264	}
	265
69ab820c TK	266	rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
	267	xcr = DAVINCI_MCBSP_XCR_XFIG \| DAVINCI_MCBSP_XCR_XFRLEN1(1);
	268	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
07d8d9dc	269	case SND_SOC_DAIFMT_DSP_B:
69ab820c TK	270	break;
69ab820c TK	271	case SND_SOC_DAIFMT_I2S:
07d8d9dc TK	272	/* Davinci doesn't support TRUE I2S, but some codecs will have
	273	* the left and right channels contiguous. This allows
	274	* dsp_a mode to be used with an inverted normal frame clk.
	275	* If your codec is master and does not have contiguous
	276	* channels, then you will have sound on only one channel.
	277	* Try using a different mode, or codec as slave.
	278	*
	279	* The TLV320AIC33 is an example of a codec where this works.
	280	* It has a variable bit clock frequency allowing it to have
	281	* valid data on every bit clock.
	282	*
	283	* The TLV320AIC23 is an example of a codec where this does not
	284	* work. It has a fixed bit clock frequency with progressively
	285	* more empty bit clock slots between channels as the sample
	286	* rate is lowered.
	287	*/
	288	fmt ^= SND_SOC_DAIFMT_NB_IF;
	289	case SND_SOC_DAIFMT_DSP_A:
69ab820c TK	290	rcr \|= DAVINCI_MCBSP_RCR_RDATDLY(1);
	291	xcr \|= DAVINCI_MCBSP_XCR_XDATDLY(1);
	292	break;
	293	default:
	294	printk(KERN_ERR "%s:bad format\n", __func__);
	295	return -EINVAL;
	296	}
	297
310355c1	298	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
9e031624	299	case SND_SOC_DAIFMT_NB_NF:
664b4af8 TK	300	/* CLKRP Receive clock polarity,
	301	* 1 - sampled on rising edge of CLKR
	302	* valid on rising edge
	303	* CLKXP Transmit clock polarity,
	304	* 1 - clocked on falling edge of CLKX
	305	* valid on rising edge
	306	* FSRP Receive frame sync pol, 0 - active high
	307	* FSXP Transmit frame sync pol, 0 - active high
	308	*/
21903c1c	309	pcr \|= (DAVINCI_MCBSP_PCR_CLKXP \| DAVINCI_MCBSP_PCR_CLKRP);
310355c1	310	break;
9e031624	311	case SND_SOC_DAIFMT_IB_IF:
664b4af8 TK	312	/* CLKRP Receive clock polarity,
	313	* 0 - sampled on falling edge of CLKR
	314	* valid on falling edge
	315	* CLKXP Transmit clock polarity,
	316	* 0 - clocked on rising edge of CLKX
	317	* valid on falling edge
	318	* FSRP Receive frame sync pol, 1 - active low
	319	* FSXP Transmit frame sync pol, 1 - active low
	320	*/
21903c1c	321	pcr \|= (DAVINCI_MCBSP_PCR_FSXP \| DAVINCI_MCBSP_PCR_FSRP);
310355c1	322	break;
9e031624	323	case SND_SOC_DAIFMT_NB_IF:
664b4af8 TK	324	/* CLKRP Receive clock polarity,
	325	* 1 - sampled on rising edge of CLKR
	326	* valid on rising edge
	327	* CLKXP Transmit clock polarity,
	328	* 1 - clocked on falling edge of CLKX
	329	* valid on rising edge
	330	* FSRP Receive frame sync pol, 1 - active low
	331	* FSXP Transmit frame sync pol, 1 - active low
	332	*/
21903c1c TK	333	pcr \|= (DAVINCI_MCBSP_PCR_CLKXP \| DAVINCI_MCBSP_PCR_CLKRP \|
21903c1c TK	334	DAVINCI_MCBSP_PCR_FSXP \| DAVINCI_MCBSP_PCR_FSRP);
310355c1	335	break;
9e031624	336	case SND_SOC_DAIFMT_IB_NF:
664b4af8 TK	337	/* CLKRP Receive clock polarity,
	338	* 0 - sampled on falling edge of CLKR
	339	* valid on falling edge
	340	* CLKXP Transmit clock polarity,
	341	* 0 - clocked on rising edge of CLKX
	342	* valid on falling edge
	343	* FSRP Receive frame sync pol, 0 - active high
	344	* FSXP Transmit frame sync pol, 0 - active high
	345	*/
310355c1 VB	346	break;
	347	default:
	348	return -EINVAL;
	349	}
21903c1c	350	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
c392bec7	351	dev->pcr = pcr;
21903c1c TK	352	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
	353	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
	354	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
310355c1 VB	355	return 0;
	356	}
	357
	358	static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	359	struct snd_pcm_hw_params *params,
dee89c4d MB	360	struct snd_soc_dai *dai)
310355c1 VB	361	{
	362	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	363	struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
	364	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
	365	struct snd_interval *i = NULL;
	366	int mcbsp_word_length;
35cf6358 TK	367	unsigned int rcr, xcr, srgr;
35cf6358 TK	368	u32 spcr;
310355c1 VB	369
310355c1 VB	370	/* general line settings */
35cf6358	371	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
cb6e2063	372	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
35cf6358 TK	373	spcr \|= DAVINCI_MCBSP_SPCR_RINTM(3) \| DAVINCI_MCBSP_SPCR_FREE;
35cf6358 TK	374	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
cb6e2063	375	} else {
35cf6358 TK	376	spcr \|= DAVINCI_MCBSP_SPCR_XINTM(3) \| DAVINCI_MCBSP_SPCR_FREE;
35cf6358 TK	377	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
cb6e2063	378	}
310355c1 VB	379
310355c1 VB	380	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
35cf6358 TK	381	srgr = DAVINCI_MCBSP_SRGR_FSGM;
35cf6358 TK	382	srgr \|= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
310355c1 VB	383
310355c1 VB	384	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
35cf6358 TK	385	srgr \|= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
35cf6358 TK	386	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
310355c1 VB	387
	388	/* Determine xfer data type */
	389	switch (params_format(params)) {
	390	case SNDRV_PCM_FORMAT_S8:
	391	dma_params->data_type = 1;
	392	mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
	393	break;
	394	case SNDRV_PCM_FORMAT_S16_LE:
	395	dma_params->data_type = 2;
	396	mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
	397	break;
	398	case SNDRV_PCM_FORMAT_S32_LE:
	399	dma_params->data_type = 4;
	400	mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
	401	break;
	402	default:
9b6e12e4	403	printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
310355c1 VB	404	return -EINVAL;
	405	}
	406
cb6e2063	407	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
35cf6358 TK	408	rcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
	409	rcr \|= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) \|
	410	DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
	411	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
310355c1	412
cb6e2063	413	} else {
35cf6358 TK	414	xcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
	415	xcr \|= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) \|
	416	DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
	417	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
310355c1	418
cb6e2063	419	}
310355c1 VB	420	return 0;
	421	}
	422
dee89c4d MB	423	static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	424	struct snd_soc_dai *dai)
310355c1	425	{
f9af37cc TK	426	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f9af37cc TK	427	struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
310355c1	428	int ret = 0;
f9af37cc	429	int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
310355c1 VB	430
	431	switch (cmd) {
	432	case SNDRV_PCM_TRIGGER_START:
	433	case SNDRV_PCM_TRIGGER_RESUME:
	434	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
f9af37cc	435	davinci_mcbsp_start(dev, substream);
310355c1 VB	436	break;
	437	case SNDRV_PCM_TRIGGER_STOP:
	438	case SNDRV_PCM_TRIGGER_SUSPEND:
	439	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
f9af37cc	440	davinci_mcbsp_stop(dev, playback);
310355c1 VB	441	break;
	442	default:
	443	ret = -EINVAL;
	444	}
	445
	446	return ret;
	447	}
	448
bdb92876	449	static int davinci_i2s_probe(struct platform_device *pdev,
9cb132d7	450	struct snd_soc_dai *dai)
310355c1 VB	451	{
310355c1 VB	452	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
87506549	453	struct snd_soc_card *card = socdev->card;
a62114cb	454	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
310355c1 VB	455	struct davinci_mcbsp_dev *dev;
	456	struct resource mem, ioarea;
	457	struct evm_snd_platform_data *pdata;
	458	int ret;
	459
	460	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	461	if (!mem) {
	462	dev_err(&pdev->dev, "no mem resource?\n");
	463	return -ENODEV;
	464	}
	465
	466	ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
	467	pdev->name);
	468	if (!ioarea) {
	469	dev_err(&pdev->dev, "McBSP region already claimed\n");
	470	return -EBUSY;
	471	}
	472
	473	dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
	474	if (!dev) {
	475	ret = -ENOMEM;
	476	goto err_release_region;
	477	}
	478
	479	cpu_dai->private_data = dev;
	480
a62114cb	481	dev->clk = clk_get(&pdev->dev, NULL);
310355c1 VB	482	if (IS_ERR(dev->clk)) {
	483	ret = -ENODEV;
	484	goto err_free_mem;
	485	}
	486	clk_enable(dev->clk);
	487
	488	dev->base = (void __iomem *)IO_ADDRESS(mem->start);
	489	pdata = pdev->dev.platform_data;
	490
	491	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
	492	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
	493	dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
	494	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
	495
	496	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
	497	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
	498	dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
	499	(dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
	500
	501	return 0;
	502
	503	err_free_mem:
	504	kfree(dev);
	505	err_release_region:
	506	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	507
	508	return ret;
	509	}
	510
bdb92876	511	static void davinci_i2s_remove(struct platform_device *pdev,
9cb132d7	512	struct snd_soc_dai *dai)
310355c1 VB	513	{
310355c1 VB	514	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
87506549	515	struct snd_soc_card *card = socdev->card;
a62114cb	516	struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
310355c1 VB	517	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
	518	struct resource *mem;
	519
	520	clk_disable(dev->clk);
	521	clk_put(dev->clk);
	522	dev->clk = NULL;
	523
	524	kfree(dev);
	525
	526	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	527	release_mem_region(mem->start, (mem->end - mem->start) + 1);
	528	}
	529
	530	#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
	531
6335d055 EM	532	static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
	533	.startup = davinci_i2s_startup,
	534	.trigger = davinci_i2s_trigger,
	535	.hw_params = davinci_i2s_hw_params,
	536	.set_fmt = davinci_i2s_set_dai_fmt,
	537	};
	538
9cb132d7	539	struct snd_soc_dai davinci_i2s_dai = {
310355c1 VB	540	.name = "davinci-i2s",
310355c1 VB	541	.id = 0,
310355c1 VB	542	.probe = davinci_i2s_probe,
	543	.remove = davinci_i2s_remove,
	544	.playback = {
	545	.channels_min = 2,
	546	.channels_max = 2,
	547	.rates = DAVINCI_I2S_RATES,
	548	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
	549	.capture = {
	550	.channels_min = 2,
	551	.channels_max = 2,
	552	.rates = DAVINCI_I2S_RATES,
	553	.formats = SNDRV_PCM_FMTBIT_S16_LE,},
6335d055	554	.ops = &davinci_i2s_dai_ops,
310355c1 VB	555	};
	556	EXPORT_SYMBOL_GPL(davinci_i2s_dai);
	557
c9b3a40f	558	static int __init davinci_i2s_init(void)
3f4b783c MB	559	{
	560	return snd_soc_register_dai(&davinci_i2s_dai);
	561	}
	562	module_init(davinci_i2s_init);
	563
	564	static void __exit davinci_i2s_exit(void)
	565	{
	566	snd_soc_unregister_dai(&davinci_i2s_dai);
	567	}
	568	module_exit(davinci_i2s_exit);
	569
310355c1 VB	570	MODULE_AUTHOR("Vladimir Barinov");
	571	MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
	572	MODULE_LICENSE("GPL");