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ASoC: DaVinci: Added selection of clk input pin for McBSP
[deliverable/linux.git] / sound / soc / davinci / davinci-i2s.c
CommitLineData
310355c1
VB		 1/*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
310355c1
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/device.h>
5a0e3ad6 15#include <linux/slab.h>
310355c1
VB		 16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/initval.h>
24#include <sound/soc.h>
25
ff7d04b1
MB		 26#include <mach/asp.h>
27
310355c1 28#include "davinci-pcm.h"
a4c8ea2d 29#include "davinci-i2s.h"
310355c1 30
a62114cb
DB		 31
32/*
33 * NOTE: terminology here is confusing.
34 *
35 * - This driver supports the "Audio Serial Port" (ASP),
36 * found on dm6446, dm355, and other DaVinci chips.
37 *
38 * - But it labels it a "Multi-channel Buffered Serial Port"
39 * (McBSP) as on older chips like the dm642 ... which was
40 * backward-compatible, possibly explaining that confusion.
41 *
42 * - OMAP chips have a controller called McBSP, which is
43 * incompatible with the DaVinci flavor of McBSP.
44 *
45 * - Newer DaVinci chips have a controller called McASP,
46 * incompatible with ASP and with either McBSP.
47 *
48 * In short: this uses ASP to implement I2S, not McBSP.
49 * And it won't be the only DaVinci implemention of I2S.
50 */
310355c1
VB		 51#define DAVINCI_MCBSP_DRR_REG 0x00
52#define DAVINCI_MCBSP_DXR_REG 0x04
53#define DAVINCI_MCBSP_SPCR_REG 0x08
54#define DAVINCI_MCBSP_RCR_REG 0x0c
55#define DAVINCI_MCBSP_XCR_REG 0x10
56#define DAVINCI_MCBSP_SRGR_REG 0x14
57#define DAVINCI_MCBSP_PCR_REG 0x24
58
59#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
60#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
61#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
62#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
63#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
64#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
65#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
66
67#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
68#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
69#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
f5cfa954 70#define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
310355c1 71#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
a4c8ea2d
RR		 72#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
73#define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
310355c1
VB		 74
75#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
76#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
77#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
78#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
79#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
a4c8ea2d
RR		 80#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
81#define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
310355c1
VB		 82
83#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
84#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
85#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
a4c8ea2d 86#define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
310355c1
VB		 87
88#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
89#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
90#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
91#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
b402dff8 92#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
310355c1
VB		 93#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
94#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
95#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
96#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
97
310355c1
VB		 98enum {
99 DAVINCI_MCBSP_WORD_8 = 0,
100 DAVINCI_MCBSP_WORD_12,
101 DAVINCI_MCBSP_WORD_16,
102 DAVINCI_MCBSP_WORD_20,
103 DAVINCI_MCBSP_WORD_24,
104 DAVINCI_MCBSP_WORD_32,
105};
106
0d6c9774
TK		 107static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
108 [SNDRV_PCM_FORMAT_S8] = 1,
109 [SNDRV_PCM_FORMAT_S16_LE] = 2,
110 [SNDRV_PCM_FORMAT_S32_LE] = 4,
111};
112
113static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
114 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
115 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
116 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
117};
118
119static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
120 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
121 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
122};
123
310355c1 124struct davinci_mcbsp_dev {
ec637553 125 struct device *dev;
92e2a6f6 126 struct davinci_pcm_dma_params dma_params[2];
310355c1 127 void __iomem *base;
f5cfa954
TK		 128#define MOD_DSP_A 0
129#define MOD_DSP_B 1
130 int mode;
c392bec7 131 u32 pcr;
310355c1 132 struct clk *clk;
0d6c9774
TK		 133 /*
134 * Combining both channels into 1 element will at least double the
135 * amount of time between servicing the dma channel, increase
136 * effiency, and reduce the chance of overrun/underrun. But,
137 * it will result in the left & right channels being swapped.
138 *
139 * If relabeling the left and right channels is not possible,
140 * you may want to let the codec know to swap them back.
141 *
142 * It may allow x10 the amount of time to service dma requests,
143 * if the codec is master and is using an unnecessarily fast bit clock
144 * (ie. tlvaic23b), independent of the sample rate. So, having an
145 * entire frame at once means it can be serviced at the sample rate
146 * instead of the bit clock rate.
147 *
148 * In the now unlikely case that an underrun still
149 * occurs, both the left and right samples will be repeated
150 * so that no pops are heard, and the left and right channels
151 * won't end up being swapped because of the underrun.
152 */
153 unsigned enable_channel_combine:1;
a4c8ea2d
RR		 154
155 unsigned int fmt;
156 int clk_div;
ec637553 157 int clk_input_pin;
310355c1
VB		 158};
159
160static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
161 int reg, u32 val)
162{
163 __raw_writel(val, dev->base + reg);
164}
165
166static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
167{
168 return __raw_readl(dev->base + reg);
169}
170
c392bec7
TK		 171static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
172{
173 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
174 /* The clock needs to toggle to complete reset.
175 * So, fake it by toggling the clk polarity.
176 */
177 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
178 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
179}
180
f9af37cc
TK		 181static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
182 struct snd_pcm_substream *substream)
310355c1
VB		 183{
184 struct snd_soc_pcm_runtime *rtd = substream->private_data;
fb0ef645 185 struct snd_soc_device *socdev = rtd->socdev;
87689d56 186 struct snd_soc_platform *platform = socdev->card->platform;
c392bec7 187 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
35cf6358 188 u32 spcr;
c392bec7 189 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
35cf6358 190 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
c392bec7
TK		 191 if (spcr & mask) {
192 /* start off disabled */
193 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
194 spcr & ~mask);
195 toggle_clock(dev, playback);
196 }
1bef4499
TK		 197 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
198 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
199 /* Start the sample generator */
200 spcr |= DAVINCI_MCBSP_SPCR_GRST;
201 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
202 }
fb0ef645 203
1bef4499 204 if (playback) {
fb0ef645
NM		 205 /* Stop the DMA to avoid data loss */
206 /* while the transmitter is out of reset to handle XSYNCERR */
207 if (platform->pcm_ops->trigger) {
eba575c3 208 int ret = platform->pcm_ops->trigger(substream,
fb0ef645
NM		 209 SNDRV_PCM_TRIGGER_STOP);
210 if (ret < 0)
211 printk(KERN_DEBUG "Playback DMA stop failed\n");
212 }
213
214 /* Enable the transmitter */
35cf6358
TK		 215 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
216 spcr |= DAVINCI_MCBSP_SPCR_XRST;
217 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
fb0ef645
NM		 218
219 /* wait for any unexpected frame sync error to occur */
220 udelay(100);
221
222 /* Disable the transmitter to clear any outstanding XSYNCERR */
35cf6358
TK		 223 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
224 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
225 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
c392bec7 226 toggle_clock(dev, playback);
fb0ef645
NM		 227
228 /* Restart the DMA */
229 if (platform->pcm_ops->trigger) {
eba575c3 230 int ret = platform->pcm_ops->trigger(substream,
fb0ef645
NM		 231 SNDRV_PCM_TRIGGER_START);
232 if (ret < 0)
233 printk(KERN_DEBUG "Playback DMA start failed\n");
234 }
fb0ef645
NM		 235 }
236
1bef4499 237 /* Enable transmitter or receiver */
35cf6358 238 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
1bef4499
TK		 239 spcr |= mask;
240
241 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
242 /* Start frame sync */
243 spcr |= DAVINCI_MCBSP_SPCR_FRST;
244 }
35cf6358 245 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
310355c1
VB		 246}
247
f9af37cc 248static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
310355c1 249{
35cf6358 250 u32 spcr;
310355c1
VB		 251
252 /* Reset transmitter/receiver and sample rate/frame sync generators */
35cf6358
TK		 253 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
254 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
c392bec7 255 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
35cf6358 256 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
c392bec7 257 toggle_clock(dev, playback);
310355c1
VB		 258}
259
21903c1c
TK		 260#define DEFAULT_BITPERSAMPLE 16
261
9cb132d7 262static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
310355c1
VB		 263 unsigned int fmt)
264{
265 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
21903c1c
TK		 266 unsigned int pcr;
267 unsigned int srgr;
a4c8ea2d 268 /* Attention srgr is updated by hw_params! */
21903c1c
TK		 269 srgr = DAVINCI_MCBSP_SRGR_FSGM |
270 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
271 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
310355c1 272
a4c8ea2d 273 dev->fmt = fmt;
f5cfa954 274 /* set master/slave audio interface */
310355c1
VB		 275 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
276 case SND_SOC_DAIFMT_CBS_CFS:
21903c1c
TK		 277 /* cpu is master */
278 pcr = DAVINCI_MCBSP_PCR_FSXM |
279 DAVINCI_MCBSP_PCR_FSRM |
280 DAVINCI_MCBSP_PCR_CLKXM |
281 DAVINCI_MCBSP_PCR_CLKRM;
310355c1 282 break;
b402dff8 283 case SND_SOC_DAIFMT_CBM_CFS:
ec637553
RR		 284 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
285 /*
286 * Selection of the clock input pin that is the
287 * input for the Sample Rate Generator.
288 * McBSP FSR and FSX are driven by the Sample Rate
289 * Generator.
290 */
291 switch (dev->clk_input_pin) {
292 case MCBSP_CLKS:
293 pcr |= DAVINCI_MCBSP_PCR_CLKXM |
294 DAVINCI_MCBSP_PCR_CLKRM;
295 break;
296 case MCBSP_CLKR:
297 pcr |= DAVINCI_MCBSP_PCR_SCLKME;
298 break;
299 default:
300 dev_err(dev->dev, "bad clk_input_pin\n");
301 return -EINVAL;
302 }
303
b402dff8 304 break;
310355c1 305 case SND_SOC_DAIFMT_CBM_CFM:
21903c1c
TK		 306 /* codec is master */
307 pcr = 0;
310355c1
VB		 308 break;
309 default:
21903c1c 310 printk(KERN_ERR "%s:bad master\n", __func__);
310355c1
VB		 311 return -EINVAL;
312 }
313
f5cfa954 314 /* interface format */
69ab820c 315 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
69ab820c 316 case SND_SOC_DAIFMT_I2S:
07d8d9dc
TK		 317 /* Davinci doesn't support TRUE I2S, but some codecs will have
318 * the left and right channels contiguous. This allows
319 * dsp_a mode to be used with an inverted normal frame clk.
320 * If your codec is master and does not have contiguous
321 * channels, then you will have sound on only one channel.
322 * Try using a different mode, or codec as slave.
323 *
324 * The TLV320AIC33 is an example of a codec where this works.
325 * It has a variable bit clock frequency allowing it to have
326 * valid data on every bit clock.
327 *
328 * The TLV320AIC23 is an example of a codec where this does not
329 * work. It has a fixed bit clock frequency with progressively
330 * more empty bit clock slots between channels as the sample
331 * rate is lowered.
332 */
333 fmt ^= SND_SOC_DAIFMT_NB_IF;
334 case SND_SOC_DAIFMT_DSP_A:
f5cfa954
TK		 335 dev->mode = MOD_DSP_A;
336 break;
337 case SND_SOC_DAIFMT_DSP_B:
338 dev->mode = MOD_DSP_B;
69ab820c
TK		 339 break;
340 default:
341 printk(KERN_ERR "%s:bad format\n", __func__);
342 return -EINVAL;
343 }
344
310355c1 345 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
9e031624 346 case SND_SOC_DAIFMT_NB_NF:
664b4af8
TK		 347 /* CLKRP Receive clock polarity,
348 * 1 - sampled on rising edge of CLKR
349 * valid on rising edge
350 * CLKXP Transmit clock polarity,
351 * 1 - clocked on falling edge of CLKX
352 * valid on rising edge
353 * FSRP Receive frame sync pol, 0 - active high
354 * FSXP Transmit frame sync pol, 0 - active high
355 */
21903c1c 356 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
310355c1 357 break;
9e031624 358 case SND_SOC_DAIFMT_IB_IF:
664b4af8
TK		 359 /* CLKRP Receive clock polarity,
360 * 0 - sampled on falling edge of CLKR
361 * valid on falling edge
362 * CLKXP Transmit clock polarity,
363 * 0 - clocked on rising edge of CLKX
364 * valid on falling edge
365 * FSRP Receive frame sync pol, 1 - active low
366 * FSXP Transmit frame sync pol, 1 - active low
367 */
21903c1c 368 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
310355c1 369 break;
9e031624 370 case SND_SOC_DAIFMT_NB_IF:
664b4af8
TK		 371 /* CLKRP Receive clock polarity,
372 * 1 - sampled on rising edge of CLKR
373 * valid on rising edge
374 * CLKXP Transmit clock polarity,
375 * 1 - clocked on falling edge of CLKX
376 * valid on rising edge
377 * FSRP Receive frame sync pol, 1 - active low
378 * FSXP Transmit frame sync pol, 1 - active low
379 */
21903c1c
TK		 380 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
381 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
310355c1 382 break;
9e031624 383 case SND_SOC_DAIFMT_IB_NF:
664b4af8
TK		 384 /* CLKRP Receive clock polarity,
385 * 0 - sampled on falling edge of CLKR
386 * valid on falling edge
387 * CLKXP Transmit clock polarity,
388 * 0 - clocked on rising edge of CLKX
389 * valid on falling edge
390 * FSRP Receive frame sync pol, 0 - active high
391 * FSXP Transmit frame sync pol, 0 - active high
392 */
310355c1
VB		 393 break;
394 default:
395 return -EINVAL;
396 }
21903c1c 397 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
c392bec7 398 dev->pcr = pcr;
21903c1c 399 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
310355c1
VB		 400 return 0;
401}
402
a4c8ea2d
RR		 403static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
404 int div_id, int div)
405{
406 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
407
408 if (div_id != DAVINCI_MCBSP_CLKGDV)
409 return -ENODEV;
410
411 dev->clk_div = div;
412 return 0;
413}
414
310355c1 415static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 416 struct snd_pcm_hw_params *params,
417 struct snd_soc_dai *dai)
310355c1 418{
9bb74150 419 struct davinci_mcbsp_dev *dev = dai->private_data;
81ac55aa 420 struct davinci_pcm_dma_params *dma_params =
92e2a6f6 421 &dev->dma_params[substream->stream];
310355c1 422 struct snd_interval *i = NULL;
a4c8ea2d
RR		 423 int mcbsp_word_length, master;
424 unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
35cf6358 425 u32 spcr;
0d6c9774
TK		 426 snd_pcm_format_t fmt;
427 unsigned element_cnt = 1;
310355c1
VB		 428
429 /* general line settings */
35cf6358 430 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
cb6e2063 431 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
35cf6358
TK		 432 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
433 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
cb6e2063 434 } else {
35cf6358
TK		 435 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
436 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
cb6e2063 437 }
310355c1 438
a4c8ea2d
RR		 439 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
440 fmt = params_format(params);
441 mcbsp_word_length = asp_word_length[fmt];
310355c1 442
a4c8ea2d
RR		 443 switch (master) {
444 case SND_SOC_DAIFMT_CBS_CFS:
445 freq = clk_get_rate(dev->clk);
446 srgr = DAVINCI_MCBSP_SRGR_FSGM |
447 DAVINCI_MCBSP_SRGR_CLKSM;
448 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
449 8 - 1);
450 /* symmetric waveforms */
451 clk_div = freq / (mcbsp_word_length * 16) /
452 params->rate_num * params->rate_den;
453 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
454 16 - 1);
455 clk_div &= 0xFF;
456 srgr |= clk_div;
457 break;
458 case SND_SOC_DAIFMT_CBM_CFS:
459 srgr = DAVINCI_MCBSP_SRGR_FSGM;
460 clk_div = dev->clk_div - 1;
461 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
462 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
463 clk_div &= 0xFF;
464 srgr |= clk_div;
465 break;
466 case SND_SOC_DAIFMT_CBM_CFM:
467 /* Clock and frame sync given from external sources */
468 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
469 srgr = DAVINCI_MCBSP_SRGR_FSGM;
470 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
471 pr_debug("%s - %d FWID set: re-read srgr = %X\n",
472 __func__, __LINE__, snd_interval_value(i) - 1);
473
474 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
475 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
476 break;
477 default:
478 return -EINVAL;
479 }
35cf6358 480 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
310355c1 481
f5cfa954
TK		 482 rcr = DAVINCI_MCBSP_RCR_RFIG;
483 xcr = DAVINCI_MCBSP_XCR_XFIG;
484 if (dev->mode == MOD_DSP_B) {
485 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
486 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
487 } else {
488 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
489 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
490 }
310355c1 491 /* Determine xfer data type */
0d6c9774
TK		 492 fmt = params_format(params);
493 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
9b6e12e4 494 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
310355c1
VB		 495 return -EINVAL;
496 }
497
0d6c9774
TK		 498 if (params_channels(params) == 2) {
499 element_cnt = 2;
500 if (double_fmt[fmt] && dev->enable_channel_combine) {
501 element_cnt = 1;
502 fmt = double_fmt[fmt];
503 }
a4c8ea2d
RR		 504 switch (master) {
505 case SND_SOC_DAIFMT_CBS_CFS:
506 case SND_SOC_DAIFMT_CBS_CFM:
507 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
508 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
509 rcr |= DAVINCI_MCBSP_RCR_RPHASE;
510 xcr |= DAVINCI_MCBSP_XCR_XPHASE;
511 break;
512 case SND_SOC_DAIFMT_CBM_CFM:
513 case SND_SOC_DAIFMT_CBM_CFS:
514 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
515 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
516 break;
517 default:
518 return -EINVAL;
519 }
0d6c9774
TK		 520 }
521 dma_params->acnt = dma_params->data_type = data_type[fmt];
4fa9c1a5 522 dma_params->fifo_level = 0;
0d6c9774 523 mcbsp_word_length = asp_word_length[fmt];
a4c8ea2d
RR		 524
525 switch (master) {
526 case SND_SOC_DAIFMT_CBS_CFS:
527 case SND_SOC_DAIFMT_CBS_CFM:
528 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
529 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
530 break;
531 case SND_SOC_DAIFMT_CBM_CFM:
532 case SND_SOC_DAIFMT_CBM_CFS:
533 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
534 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
535 break;
536 default:
537 return -EINVAL;
538 }
310355c1 539
f5cfa954
TK		 540 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
541 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
542 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
543 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
310355c1 544
f5cfa954
TK		 545 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
546 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
547 else
548 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
a4c8ea2d
RR		 549
550 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
551 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
552 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
310355c1
VB		 553 return 0;
554}
555
af0adf3e
TK		 556static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
557 struct snd_soc_dai *dai)
558{
9bb74150 559 struct davinci_mcbsp_dev *dev = dai->private_data;
af0adf3e
TK		 560 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
561 davinci_mcbsp_stop(dev, playback);
562 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) {
563 /* codec is master */
564 davinci_mcbsp_start(dev, substream);
565 }
566 return 0;
567}
568
dee89c4d
MB		 569static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
570 struct snd_soc_dai *dai)
310355c1 571{
9bb74150 572 struct davinci_mcbsp_dev *dev = dai->private_data;
310355c1 573 int ret = 0;
f9af37cc 574 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
af0adf3e
TK		 575 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0)
576 return 0; /* return if codec is master */
310355c1
VB		 577
578 switch (cmd) {
579 case SNDRV_PCM_TRIGGER_START:
580 case SNDRV_PCM_TRIGGER_RESUME:
581 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
f9af37cc 582 davinci_mcbsp_start(dev, substream);
310355c1
VB		 583 break;
584 case SNDRV_PCM_TRIGGER_STOP:
585 case SNDRV_PCM_TRIGGER_SUSPEND:
586 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
f9af37cc 587 davinci_mcbsp_stop(dev, playback);
310355c1
VB		 588 break;
589 default:
590 ret = -EINVAL;
591 }
310355c1
VB		 592 return ret;
593}
594
af0adf3e
TK		 595static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
596 struct snd_soc_dai *dai)
597{
9bb74150 598 struct davinci_mcbsp_dev *dev = dai->private_data;
af0adf3e
TK		 599 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
600 davinci_mcbsp_stop(dev, playback);
601}
602
5204d496
C		 603#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
604
605static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
3f405b46
MB		 606 .shutdown = davinci_i2s_shutdown,
607 .prepare = davinci_i2s_prepare,
5204d496
C		 608 .trigger = davinci_i2s_trigger,
609 .hw_params = davinci_i2s_hw_params,
610 .set_fmt = davinci_i2s_set_dai_fmt,
a4c8ea2d 611 .set_clkdiv = davinci_i2s_dai_set_clkdiv,
5204d496
C		 612
613};
614
615struct snd_soc_dai davinci_i2s_dai = {
616 .name = "davinci-i2s",
617 .id = 0,
618 .playback = {
619 .channels_min = 2,
620 .channels_max = 2,
621 .rates = DAVINCI_I2S_RATES,
622 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
623 .capture = {
624 .channels_min = 2,
625 .channels_max = 2,
626 .rates = DAVINCI_I2S_RATES,
627 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
628 .ops = &davinci_i2s_dai_ops,
629
630};
631EXPORT_SYMBOL_GPL(davinci_i2s_dai);
632
633static int davinci_i2s_probe(struct platform_device *pdev)
310355c1 634{
5204d496 635 struct snd_platform_data *pdata = pdev->dev.platform_data;
310355c1 636 struct davinci_mcbsp_dev *dev;
5204d496 637 struct resource *mem, *ioarea, *res;
310355c1
VB		 638 int ret;
639
640 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
641 if (!mem) {
642 dev_err(&pdev->dev, "no mem resource?\n");
643 return -ENODEV;
644 }
645
646 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
647 pdev->name);
648 if (!ioarea) {
649 dev_err(&pdev->dev, "McBSP region already claimed\n");
650 return -EBUSY;
651 }
652
653 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
654 if (!dev) {
655 ret = -ENOMEM;
656 goto err_release_region;
657 }
1e224f32 658 if (pdata) {
0d6c9774 659 dev->enable_channel_combine = pdata->enable_channel_combine;
1e224f32
TK		 660 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
661 pdata->sram_size_playback;
662 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
663 pdata->sram_size_capture;
ec637553 664 dev->clk_input_pin = pdata->clk_input_pin;
1e224f32 665 }
3e46a447 666 dev->clk = clk_get(&pdev->dev, NULL);
310355c1
VB		 667 if (IS_ERR(dev->clk)) {
668 ret = -ENODEV;
669 goto err_free_mem;
670 }
671 clk_enable(dev->clk);
672
673 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
310355c1 674
92e2a6f6 675 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr =
310355c1
VB		 676 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
677
92e2a6f6 678 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr =
310355c1
VB		 679 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
680
5204d496
C		 681 /* first TX, then RX */
682 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
683 if (!res) {
684 dev_err(&pdev->dev, "no DMA resource\n");
efd13be0 685 ret = -ENXIO;
5204d496
C		 686 goto err_free_mem;
687 }
92e2a6f6 688 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start;
5204d496
C		 689
690 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
691 if (!res) {
692 dev_err(&pdev->dev, "no DMA resource\n");
efd13be0 693 ret = -ENXIO;
5204d496
C		 694 goto err_free_mem;
695 }
92e2a6f6 696 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start;
ec637553 697 dev->dev = &pdev->dev;
5204d496
C		 698
699 davinci_i2s_dai.private_data = dev;
5f712b2b
DM		 700 davinci_i2s_dai.capture.dma_data = dev->dma_params;
701 davinci_i2s_dai.playback.dma_data = dev->dma_params;
5204d496
C		 702 ret = snd_soc_register_dai(&davinci_i2s_dai);
703 if (ret != 0)
704 goto err_free_mem;
705
310355c1
VB		 706 return 0;
707
708err_free_mem:
709 kfree(dev);
710err_release_region:
711 release_mem_region(mem->start, (mem->end - mem->start) + 1);
712
713 return ret;
714}
715
5204d496 716static int davinci_i2s_remove(struct platform_device *pdev)
310355c1 717{
5204d496 718 struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data;
310355c1
VB		 719 struct resource *mem;
720
5204d496 721 snd_soc_unregister_dai(&davinci_i2s_dai);
310355c1
VB		 722 clk_disable(dev->clk);
723 clk_put(dev->clk);
724 dev->clk = NULL;
310355c1 725 kfree(dev);
310355c1
VB		 726 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
727 release_mem_region(mem->start, (mem->end - mem->start) + 1);
310355c1 728
5204d496
C		 729 return 0;
730}
6335d055 731
5204d496
C		 732static struct platform_driver davinci_mcbsp_driver = {
733 .probe = davinci_i2s_probe,
734 .remove = davinci_i2s_remove,
735 .driver = {
736 .name = "davinci-asp",
737 .owner = THIS_MODULE,
738 },
310355c1 739};
310355c1 740
c9b3a40f 741static int __init davinci_i2s_init(void)
3f4b783c 742{
5204d496 743 return platform_driver_register(&davinci_mcbsp_driver);
3f4b783c
MB		 744}
745module_init(davinci_i2s_init);
746
747static void __exit davinci_i2s_exit(void)
748{
5204d496 749 platform_driver_unregister(&davinci_mcbsp_driver);
3f4b783c
MB		 750}
751module_exit(davinci_i2s_exit);
752
310355c1
VB		 753MODULE_AUTHOR("Vladimir Barinov");
754MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
755MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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