Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
9759e7ef | 29 | #include <linux/platform_data/davinci_asp.h> |
a75a053f | 30 | #include <linux/math64.h> |
b67f4487 | 31 | |
6479285d | 32 | #include <sound/asoundef.h> |
b67f4487 C |
33 | #include <sound/core.h> |
34 | #include <sound/pcm.h> | |
35 | #include <sound/pcm_params.h> | |
36 | #include <sound/initval.h> | |
37 | #include <sound/soc.h> | |
453c4990 | 38 | #include <sound/dmaengine_pcm.h> |
87c19364 | 39 | #include <sound/omap-pcm.h> |
b67f4487 | 40 | |
f3f9cfa8 | 41 | #include "edma-pcm.h" |
b67f4487 C |
42 | #include "davinci-mcasp.h" |
43 | ||
0bf0e8ae PU |
44 | #define MCASP_MAX_AFIFO_DEPTH 64 |
45 | ||
1cc0c054 PU |
46 | static u32 context_regs[] = { |
47 | DAVINCI_MCASP_TXFMCTL_REG, | |
48 | DAVINCI_MCASP_RXFMCTL_REG, | |
49 | DAVINCI_MCASP_TXFMT_REG, | |
50 | DAVINCI_MCASP_RXFMT_REG, | |
51 | DAVINCI_MCASP_ACLKXCTL_REG, | |
52 | DAVINCI_MCASP_ACLKRCTL_REG, | |
f114ce60 PU |
53 | DAVINCI_MCASP_AHCLKXCTL_REG, |
54 | DAVINCI_MCASP_AHCLKRCTL_REG, | |
1cc0c054 | 55 | DAVINCI_MCASP_PDIR_REG, |
f114ce60 PU |
56 | DAVINCI_MCASP_RXMASK_REG, |
57 | DAVINCI_MCASP_TXMASK_REG, | |
58 | DAVINCI_MCASP_RXTDM_REG, | |
59 | DAVINCI_MCASP_TXTDM_REG, | |
1cc0c054 PU |
60 | }; |
61 | ||
790bb94b | 62 | struct davinci_mcasp_context { |
1cc0c054 | 63 | u32 config_regs[ARRAY_SIZE(context_regs)]; |
f114ce60 PU |
64 | u32 afifo_regs[2]; /* for read/write fifo control registers */ |
65 | u32 *xrsr_regs; /* for serializer configuration */ | |
6afda7f5 | 66 | bool pm_state; |
790bb94b PU |
67 | }; |
68 | ||
a75a053f JS |
69 | struct davinci_mcasp_ruledata { |
70 | struct davinci_mcasp *mcasp; | |
71 | int serializers; | |
72 | }; | |
73 | ||
70091a3e | 74 | struct davinci_mcasp { |
453c4990 | 75 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 76 | void __iomem *base; |
487dce88 | 77 | u32 fifo_base; |
21400a72 | 78 | struct device *dev; |
a7a3324a | 79 | struct snd_pcm_substream *substreams[2]; |
4a11ff26 | 80 | unsigned int dai_fmt; |
21400a72 PU |
81 | |
82 | /* McASP specific data */ | |
83 | int tdm_slots; | |
dd55ff83 JS |
84 | u32 tdm_mask[2]; |
85 | int slot_width; | |
21400a72 PU |
86 | u8 op_mode; |
87 | u8 num_serializer; | |
88 | u8 *serial_dir; | |
89 | u8 version; | |
8267525c | 90 | u8 bclk_div; |
4dcb5a0b | 91 | int streams; |
a7a3324a | 92 | u32 irq_request[2]; |
9759e7ef | 93 | int dma_request[2]; |
21400a72 | 94 | |
ab8b14b6 JS |
95 | int sysclk_freq; |
96 | bool bclk_master; | |
97 | ||
21400a72 PU |
98 | /* McASP FIFO related */ |
99 | u8 txnumevt; | |
100 | u8 rxnumevt; | |
101 | ||
cbc7956c PU |
102 | bool dat_port; |
103 | ||
11277833 PU |
104 | /* Used for comstraint setting on the second stream */ |
105 | u32 channels; | |
106 | ||
21400a72 | 107 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 108 | struct davinci_mcasp_context context; |
21400a72 | 109 | #endif |
a75a053f JS |
110 | |
111 | struct davinci_mcasp_ruledata ruledata[2]; | |
5935a056 | 112 | struct snd_pcm_hw_constraint_list chconstr[2]; |
21400a72 PU |
113 | }; |
114 | ||
f68205a7 PU |
115 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
116 | u32 val) | |
b67f4487 | 117 | { |
f68205a7 | 118 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
119 | __raw_writel(__raw_readl(reg) | val, reg); |
120 | } | |
121 | ||
f68205a7 PU |
122 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
123 | u32 val) | |
b67f4487 | 124 | { |
f68205a7 | 125 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
126 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
127 | } | |
128 | ||
f68205a7 PU |
129 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
130 | u32 val, u32 mask) | |
b67f4487 | 131 | { |
f68205a7 | 132 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
133 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
134 | } | |
135 | ||
f68205a7 PU |
136 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
137 | u32 val) | |
b67f4487 | 138 | { |
f68205a7 | 139 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
140 | } |
141 | ||
f68205a7 | 142 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 143 | { |
f68205a7 | 144 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
145 | } |
146 | ||
f68205a7 | 147 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
148 | { |
149 | int i = 0; | |
150 | ||
f68205a7 | 151 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
152 | |
153 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
154 | /* loop count is to avoid the lock-up */ | |
155 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 156 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
157 | break; |
158 | } | |
159 | ||
f68205a7 | 160 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
161 | printk(KERN_ERR "GBLCTL write error\n"); |
162 | } | |
163 | ||
4dcb5a0b PU |
164 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
165 | { | |
f68205a7 PU |
166 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
167 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
168 | |
169 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
170 | } | |
171 | ||
70091a3e | 172 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 173 | { |
bb372af0 PU |
174 | if (mcasp->rxnumevt) { /* enable FIFO */ |
175 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
176 | ||
177 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
178 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
179 | } | |
180 | ||
44982735 | 181 | /* Start clocks */ |
f68205a7 PU |
182 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
183 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
184 | /* |
185 | * When ASYNC == 0 the transmit and receive sections operate | |
186 | * synchronously from the transmit clock and frame sync. We need to make | |
187 | * sure that the TX signlas are enabled when starting reception. | |
188 | */ | |
189 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
190 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
191 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
192 | } |
193 | ||
44982735 | 194 | /* Activate serializer(s) */ |
f68205a7 | 195 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
44982735 | 196 | /* Release RX state machine */ |
f68205a7 | 197 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
44982735 | 198 | /* Release Frame Sync generator */ |
f68205a7 | 199 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
4dcb5a0b | 200 | if (mcasp_is_synchronous(mcasp)) |
f68205a7 | 201 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
a7a3324a MLC |
202 | |
203 | /* enable receive IRQs */ | |
204 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
205 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
b67f4487 C |
206 | } |
207 | ||
70091a3e | 208 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 209 | { |
6a99fb5f C |
210 | u32 cnt; |
211 | ||
bb372af0 PU |
212 | if (mcasp->txnumevt) { /* enable FIFO */ |
213 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
214 | ||
215 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
216 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
217 | } | |
218 | ||
36bcecd0 | 219 | /* Start clocks */ |
f68205a7 PU |
220 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
221 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
36bcecd0 | 222 | /* Activate serializer(s) */ |
f68205a7 | 223 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); |
b67f4487 | 224 | |
36bcecd0 | 225 | /* wait for XDATA to be cleared */ |
6a99fb5f | 226 | cnt = 0; |
e2a0c9fa PU |
227 | while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && |
228 | (cnt < 100000)) | |
6a99fb5f C |
229 | cnt++; |
230 | ||
36bcecd0 PU |
231 | /* Release TX state machine */ |
232 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); | |
233 | /* Release Frame Sync generator */ | |
234 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
a7a3324a MLC |
235 | |
236 | /* enable transmit IRQs */ | |
237 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
238 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
b67f4487 C |
239 | } |
240 | ||
70091a3e | 241 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 242 | { |
4dcb5a0b PU |
243 | mcasp->streams++; |
244 | ||
bb372af0 | 245 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 246 | mcasp_start_tx(mcasp); |
bb372af0 | 247 | else |
70091a3e | 248 | mcasp_start_rx(mcasp); |
b67f4487 C |
249 | } |
250 | ||
70091a3e | 251 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 252 | { |
a7a3324a MLC |
253 | /* disable IRQ sources */ |
254 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
255 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
256 | ||
4dcb5a0b PU |
257 | /* |
258 | * In synchronous mode stop the TX clocks if no other stream is | |
259 | * running | |
260 | */ | |
261 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 262 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 263 | |
f68205a7 PU |
264 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
265 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
266 | |
267 | if (mcasp->rxnumevt) { /* disable FIFO */ | |
268 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
269 | ||
270 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
271 | } | |
b67f4487 C |
272 | } |
273 | ||
70091a3e | 274 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 275 | { |
4dcb5a0b PU |
276 | u32 val = 0; |
277 | ||
a7a3324a MLC |
278 | /* disable IRQ sources */ |
279 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
280 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
281 | ||
4dcb5a0b PU |
282 | /* |
283 | * In synchronous mode keep TX clocks running if the capture stream is | |
284 | * still running. | |
285 | */ | |
286 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
287 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
288 | ||
f68205a7 PU |
289 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
290 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
291 | |
292 | if (mcasp->txnumevt) { /* disable FIFO */ | |
293 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
294 | ||
295 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
296 | } | |
b67f4487 C |
297 | } |
298 | ||
70091a3e | 299 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 300 | { |
4dcb5a0b PU |
301 | mcasp->streams--; |
302 | ||
0380866a | 303 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 304 | mcasp_stop_tx(mcasp); |
0380866a | 305 | else |
70091a3e | 306 | mcasp_stop_rx(mcasp); |
b67f4487 C |
307 | } |
308 | ||
a7a3324a MLC |
309 | static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) |
310 | { | |
311 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
312 | struct snd_pcm_substream *substream; | |
313 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; | |
314 | u32 handled_mask = 0; | |
315 | u32 stat; | |
316 | ||
317 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); | |
318 | if (stat & XUNDRN & irq_mask) { | |
319 | dev_warn(mcasp->dev, "Transmit buffer underflow\n"); | |
320 | handled_mask |= XUNDRN; | |
321 | ||
322 | substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; | |
323 | if (substream) { | |
324 | snd_pcm_stream_lock_irq(substream); | |
325 | if (snd_pcm_running(substream)) | |
326 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); | |
327 | snd_pcm_stream_unlock_irq(substream); | |
328 | } | |
329 | } | |
330 | ||
331 | if (!handled_mask) | |
332 | dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", | |
333 | stat); | |
334 | ||
335 | if (stat & XRERR) | |
336 | handled_mask |= XRERR; | |
337 | ||
338 | /* Ack the handled event only */ | |
339 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); | |
340 | ||
341 | return IRQ_RETVAL(handled_mask); | |
342 | } | |
343 | ||
344 | static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) | |
345 | { | |
346 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
347 | struct snd_pcm_substream *substream; | |
348 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; | |
349 | u32 handled_mask = 0; | |
350 | u32 stat; | |
351 | ||
352 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); | |
353 | if (stat & ROVRN & irq_mask) { | |
354 | dev_warn(mcasp->dev, "Receive buffer overflow\n"); | |
355 | handled_mask |= ROVRN; | |
356 | ||
357 | substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; | |
358 | if (substream) { | |
359 | snd_pcm_stream_lock_irq(substream); | |
360 | if (snd_pcm_running(substream)) | |
361 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); | |
362 | snd_pcm_stream_unlock_irq(substream); | |
363 | } | |
364 | } | |
365 | ||
366 | if (!handled_mask) | |
367 | dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", | |
368 | stat); | |
369 | ||
370 | if (stat & XRERR) | |
371 | handled_mask |= XRERR; | |
372 | ||
373 | /* Ack the handled event only */ | |
374 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); | |
375 | ||
376 | return IRQ_RETVAL(handled_mask); | |
377 | } | |
378 | ||
5a1b8a80 PU |
379 | static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) |
380 | { | |
381 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
382 | irqreturn_t ret = IRQ_NONE; | |
383 | ||
384 | if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) | |
385 | ret = davinci_mcasp_tx_irq_handler(irq, data); | |
386 | ||
387 | if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) | |
388 | ret |= davinci_mcasp_rx_irq_handler(irq, data); | |
389 | ||
390 | return ret; | |
391 | } | |
392 | ||
b67f4487 C |
393 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
394 | unsigned int fmt) | |
395 | { | |
70091a3e | 396 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 397 | int ret = 0; |
6dfa9a4e | 398 | u32 data_delay; |
83f12503 | 399 | bool fs_pol_rising; |
ffd950f7 | 400 | bool inv_fs = false; |
b67f4487 | 401 | |
4a11ff26 PU |
402 | if (!fmt) |
403 | return 0; | |
404 | ||
1d17a04e | 405 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d | 406 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
188edc59 PU |
407 | case SND_SOC_DAIFMT_DSP_A: |
408 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
409 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
188edc59 PU |
410 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
411 | data_delay = 1; | |
412 | break; | |
5296cf2d DM |
413 | case SND_SOC_DAIFMT_DSP_B: |
414 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
415 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
416 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
417 | /* No delay after FS */ |
418 | data_delay = 0; | |
5296cf2d | 419 | break; |
ffd950f7 | 420 | case SND_SOC_DAIFMT_I2S: |
5296cf2d | 421 | /* configure a full-word SYNC pulse (LRCLK) */ |
f68205a7 PU |
422 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
423 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
424 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
425 | data_delay = 1; | |
ffd950f7 PU |
426 | /* FS need to be inverted */ |
427 | inv_fs = true; | |
5296cf2d | 428 | break; |
423761e0 PU |
429 | case SND_SOC_DAIFMT_LEFT_J: |
430 | /* configure a full-word SYNC pulse (LRCLK) */ | |
431 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
432 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
433 | /* No delay after FS */ | |
434 | data_delay = 0; | |
435 | break; | |
ffd950f7 PU |
436 | default: |
437 | ret = -EINVAL; | |
438 | goto out; | |
5296cf2d DM |
439 | } |
440 | ||
6dfa9a4e PU |
441 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), |
442 | FSXDLY(3)); | |
443 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), | |
444 | FSRDLY(3)); | |
445 | ||
b67f4487 C |
446 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
447 | case SND_SOC_DAIFMT_CBS_CFS: | |
448 | /* codec is clock and frame slave */ | |
f68205a7 PU |
449 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
450 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 451 | |
f68205a7 PU |
452 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
453 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 454 | |
f68205a7 PU |
455 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
456 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 457 | mcasp->bclk_master = 1; |
b67f4487 | 458 | break; |
226e2f1b PU |
459 | case SND_SOC_DAIFMT_CBS_CFM: |
460 | /* codec is clock slave and frame master */ | |
461 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); | |
462 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
463 | ||
464 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); | |
465 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
466 | ||
467 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); | |
468 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
469 | mcasp->bclk_master = 1; | |
470 | break; | |
517ee6cf C |
471 | case SND_SOC_DAIFMT_CBM_CFS: |
472 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
473 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
474 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 475 | |
f68205a7 PU |
476 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
477 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 478 | |
f68205a7 PU |
479 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
480 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 481 | mcasp->bclk_master = 0; |
517ee6cf | 482 | break; |
b67f4487 C |
483 | case SND_SOC_DAIFMT_CBM_CFM: |
484 | /* codec is clock and frame master */ | |
f68205a7 PU |
485 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
486 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 487 | |
f68205a7 PU |
488 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
489 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 490 | |
f68205a7 | 491 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
823ecdd6 | 492 | ACLKX | AFSX | ACLKR | AHCLKR | AFSR); |
ab8b14b6 | 493 | mcasp->bclk_master = 0; |
b67f4487 | 494 | break; |
b67f4487 | 495 | default: |
1d17a04e PU |
496 | ret = -EINVAL; |
497 | goto out; | |
b67f4487 C |
498 | } |
499 | ||
500 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
501 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 | 502 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 503 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 504 | fs_pol_rising = true; |
b67f4487 | 505 | break; |
b67f4487 | 506 | case SND_SOC_DAIFMT_NB_IF: |
f68205a7 | 507 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 508 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 509 | fs_pol_rising = false; |
b67f4487 | 510 | break; |
b67f4487 | 511 | case SND_SOC_DAIFMT_IB_IF: |
f68205a7 | 512 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 513 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 514 | fs_pol_rising = false; |
b67f4487 | 515 | break; |
b67f4487 | 516 | case SND_SOC_DAIFMT_NB_NF: |
f68205a7 | 517 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
f68205a7 | 518 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 519 | fs_pol_rising = true; |
b67f4487 | 520 | break; |
b67f4487 | 521 | default: |
1d17a04e | 522 | ret = -EINVAL; |
83f12503 PU |
523 | goto out; |
524 | } | |
525 | ||
ffd950f7 PU |
526 | if (inv_fs) |
527 | fs_pol_rising = !fs_pol_rising; | |
528 | ||
83f12503 PU |
529 | if (fs_pol_rising) { |
530 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
531 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
532 | } else { | |
533 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
534 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 | 535 | } |
4a11ff26 PU |
536 | |
537 | mcasp->dai_fmt = fmt; | |
1d17a04e | 538 | out: |
6afda7f5 | 539 | pm_runtime_put(mcasp->dev); |
1d17a04e | 540 | return ret; |
b67f4487 C |
541 | } |
542 | ||
226e73e2 | 543 | static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, |
8813543e | 544 | int div, bool explicit) |
4ed8c9b7 | 545 | { |
6afda7f5 | 546 | pm_runtime_get_sync(mcasp->dev); |
4ed8c9b7 | 547 | switch (div_id) { |
20d4b107 | 548 | case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ |
f68205a7 | 549 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 550 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 551 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
552 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
553 | break; | |
554 | ||
20d4b107 | 555 | case MCASP_CLKDIV_BCLK: /* BCLK divider */ |
f68205a7 | 556 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 557 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 558 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 | 559 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
8813543e JS |
560 | if (explicit) |
561 | mcasp->bclk_div = div; | |
4ed8c9b7 DM |
562 | break; |
563 | ||
20d4b107 PU |
564 | case MCASP_CLKDIV_BCLK_FS_RATIO: |
565 | /* | |
14a998be JS |
566 | * BCLK/LRCLK ratio descries how many bit-clock cycles |
567 | * fit into one frame. The clock ratio is given for a | |
568 | * full period of data (for I2S format both left and | |
569 | * right channels), so it has to be divided by number | |
570 | * of tdm-slots (for I2S - divided by 2). | |
571 | * Instead of storing this ratio, we calculate a new | |
572 | * tdm_slot width by dividing the the ratio by the | |
573 | * number of configured tdm slots. | |
574 | */ | |
575 | mcasp->slot_width = div / mcasp->tdm_slots; | |
576 | if (div % mcasp->tdm_slots) | |
577 | dev_warn(mcasp->dev, | |
578 | "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots", | |
579 | __func__, div, mcasp->tdm_slots); | |
1b3bc060 DM |
580 | break; |
581 | ||
4ed8c9b7 DM |
582 | default: |
583 | return -EINVAL; | |
584 | } | |
585 | ||
6afda7f5 | 586 | pm_runtime_put(mcasp->dev); |
4ed8c9b7 DM |
587 | return 0; |
588 | } | |
589 | ||
8813543e JS |
590 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
591 | int div) | |
592 | { | |
226e73e2 PU |
593 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
594 | ||
595 | return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); | |
8813543e JS |
596 | } |
597 | ||
5b66aa2d DM |
598 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
599 | unsigned int freq, int dir) | |
600 | { | |
70091a3e | 601 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d | 602 | |
6afda7f5 | 603 | pm_runtime_get_sync(mcasp->dev); |
5b66aa2d | 604 | if (dir == SND_SOC_CLOCK_OUT) { |
f68205a7 PU |
605 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
606 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
607 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 608 | } else { |
f68205a7 PU |
609 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
610 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
611 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
612 | } |
613 | ||
ab8b14b6 JS |
614 | mcasp->sysclk_freq = freq; |
615 | ||
6afda7f5 | 616 | pm_runtime_put(mcasp->dev); |
5b66aa2d DM |
617 | return 0; |
618 | } | |
619 | ||
dd55ff83 JS |
620 | /* All serializers must have equal number of channels */ |
621 | static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, | |
622 | int serializers) | |
623 | { | |
624 | struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; | |
625 | unsigned int *list = (unsigned int *) cl->list; | |
626 | int slots = mcasp->tdm_slots; | |
627 | int i, count = 0; | |
628 | ||
629 | if (mcasp->tdm_mask[stream]) | |
630 | slots = hweight32(mcasp->tdm_mask[stream]); | |
631 | ||
632 | for (i = 2; i <= slots; i++) | |
633 | list[count++] = i; | |
634 | ||
635 | for (i = 2; i <= serializers; i++) | |
636 | list[count++] = i*slots; | |
637 | ||
638 | cl->count = count; | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) | |
644 | { | |
645 | int rx_serializers = 0, tx_serializers = 0, ret, i; | |
646 | ||
647 | for (i = 0; i < mcasp->num_serializer; i++) | |
648 | if (mcasp->serial_dir[i] == TX_MODE) | |
649 | tx_serializers++; | |
650 | else if (mcasp->serial_dir[i] == RX_MODE) | |
651 | rx_serializers++; | |
652 | ||
653 | ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, | |
654 | tx_serializers); | |
655 | if (ret) | |
656 | return ret; | |
657 | ||
658 | ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, | |
659 | rx_serializers); | |
660 | ||
661 | return ret; | |
662 | } | |
663 | ||
664 | ||
665 | static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, | |
666 | unsigned int tx_mask, | |
667 | unsigned int rx_mask, | |
668 | int slots, int slot_width) | |
669 | { | |
670 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
671 | ||
672 | dev_dbg(mcasp->dev, | |
673 | "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", | |
674 | __func__, tx_mask, rx_mask, slots, slot_width); | |
675 | ||
676 | if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { | |
677 | dev_err(mcasp->dev, | |
678 | "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", | |
679 | tx_mask, rx_mask, slots); | |
680 | return -EINVAL; | |
681 | } | |
682 | ||
683 | if (slot_width && | |
684 | (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { | |
685 | dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", | |
686 | __func__, slot_width); | |
687 | return -EINVAL; | |
688 | } | |
689 | ||
690 | mcasp->tdm_slots = slots; | |
1bdd5932 AD |
691 | mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; |
692 | mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; | |
dd55ff83 JS |
693 | mcasp->slot_width = slot_width; |
694 | ||
695 | return davinci_mcasp_set_ch_constraints(mcasp); | |
696 | } | |
697 | ||
70091a3e | 698 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
14a998be | 699 | int sample_width) |
b67f4487 | 700 | { |
ba764b3d | 701 | u32 fmt; |
14a998be JS |
702 | u32 tx_rotate = (sample_width / 4) & 0x7; |
703 | u32 mask = (1ULL << sample_width) - 1; | |
704 | u32 slot_width = sample_width; | |
705 | ||
fe0a29e1 PU |
706 | /* |
707 | * For captured data we should not rotate, inversion and masking is | |
708 | * enoguh to get the data to the right position: | |
709 | * Format data from bus after reverse (XRBUF) | |
710 | * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| | |
711 | * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
712 | * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
713 | * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| | |
714 | */ | |
715 | u32 rx_rotate = 0; | |
b67f4487 | 716 | |
1b3bc060 | 717 | /* |
14a998be JS |
718 | * Setting the tdm slot width either with set_clkdiv() or |
719 | * set_tdm_slot() allows us to for example send 32 bits per | |
720 | * channel to the codec, while only 16 of them carry audio | |
721 | * payload. | |
1b3bc060 | 722 | */ |
14a998be | 723 | if (mcasp->slot_width) { |
d742b925 | 724 | /* |
14a998be JS |
725 | * When we have more bclk then it is needed for the |
726 | * data, we need to use the rotation to move the | |
727 | * received samples to have correct alignment. | |
d742b925 | 728 | */ |
14a998be JS |
729 | slot_width = mcasp->slot_width; |
730 | rx_rotate = (slot_width - sample_width) / 4; | |
d742b925 | 731 | } |
1b3bc060 | 732 | |
ba764b3d | 733 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
14a998be | 734 | fmt = (slot_width >> 1) - 1; |
b67f4487 | 735 | |
70091a3e | 736 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
737 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
738 | RXSSZ(0x0F)); | |
739 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
740 | TXSSZ(0x0F)); | |
741 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
742 | TXROT(7)); | |
743 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
744 | RXROT(7)); | |
745 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
746 | } |
747 | ||
f68205a7 | 748 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 749 | |
b67f4487 C |
750 | return 0; |
751 | } | |
752 | ||
662ffae9 | 753 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
dd093a0f | 754 | int period_words, int channels) |
b67f4487 | 755 | { |
5f04c603 | 756 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; |
b67f4487 | 757 | int i; |
6a99fb5f C |
758 | u8 tx_ser = 0; |
759 | u8 rx_ser = 0; | |
70091a3e | 760 | u8 slots = mcasp->tdm_slots; |
2952b27e | 761 | u8 max_active_serializers = (channels + slots - 1) / slots; |
72383192 | 762 | int active_serializers, numevt; |
487dce88 | 763 | u32 reg; |
b67f4487 | 764 | /* Default configuration */ |
40448e5e | 765 | if (mcasp->version < MCASP_VERSION_3) |
f68205a7 | 766 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
767 | |
768 | /* All PINS as McASP */ | |
f68205a7 | 769 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
770 | |
771 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
772 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
773 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 774 | } else { |
f68205a7 PU |
775 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
776 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
777 | } |
778 | ||
70091a3e | 779 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
780 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
781 | mcasp->serial_dir[i]); | |
70091a3e | 782 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 783 | tx_ser < max_active_serializers) { |
f68205a7 | 784 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
19db62ea MLC |
785 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
786 | DISMOD_LOW, DISMOD_MASK); | |
6a99fb5f | 787 | tx_ser++; |
70091a3e | 788 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 789 | rx_ser < max_active_serializers) { |
f68205a7 | 790 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 791 | rx_ser++; |
2952b27e | 792 | } else { |
f68205a7 PU |
793 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
794 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
795 | } |
796 | } | |
797 | ||
0bf0e8ae PU |
798 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
799 | active_serializers = tx_ser; | |
800 | numevt = mcasp->txnumevt; | |
801 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
802 | } else { | |
803 | active_serializers = rx_ser; | |
804 | numevt = mcasp->rxnumevt; | |
805 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
806 | } | |
ecf327c7 | 807 | |
0bf0e8ae | 808 | if (active_serializers < max_active_serializers) { |
70091a3e | 809 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
0bf0e8ae PU |
810 | "enabled in mcasp (%d)\n", channels, |
811 | active_serializers * slots); | |
ecf327c7 DM |
812 | return -EINVAL; |
813 | } | |
814 | ||
0bf0e8ae | 815 | /* AFIFO is not in use */ |
5f04c603 PU |
816 | if (!numevt) { |
817 | /* Configure the burst size for platform drivers */ | |
33445643 PU |
818 | if (active_serializers > 1) { |
819 | /* | |
820 | * If more than one serializers are in use we have one | |
821 | * DMA request to provide data for all serializers. | |
822 | * For example if three serializers are enabled the DMA | |
823 | * need to transfer three words per DMA request. | |
824 | */ | |
33445643 PU |
825 | dma_data->maxburst = active_serializers; |
826 | } else { | |
33445643 PU |
827 | dma_data->maxburst = 0; |
828 | } | |
0bf0e8ae | 829 | return 0; |
5f04c603 | 830 | } |
6a99fb5f | 831 | |
dd093a0f PU |
832 | if (period_words % active_serializers) { |
833 | dev_err(mcasp->dev, "Invalid combination of period words and " | |
834 | "active serializers: %d, %d\n", period_words, | |
835 | active_serializers); | |
836 | return -EINVAL; | |
837 | } | |
838 | ||
839 | /* | |
840 | * Calculate the optimal AFIFO depth for platform side: | |
841 | * The number of words for numevt need to be in steps of active | |
842 | * serializers. | |
843 | */ | |
72383192 PU |
844 | numevt = (numevt / active_serializers) * active_serializers; |
845 | ||
dd093a0f PU |
846 | while (period_words % numevt && numevt > 0) |
847 | numevt -= active_serializers; | |
848 | if (numevt <= 0) | |
0bf0e8ae | 849 | numevt = active_serializers; |
487dce88 | 850 | |
0bf0e8ae PU |
851 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
852 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); | |
2952b27e | 853 | |
5f04c603 | 854 | /* Configure the burst size for platform drivers */ |
33445643 PU |
855 | if (numevt == 1) |
856 | numevt = 0; | |
5f04c603 PU |
857 | dma_data->maxburst = numevt; |
858 | ||
2952b27e | 859 | return 0; |
b67f4487 C |
860 | } |
861 | ||
18a4f557 MLC |
862 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, |
863 | int channels) | |
b67f4487 C |
864 | { |
865 | int i, active_slots; | |
18a4f557 MLC |
866 | int total_slots; |
867 | int active_serializers; | |
b67f4487 | 868 | u32 mask = 0; |
cbc7956c | 869 | u32 busel = 0; |
b67f4487 | 870 | |
18a4f557 MLC |
871 | total_slots = mcasp->tdm_slots; |
872 | ||
873 | /* | |
874 | * If more than one serializer is needed, then use them with | |
dd55ff83 JS |
875 | * all the specified tdm_slots. Otherwise, one serializer can |
876 | * cope with the transaction using just as many slots as there | |
877 | * are channels in the stream. | |
18a4f557 | 878 | */ |
dd55ff83 JS |
879 | if (mcasp->tdm_mask[stream]) { |
880 | active_slots = hweight32(mcasp->tdm_mask[stream]); | |
881 | active_serializers = (channels + active_slots - 1) / | |
882 | active_slots; | |
883 | if (active_serializers == 1) { | |
884 | active_slots = channels; | |
885 | for (i = 0; i < total_slots; i++) { | |
886 | if ((1 << i) & mcasp->tdm_mask[stream]) { | |
887 | mask |= (1 << i); | |
888 | if (--active_slots <= 0) | |
889 | break; | |
890 | } | |
891 | } | |
892 | } | |
893 | } else { | |
894 | active_serializers = (channels + total_slots - 1) / total_slots; | |
895 | if (active_serializers == 1) | |
896 | active_slots = channels; | |
897 | else | |
898 | active_slots = total_slots; | |
b67f4487 | 899 | |
dd55ff83 JS |
900 | for (i = 0; i < active_slots; i++) |
901 | mask |= (1 << i); | |
902 | } | |
f68205a7 | 903 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 904 | |
cbc7956c PU |
905 | if (!mcasp->dat_port) |
906 | busel = TXSEL; | |
907 | ||
dd55ff83 JS |
908 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
909 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); | |
910 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
911 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
912 | FSXMOD(total_slots), FSXMOD(0x1FF)); | |
913 | } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { | |
914 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
915 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
916 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
917 | FSRMOD(total_slots), FSRMOD(0x1FF)); | |
0ad7d3a0 PU |
918 | /* |
919 | * If McASP is set to be TX/RX synchronous and the playback is | |
920 | * not running already we need to configure the TX slots in | |
921 | * order to have correct FSX on the bus | |
922 | */ | |
923 | if (mcasp_is_synchronous(mcasp) && !mcasp->channels) | |
924 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
925 | FSXMOD(total_slots), FSXMOD(0x1FF)); | |
dd55ff83 | 926 | } |
2c56c4c2 PU |
927 | |
928 | return 0; | |
b67f4487 C |
929 | } |
930 | ||
931 | /* S/PDIF */ | |
6479285d DM |
932 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, |
933 | unsigned int rate) | |
b67f4487 | 934 | { |
6479285d DM |
935 | u32 cs_value = 0; |
936 | u8 *cs_bytes = (u8*) &cs_value; | |
937 | ||
b67f4487 C |
938 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
939 | and LSB first */ | |
f68205a7 | 940 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
941 | |
942 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 943 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
944 | |
945 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 946 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
947 | |
948 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 949 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 950 | |
f68205a7 | 951 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
952 | |
953 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 954 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
955 | |
956 | /* Enable the DIT */ | |
f68205a7 | 957 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 | 958 | |
6479285d DM |
959 | /* Set S/PDIF channel status bits */ |
960 | cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; | |
961 | cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; | |
962 | ||
963 | switch (rate) { | |
964 | case 22050: | |
965 | cs_bytes[3] |= IEC958_AES3_CON_FS_22050; | |
966 | break; | |
967 | case 24000: | |
968 | cs_bytes[3] |= IEC958_AES3_CON_FS_24000; | |
969 | break; | |
970 | case 32000: | |
971 | cs_bytes[3] |= IEC958_AES3_CON_FS_32000; | |
972 | break; | |
973 | case 44100: | |
974 | cs_bytes[3] |= IEC958_AES3_CON_FS_44100; | |
975 | break; | |
976 | case 48000: | |
977 | cs_bytes[3] |= IEC958_AES3_CON_FS_48000; | |
978 | break; | |
979 | case 88200: | |
980 | cs_bytes[3] |= IEC958_AES3_CON_FS_88200; | |
981 | break; | |
982 | case 96000: | |
983 | cs_bytes[3] |= IEC958_AES3_CON_FS_96000; | |
984 | break; | |
985 | case 176400: | |
986 | cs_bytes[3] |= IEC958_AES3_CON_FS_176400; | |
987 | break; | |
988 | case 192000: | |
989 | cs_bytes[3] |= IEC958_AES3_CON_FS_192000; | |
990 | break; | |
991 | default: | |
992 | printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); | |
993 | return -EINVAL; | |
994 | } | |
995 | ||
996 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); | |
997 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); | |
998 | ||
2c56c4c2 | 999 | return 0; |
b67f4487 C |
1000 | } |
1001 | ||
a75a053f | 1002 | static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, |
3e9bee11 | 1003 | unsigned int bclk_freq, bool set) |
a75a053f | 1004 | { |
3e9bee11 | 1005 | int error_ppm; |
ddecd149 PU |
1006 | unsigned int sysclk_freq = mcasp->sysclk_freq; |
1007 | u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); | |
1008 | int div = sysclk_freq / bclk_freq; | |
1009 | int rem = sysclk_freq % bclk_freq; | |
1010 | int aux_div = 1; | |
1011 | ||
1012 | if (div > (ACLKXDIV_MASK + 1)) { | |
1013 | if (reg & AHCLKXE) { | |
1014 | aux_div = div / (ACLKXDIV_MASK + 1); | |
1015 | if (div % (ACLKXDIV_MASK + 1)) | |
1016 | aux_div++; | |
1017 | ||
1018 | sysclk_freq /= aux_div; | |
1019 | div = sysclk_freq / bclk_freq; | |
1020 | rem = sysclk_freq % bclk_freq; | |
1021 | } else if (set) { | |
1022 | dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", | |
1023 | sysclk_freq); | |
1024 | } | |
1025 | } | |
a75a053f JS |
1026 | |
1027 | if (rem != 0) { | |
1028 | if (div == 0 || | |
ddecd149 PU |
1029 | ((sysclk_freq / div) - bclk_freq) > |
1030 | (bclk_freq - (sysclk_freq / (div+1)))) { | |
a75a053f JS |
1031 | div++; |
1032 | rem = rem - bclk_freq; | |
1033 | } | |
1034 | } | |
3e9bee11 PU |
1035 | error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, |
1036 | (int)bclk_freq)) / div - 1000000; | |
a75a053f | 1037 | |
3e9bee11 PU |
1038 | if (set) { |
1039 | if (error_ppm) | |
1040 | dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", | |
1041 | error_ppm); | |
1042 | ||
1043 | __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0); | |
ddecd149 PU |
1044 | if (reg & AHCLKXE) |
1045 | __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK, | |
1046 | aux_div, 0); | |
3e9bee11 | 1047 | } |
a75a053f | 1048 | |
3e9bee11 | 1049 | return error_ppm; |
a75a053f JS |
1050 | } |
1051 | ||
b67f4487 C |
1052 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, |
1053 | struct snd_pcm_hw_params *params, | |
1054 | struct snd_soc_dai *cpu_dai) | |
1055 | { | |
70091a3e | 1056 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 1057 | int word_length; |
a7e46bd9 | 1058 | int channels = params_channels(params); |
dd093a0f | 1059 | int period_size = params_period_size(params); |
2c56c4c2 | 1060 | int ret; |
ab8b14b6 | 1061 | |
4a11ff26 PU |
1062 | ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); |
1063 | if (ret) | |
1064 | return ret; | |
1065 | ||
8267525c DM |
1066 | /* |
1067 | * If mcasp is BCLK master, and a BCLK divider was not provided by | |
1068 | * the machine driver, we need to calculate the ratio. | |
1069 | */ | |
1070 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
1f114f77 | 1071 | int slots = mcasp->tdm_slots; |
a75a053f JS |
1072 | int rate = params_rate(params); |
1073 | int sbits = params_width(params); | |
a75a053f | 1074 | |
dd55ff83 JS |
1075 | if (mcasp->slot_width) |
1076 | sbits = mcasp->slot_width; | |
1077 | ||
3e9bee11 | 1078 | davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true); |
ab8b14b6 JS |
1079 | } |
1080 | ||
dd093a0f PU |
1081 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
1082 | period_size * channels, channels); | |
0f7d9a63 PU |
1083 | if (ret) |
1084 | return ret; | |
1085 | ||
70091a3e | 1086 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
6479285d | 1087 | ret = mcasp_dit_hw_param(mcasp, params_rate(params)); |
b67f4487 | 1088 | else |
18a4f557 MLC |
1089 | ret = mcasp_i2s_hw_param(mcasp, substream->stream, |
1090 | channels); | |
2c56c4c2 PU |
1091 | |
1092 | if (ret) | |
1093 | return ret; | |
b67f4487 C |
1094 | |
1095 | switch (params_format(params)) { | |
0a9d1385 | 1096 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 | 1097 | case SNDRV_PCM_FORMAT_S8: |
ba764b3d | 1098 | word_length = 8; |
b67f4487 C |
1099 | break; |
1100 | ||
0a9d1385 | 1101 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 | 1102 | case SNDRV_PCM_FORMAT_S16_LE: |
ba764b3d | 1103 | word_length = 16; |
b67f4487 C |
1104 | break; |
1105 | ||
21eb24d8 DM |
1106 | case SNDRV_PCM_FORMAT_U24_3LE: |
1107 | case SNDRV_PCM_FORMAT_S24_3LE: | |
ba764b3d | 1108 | word_length = 24; |
21eb24d8 DM |
1109 | break; |
1110 | ||
6b7fa011 DM |
1111 | case SNDRV_PCM_FORMAT_U24_LE: |
1112 | case SNDRV_PCM_FORMAT_S24_LE: | |
182bef86 PU |
1113 | word_length = 24; |
1114 | break; | |
1115 | ||
0a9d1385 | 1116 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 | 1117 | case SNDRV_PCM_FORMAT_S32_LE: |
ba764b3d | 1118 | word_length = 32; |
b67f4487 C |
1119 | break; |
1120 | ||
1121 | default: | |
1122 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
1123 | return -EINVAL; | |
1124 | } | |
6a99fb5f | 1125 | |
70091a3e | 1126 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 | 1127 | |
11277833 PU |
1128 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) |
1129 | mcasp->channels = channels; | |
1130 | ||
b67f4487 C |
1131 | return 0; |
1132 | } | |
1133 | ||
1134 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
1135 | int cmd, struct snd_soc_dai *cpu_dai) | |
1136 | { | |
70091a3e | 1137 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
1138 | int ret = 0; |
1139 | ||
1140 | switch (cmd) { | |
b67f4487 | 1141 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
1142 | case SNDRV_PCM_TRIGGER_START: |
1143 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 1144 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 1145 | break; |
b67f4487 | 1146 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 1147 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 1148 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 1149 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
1150 | break; |
1151 | ||
1152 | default: | |
1153 | ret = -EINVAL; | |
1154 | } | |
1155 | ||
1156 | return ret; | |
1157 | } | |
1158 | ||
a75a053f JS |
1159 | static const unsigned int davinci_mcasp_dai_rates[] = { |
1160 | 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, | |
1161 | 88200, 96000, 176400, 192000, | |
1162 | }; | |
1163 | ||
1164 | #define DAVINCI_MAX_RATE_ERROR_PPM 1000 | |
1165 | ||
1166 | static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, | |
1167 | struct snd_pcm_hw_rule *rule) | |
1168 | { | |
1169 | struct davinci_mcasp_ruledata *rd = rule->private; | |
1170 | struct snd_interval *ri = | |
1171 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1172 | int sbits = params_width(params); | |
1f114f77 | 1173 | int slots = rd->mcasp->tdm_slots; |
518f6bab JS |
1174 | struct snd_interval range; |
1175 | int i; | |
a75a053f | 1176 | |
dd55ff83 JS |
1177 | if (rd->mcasp->slot_width) |
1178 | sbits = rd->mcasp->slot_width; | |
1179 | ||
518f6bab JS |
1180 | snd_interval_any(&range); |
1181 | range.empty = 1; | |
a75a053f JS |
1182 | |
1183 | for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { | |
518f6bab | 1184 | if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { |
1f114f77 | 1185 | uint bclk_freq = sbits*slots* |
a75a053f JS |
1186 | davinci_mcasp_dai_rates[i]; |
1187 | int ppm; | |
1188 | ||
3e9bee11 PU |
1189 | ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, |
1190 | false); | |
518f6bab JS |
1191 | if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { |
1192 | if (range.empty) { | |
1193 | range.min = davinci_mcasp_dai_rates[i]; | |
1194 | range.empty = 0; | |
1195 | } | |
1196 | range.max = davinci_mcasp_dai_rates[i]; | |
1197 | } | |
a75a053f JS |
1198 | } |
1199 | } | |
518f6bab | 1200 | |
a75a053f | 1201 | dev_dbg(rd->mcasp->dev, |
518f6bab JS |
1202 | "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", |
1203 | ri->min, ri->max, range.min, range.max, sbits, slots); | |
a75a053f | 1204 | |
518f6bab JS |
1205 | return snd_interval_refine(hw_param_interval(params, rule->var), |
1206 | &range); | |
a75a053f JS |
1207 | } |
1208 | ||
1209 | static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, | |
1210 | struct snd_pcm_hw_rule *rule) | |
1211 | { | |
1212 | struct davinci_mcasp_ruledata *rd = rule->private; | |
1213 | struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); | |
1214 | struct snd_mask nfmt; | |
1215 | int rate = params_rate(params); | |
1f114f77 | 1216 | int slots = rd->mcasp->tdm_slots; |
a75a053f JS |
1217 | int i, count = 0; |
1218 | ||
1219 | snd_mask_none(&nfmt); | |
1220 | ||
a75a053f JS |
1221 | for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) { |
1222 | if (snd_mask_test(fmt, i)) { | |
dd55ff83 | 1223 | uint sbits = snd_pcm_format_width(i); |
a75a053f JS |
1224 | int ppm; |
1225 | ||
dd55ff83 JS |
1226 | if (rd->mcasp->slot_width) |
1227 | sbits = rd->mcasp->slot_width; | |
1228 | ||
3e9bee11 PU |
1229 | ppm = davinci_mcasp_calc_clk_div(rd->mcasp, |
1230 | sbits * slots * rate, | |
1231 | false); | |
a75a053f JS |
1232 | if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { |
1233 | snd_mask_set(&nfmt, i); | |
1234 | count++; | |
1235 | } | |
1236 | } | |
1237 | } | |
1238 | dev_dbg(rd->mcasp->dev, | |
1f114f77 JS |
1239 | "%d possible sample format for %d Hz and %d tdm slots\n", |
1240 | count, rate, slots); | |
a75a053f JS |
1241 | |
1242 | return snd_mask_refine(fmt, &nfmt); | |
1243 | } | |
1244 | ||
11277833 PU |
1245 | static int davinci_mcasp_startup(struct snd_pcm_substream *substream, |
1246 | struct snd_soc_dai *cpu_dai) | |
1247 | { | |
1248 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
4cd9db08 PU |
1249 | struct davinci_mcasp_ruledata *ruledata = |
1250 | &mcasp->ruledata[substream->stream]; | |
11277833 PU |
1251 | u32 max_channels = 0; |
1252 | int i, dir; | |
dd55ff83 JS |
1253 | int tdm_slots = mcasp->tdm_slots; |
1254 | ||
19357366 PU |
1255 | /* Do not allow more then one stream per direction */ |
1256 | if (mcasp->substreams[substream->stream]) | |
1257 | return -EBUSY; | |
11277833 | 1258 | |
a7a3324a MLC |
1259 | mcasp->substreams[substream->stream] = substream; |
1260 | ||
19357366 PU |
1261 | if (mcasp->tdm_mask[substream->stream]) |
1262 | tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); | |
1263 | ||
11277833 PU |
1264 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
1265 | return 0; | |
1266 | ||
1267 | /* | |
1268 | * Limit the maximum allowed channels for the first stream: | |
1269 | * number of serializers for the direction * tdm slots per serializer | |
1270 | */ | |
1271 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1272 | dir = TX_MODE; | |
1273 | else | |
1274 | dir = RX_MODE; | |
1275 | ||
1276 | for (i = 0; i < mcasp->num_serializer; i++) { | |
1277 | if (mcasp->serial_dir[i] == dir) | |
1278 | max_channels++; | |
1279 | } | |
4cd9db08 | 1280 | ruledata->serializers = max_channels; |
dd55ff83 | 1281 | max_channels *= tdm_slots; |
11277833 PU |
1282 | /* |
1283 | * If the already active stream has less channels than the calculated | |
1284 | * limnit based on the seirializers * tdm_slots, we need to use that as | |
1285 | * a constraint for the second stream. | |
1286 | * Otherwise (first stream or less allowed channels) we use the | |
1287 | * calculated constraint. | |
1288 | */ | |
1289 | if (mcasp->channels && mcasp->channels < max_channels) | |
1290 | max_channels = mcasp->channels; | |
dd55ff83 JS |
1291 | /* |
1292 | * But we can always allow channels upto the amount of | |
1293 | * the available tdm_slots. | |
1294 | */ | |
1295 | if (max_channels < tdm_slots) | |
1296 | max_channels = tdm_slots; | |
11277833 PU |
1297 | |
1298 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1299 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1300 | 2, max_channels); | |
a75a053f | 1301 | |
dd55ff83 JS |
1302 | snd_pcm_hw_constraint_list(substream->runtime, |
1303 | 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
1304 | &mcasp->chconstr[substream->stream]); | |
1305 | ||
1306 | if (mcasp->slot_width) | |
1307 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1308 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
1309 | 8, mcasp->slot_width); | |
5935a056 | 1310 | |
a75a053f JS |
1311 | /* |
1312 | * If we rely on implicit BCLK divider setting we should | |
1313 | * set constraints based on what we can provide. | |
1314 | */ | |
1315 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
1316 | int ret; | |
1317 | ||
4cd9db08 | 1318 | ruledata->mcasp = mcasp; |
a75a053f JS |
1319 | |
1320 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
1321 | SNDRV_PCM_HW_PARAM_RATE, | |
1322 | davinci_mcasp_hw_rule_rate, | |
4cd9db08 | 1323 | ruledata, |
1f114f77 | 1324 | SNDRV_PCM_HW_PARAM_FORMAT, -1); |
a75a053f JS |
1325 | if (ret) |
1326 | return ret; | |
1327 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
1328 | SNDRV_PCM_HW_PARAM_FORMAT, | |
1329 | davinci_mcasp_hw_rule_format, | |
4cd9db08 | 1330 | ruledata, |
1f114f77 | 1331 | SNDRV_PCM_HW_PARAM_RATE, -1); |
a75a053f JS |
1332 | if (ret) |
1333 | return ret; | |
1334 | } | |
1335 | ||
11277833 PU |
1336 | return 0; |
1337 | } | |
1338 | ||
1339 | static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, | |
1340 | struct snd_soc_dai *cpu_dai) | |
1341 | { | |
1342 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
1343 | ||
a7a3324a MLC |
1344 | mcasp->substreams[substream->stream] = NULL; |
1345 | ||
11277833 PU |
1346 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
1347 | return; | |
1348 | ||
1349 | if (!cpu_dai->active) | |
1350 | mcasp->channels = 0; | |
1351 | } | |
1352 | ||
85e7652d | 1353 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
11277833 PU |
1354 | .startup = davinci_mcasp_startup, |
1355 | .shutdown = davinci_mcasp_shutdown, | |
b67f4487 C |
1356 | .trigger = davinci_mcasp_trigger, |
1357 | .hw_params = davinci_mcasp_hw_params, | |
1358 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 1359 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 1360 | .set_sysclk = davinci_mcasp_set_sysclk, |
dd55ff83 | 1361 | .set_tdm_slot = davinci_mcasp_set_tdm_slot, |
b67f4487 C |
1362 | }; |
1363 | ||
d5902f69 PU |
1364 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
1365 | { | |
1366 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
1367 | ||
9759e7ef PU |
1368 | dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
1369 | dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
d5902f69 PU |
1370 | |
1371 | return 0; | |
1372 | } | |
1373 | ||
135014ad PU |
1374 | #ifdef CONFIG_PM_SLEEP |
1375 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
1376 | { | |
1377 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1378 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1379 | u32 reg; |
1cc0c054 | 1380 | int i; |
135014ad | 1381 | |
27796e75 | 1382 | context->pm_state = pm_runtime_active(mcasp->dev); |
6afda7f5 PU |
1383 | if (!context->pm_state) |
1384 | pm_runtime_get_sync(mcasp->dev); | |
1385 | ||
1cc0c054 PU |
1386 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1387 | context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); | |
135014ad | 1388 | |
f114ce60 PU |
1389 | if (mcasp->txnumevt) { |
1390 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1391 | context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); | |
1392 | } | |
1393 | if (mcasp->rxnumevt) { | |
1394 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1395 | context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); | |
1396 | } | |
135014ad | 1397 | |
f114ce60 PU |
1398 | for (i = 0; i < mcasp->num_serializer; i++) |
1399 | context->xrsr_regs[i] = mcasp_get_reg(mcasp, | |
1400 | DAVINCI_MCASP_XRSRCTL_REG(i)); | |
135014ad | 1401 | |
6afda7f5 PU |
1402 | pm_runtime_put_sync(mcasp->dev); |
1403 | ||
135014ad PU |
1404 | return 0; |
1405 | } | |
1406 | ||
1407 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
1408 | { | |
1409 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1410 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1411 | u32 reg; |
1cc0c054 | 1412 | int i; |
790bb94b | 1413 | |
6afda7f5 PU |
1414 | pm_runtime_get_sync(mcasp->dev); |
1415 | ||
1cc0c054 PU |
1416 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1417 | mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); | |
135014ad | 1418 | |
f114ce60 PU |
1419 | if (mcasp->txnumevt) { |
1420 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1421 | mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); | |
1422 | } | |
1423 | if (mcasp->rxnumevt) { | |
1424 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1425 | mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); | |
1426 | } | |
790bb94b | 1427 | |
f114ce60 PU |
1428 | for (i = 0; i < mcasp->num_serializer; i++) |
1429 | mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), | |
1430 | context->xrsr_regs[i]); | |
135014ad | 1431 | |
6afda7f5 PU |
1432 | if (!context->pm_state) |
1433 | pm_runtime_put_sync(mcasp->dev); | |
1434 | ||
135014ad PU |
1435 | return 0; |
1436 | } | |
1437 | #else | |
1438 | #define davinci_mcasp_suspend NULL | |
1439 | #define davinci_mcasp_resume NULL | |
1440 | #endif | |
1441 | ||
ed29cd5e PU |
1442 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
1443 | ||
0a9d1385 BG |
1444 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
1445 | SNDRV_PCM_FMTBIT_U8 | \ | |
1446 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
1447 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
1448 | SNDRV_PCM_FMTBIT_S24_LE | \ |
1449 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
1450 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
1451 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
1452 | SNDRV_PCM_FMTBIT_S32_LE | \ |
1453 | SNDRV_PCM_FMTBIT_U32_LE) | |
1454 | ||
f0fba2ad | 1455 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 1456 | { |
f0fba2ad | 1457 | .name = "davinci-mcasp.0", |
d5902f69 | 1458 | .probe = davinci_mcasp_dai_probe, |
135014ad PU |
1459 | .suspend = davinci_mcasp_suspend, |
1460 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
1461 | .playback = { |
1462 | .channels_min = 2, | |
2952b27e | 1463 | .channels_max = 32 * 16, |
b67f4487 | 1464 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1465 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1466 | }, |
1467 | .capture = { | |
1468 | .channels_min = 2, | |
2952b27e | 1469 | .channels_max = 32 * 16, |
b67f4487 | 1470 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1471 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1472 | }, |
1473 | .ops = &davinci_mcasp_dai_ops, | |
1474 | ||
d75249f5 | 1475 | .symmetric_samplebits = 1, |
295c3405 | 1476 | .symmetric_rates = 1, |
b67f4487 C |
1477 | }, |
1478 | { | |
58e48d97 | 1479 | .name = "davinci-mcasp.1", |
d5902f69 | 1480 | .probe = davinci_mcasp_dai_probe, |
b67f4487 C |
1481 | .playback = { |
1482 | .channels_min = 1, | |
1483 | .channels_max = 384, | |
1484 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 1485 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1486 | }, |
1487 | .ops = &davinci_mcasp_dai_ops, | |
1488 | }, | |
1489 | ||
1490 | }; | |
b67f4487 | 1491 | |
eeef0eda KM |
1492 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
1493 | .name = "davinci-mcasp", | |
1494 | }; | |
1495 | ||
256ba181 | 1496 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 1497 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
1498 | .tx_dma_offset = 0x400, |
1499 | .rx_dma_offset = 0x400, | |
256ba181 JS |
1500 | .version = MCASP_VERSION_1, |
1501 | }; | |
1502 | ||
d1debafc | 1503 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
1504 | .tx_dma_offset = 0x2000, |
1505 | .rx_dma_offset = 0x2000, | |
256ba181 JS |
1506 | .version = MCASP_VERSION_2, |
1507 | }; | |
1508 | ||
d1debafc | 1509 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
1510 | .tx_dma_offset = 0, |
1511 | .rx_dma_offset = 0, | |
256ba181 JS |
1512 | .version = MCASP_VERSION_3, |
1513 | }; | |
1514 | ||
d1debafc | 1515 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
8e1cc0e4 PU |
1516 | /* The CFG port offset will be calculated if it is needed */ |
1517 | .tx_dma_offset = 0, | |
1518 | .rx_dma_offset = 0, | |
453c4990 PU |
1519 | .version = MCASP_VERSION_4, |
1520 | }; | |
1521 | ||
3e3b8c34 HG |
1522 | static const struct of_device_id mcasp_dt_ids[] = { |
1523 | { | |
1524 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 1525 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
1526 | }, |
1527 | { | |
1528 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 1529 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 1530 | }, |
e5ec69da | 1531 | { |
3af9e031 | 1532 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 1533 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 1534 | }, |
453c4990 PU |
1535 | { |
1536 | .compatible = "ti,dra7-mcasp-audio", | |
1537 | .data = &dra7_mcasp_pdata, | |
1538 | }, | |
3e3b8c34 HG |
1539 | { /* sentinel */ } |
1540 | }; | |
1541 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
1542 | ||
ae726e93 PU |
1543 | static int mcasp_reparent_fck(struct platform_device *pdev) |
1544 | { | |
1545 | struct device_node *node = pdev->dev.of_node; | |
1546 | struct clk *gfclk, *parent_clk; | |
1547 | const char *parent_name; | |
1548 | int ret; | |
1549 | ||
1550 | if (!node) | |
1551 | return 0; | |
1552 | ||
1553 | parent_name = of_get_property(node, "fck_parent", NULL); | |
1554 | if (!parent_name) | |
1555 | return 0; | |
1556 | ||
c670254f PU |
1557 | dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); |
1558 | ||
ae726e93 PU |
1559 | gfclk = clk_get(&pdev->dev, "fck"); |
1560 | if (IS_ERR(gfclk)) { | |
1561 | dev_err(&pdev->dev, "failed to get fck\n"); | |
1562 | return PTR_ERR(gfclk); | |
1563 | } | |
1564 | ||
1565 | parent_clk = clk_get(NULL, parent_name); | |
1566 | if (IS_ERR(parent_clk)) { | |
1567 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
1568 | ret = PTR_ERR(parent_clk); | |
1569 | goto err1; | |
1570 | } | |
1571 | ||
1572 | ret = clk_set_parent(gfclk, parent_clk); | |
1573 | if (ret) { | |
1574 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
1575 | goto err2; | |
1576 | } | |
1577 | ||
1578 | err2: | |
1579 | clk_put(parent_clk); | |
1580 | err1: | |
1581 | clk_put(gfclk); | |
1582 | return ret; | |
1583 | } | |
1584 | ||
d1debafc | 1585 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
1586 | struct platform_device *pdev) |
1587 | { | |
1588 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 1589 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 1590 | const struct of_device_id *match = |
ea421eb1 | 1591 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 1592 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
1593 | |
1594 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
1595 | u32 val; |
1596 | int i, ret = 0; | |
1597 | ||
1598 | if (pdev->dev.platform_data) { | |
1599 | pdata = pdev->dev.platform_data; | |
1600 | return pdata; | |
1601 | } else if (match) { | |
d1debafc | 1602 | pdata = (struct davinci_mcasp_pdata*) match->data; |
3e3b8c34 HG |
1603 | } else { |
1604 | /* control shouldn't reach here. something is wrong */ | |
1605 | ret = -EINVAL; | |
1606 | goto nodata; | |
1607 | } | |
1608 | ||
3e3b8c34 HG |
1609 | ret = of_property_read_u32(np, "op-mode", &val); |
1610 | if (ret >= 0) | |
1611 | pdata->op_mode = val; | |
1612 | ||
1613 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
1614 | if (ret >= 0) { |
1615 | if (val < 2 || val > 32) { | |
1616 | dev_err(&pdev->dev, | |
1617 | "tdm-slots must be in rage [2-32]\n"); | |
1618 | ret = -EINVAL; | |
1619 | goto nodata; | |
1620 | } | |
1621 | ||
3e3b8c34 | 1622 | pdata->tdm_slots = val; |
2952b27e | 1623 | } |
3e3b8c34 | 1624 | |
3e3b8c34 HG |
1625 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
1626 | val /= sizeof(u32); | |
3e3b8c34 | 1627 | if (of_serial_dir32) { |
1427e660 PU |
1628 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
1629 | (sizeof(*of_serial_dir) * val), | |
1630 | GFP_KERNEL); | |
3e3b8c34 HG |
1631 | if (!of_serial_dir) { |
1632 | ret = -ENOMEM; | |
1633 | goto nodata; | |
1634 | } | |
1635 | ||
1427e660 | 1636 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
1637 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
1638 | ||
1427e660 | 1639 | pdata->num_serializer = val; |
3e3b8c34 HG |
1640 | pdata->serial_dir = of_serial_dir; |
1641 | } | |
1642 | ||
4023fe6f JS |
1643 | ret = of_property_match_string(np, "dma-names", "tx"); |
1644 | if (ret < 0) | |
1645 | goto nodata; | |
1646 | ||
1647 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1648 | &dma_spec); | |
1649 | if (ret < 0) | |
1650 | goto nodata; | |
1651 | ||
1652 | pdata->tx_dma_channel = dma_spec.args[0]; | |
1653 | ||
caa1d794 PU |
1654 | /* RX is not valid in DIT mode */ |
1655 | if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) { | |
1656 | ret = of_property_match_string(np, "dma-names", "rx"); | |
1657 | if (ret < 0) | |
1658 | goto nodata; | |
4023fe6f | 1659 | |
caa1d794 PU |
1660 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, |
1661 | &dma_spec); | |
1662 | if (ret < 0) | |
1663 | goto nodata; | |
4023fe6f | 1664 | |
caa1d794 PU |
1665 | pdata->rx_dma_channel = dma_spec.args[0]; |
1666 | } | |
4023fe6f | 1667 | |
3e3b8c34 HG |
1668 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1669 | if (ret >= 0) | |
1670 | pdata->txnumevt = val; | |
1671 | ||
1672 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1673 | if (ret >= 0) | |
1674 | pdata->rxnumevt = val; | |
1675 | ||
1676 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1677 | if (ret >= 0) | |
1678 | pdata->sram_size_playback = val; | |
1679 | ||
1680 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1681 | if (ret >= 0) | |
1682 | pdata->sram_size_capture = val; | |
1683 | ||
1684 | return pdata; | |
1685 | ||
1686 | nodata: | |
1687 | if (ret < 0) { | |
1688 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1689 | ret); | |
1690 | pdata = NULL; | |
1691 | } | |
1692 | return pdata; | |
1693 | } | |
1694 | ||
9fbd58cf JS |
1695 | enum { |
1696 | PCM_EDMA, | |
1697 | PCM_SDMA, | |
1698 | }; | |
1699 | static const char *sdma_prefix = "ti,omap"; | |
1700 | ||
1701 | static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) | |
1702 | { | |
1703 | struct dma_chan *chan; | |
1704 | const char *tmp; | |
1705 | int ret = PCM_EDMA; | |
1706 | ||
1707 | if (!mcasp->dev->of_node) | |
1708 | return PCM_EDMA; | |
1709 | ||
1710 | tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; | |
1711 | chan = dma_request_slave_channel_reason(mcasp->dev, tmp); | |
1712 | if (IS_ERR(chan)) { | |
1713 | if (PTR_ERR(chan) != -EPROBE_DEFER) | |
1714 | dev_err(mcasp->dev, | |
1715 | "Can't verify DMA configuration (%ld)\n", | |
1716 | PTR_ERR(chan)); | |
1717 | return PTR_ERR(chan); | |
1718 | } | |
1719 | BUG_ON(!chan->device || !chan->device->dev); | |
1720 | ||
1721 | if (chan->device->dev->of_node) | |
1722 | ret = of_property_read_string(chan->device->dev->of_node, | |
1723 | "compatible", &tmp); | |
1724 | else | |
1725 | dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); | |
1726 | ||
1727 | dma_release_channel(chan); | |
1728 | if (ret) | |
1729 | return ret; | |
1730 | ||
1731 | dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); | |
1732 | if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) | |
1733 | return PCM_SDMA; | |
1734 | ||
1735 | return PCM_EDMA; | |
1736 | } | |
1737 | ||
8e1cc0e4 PU |
1738 | static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) |
1739 | { | |
1740 | int i; | |
1741 | u32 offset = 0; | |
1742 | ||
1743 | if (pdata->version != MCASP_VERSION_4) | |
1744 | return pdata->tx_dma_offset; | |
1745 | ||
1746 | for (i = 0; i < pdata->num_serializer; i++) { | |
1747 | if (pdata->serial_dir[i] == TX_MODE) { | |
1748 | if (!offset) { | |
1749 | offset = DAVINCI_MCASP_TXBUF_REG(i); | |
1750 | } else { | |
1751 | pr_err("%s: Only one serializer allowed!\n", | |
1752 | __func__); | |
1753 | break; | |
1754 | } | |
1755 | } | |
1756 | } | |
1757 | ||
1758 | return offset; | |
1759 | } | |
1760 | ||
1761 | static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) | |
1762 | { | |
1763 | int i; | |
1764 | u32 offset = 0; | |
1765 | ||
1766 | if (pdata->version != MCASP_VERSION_4) | |
1767 | return pdata->rx_dma_offset; | |
1768 | ||
1769 | for (i = 0; i < pdata->num_serializer; i++) { | |
1770 | if (pdata->serial_dir[i] == RX_MODE) { | |
1771 | if (!offset) { | |
1772 | offset = DAVINCI_MCASP_RXBUF_REG(i); | |
1773 | } else { | |
1774 | pr_err("%s: Only one serializer allowed!\n", | |
1775 | __func__); | |
1776 | break; | |
1777 | } | |
1778 | } | |
1779 | } | |
1780 | ||
1781 | return offset; | |
1782 | } | |
1783 | ||
b67f4487 C |
1784 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1785 | { | |
8de131f2 | 1786 | struct snd_dmaengine_dai_dma_data *dma_data; |
508a43fd | 1787 | struct resource *mem, *res, *dat; |
d1debafc | 1788 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1789 | struct davinci_mcasp *mcasp; |
a7a3324a | 1790 | char *irq_name; |
9759e7ef | 1791 | int *dma; |
a7a3324a | 1792 | int irq; |
96d31e2b | 1793 | int ret; |
b67f4487 | 1794 | |
3e3b8c34 HG |
1795 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1796 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1797 | return -EINVAL; | |
1798 | } | |
1799 | ||
70091a3e | 1800 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1801 | GFP_KERNEL); |
70091a3e | 1802 | if (!mcasp) |
b67f4487 C |
1803 | return -ENOMEM; |
1804 | ||
3e3b8c34 HG |
1805 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1806 | if (!pdata) { | |
1807 | dev_err(&pdev->dev, "no platform data\n"); | |
1808 | return -EINVAL; | |
1809 | } | |
1810 | ||
256ba181 | 1811 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1812 | if (!mem) { |
70091a3e | 1813 | dev_warn(mcasp->dev, |
256ba181 JS |
1814 | "\"mpu\" mem resource not found, using index 0\n"); |
1815 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1816 | if (!mem) { | |
1817 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1818 | return -ENODEV; | |
1819 | } | |
b67f4487 C |
1820 | } |
1821 | ||
508a43fd AL |
1822 | mcasp->base = devm_ioremap_resource(&pdev->dev, mem); |
1823 | if (IS_ERR(mcasp->base)) | |
1824 | return PTR_ERR(mcasp->base); | |
b67f4487 | 1825 | |
10884347 | 1826 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1827 | |
70091a3e | 1828 | mcasp->op_mode = pdata->op_mode; |
1a5923da PU |
1829 | /* sanity check for tdm slots parameter */ |
1830 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { | |
1831 | if (pdata->tdm_slots < 2) { | |
1832 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1833 | pdata->tdm_slots); | |
1834 | mcasp->tdm_slots = 2; | |
1835 | } else if (pdata->tdm_slots > 32) { | |
1836 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1837 | pdata->tdm_slots); | |
1838 | mcasp->tdm_slots = 32; | |
1839 | } else { | |
1840 | mcasp->tdm_slots = pdata->tdm_slots; | |
1841 | } | |
1842 | } | |
1843 | ||
70091a3e | 1844 | mcasp->num_serializer = pdata->num_serializer; |
f114ce60 PU |
1845 | #ifdef CONFIG_PM_SLEEP |
1846 | mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev, | |
1847 | sizeof(u32) * mcasp->num_serializer, | |
1848 | GFP_KERNEL); | |
1849 | #endif | |
70091a3e PU |
1850 | mcasp->serial_dir = pdata->serial_dir; |
1851 | mcasp->version = pdata->version; | |
1852 | mcasp->txnumevt = pdata->txnumevt; | |
1853 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1854 | |
70091a3e | 1855 | mcasp->dev = &pdev->dev; |
b67f4487 | 1856 | |
5a1b8a80 PU |
1857 | irq = platform_get_irq_byname(pdev, "common"); |
1858 | if (irq >= 0) { | |
ab1fffe3 | 1859 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", |
5a1b8a80 PU |
1860 | dev_name(&pdev->dev)); |
1861 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1862 | davinci_mcasp_common_irq_handler, | |
8f511ffb PU |
1863 | IRQF_ONESHOT | IRQF_SHARED, |
1864 | irq_name, mcasp); | |
5a1b8a80 PU |
1865 | if (ret) { |
1866 | dev_err(&pdev->dev, "common IRQ request failed\n"); | |
1867 | goto err; | |
1868 | } | |
1869 | ||
1870 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
1871 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
1872 | } | |
1873 | ||
a7a3324a MLC |
1874 | irq = platform_get_irq_byname(pdev, "rx"); |
1875 | if (irq >= 0) { | |
ab1fffe3 | 1876 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", |
a7a3324a MLC |
1877 | dev_name(&pdev->dev)); |
1878 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1879 | davinci_mcasp_rx_irq_handler, | |
1880 | IRQF_ONESHOT, irq_name, mcasp); | |
1881 | if (ret) { | |
1882 | dev_err(&pdev->dev, "RX IRQ request failed\n"); | |
1883 | goto err; | |
1884 | } | |
1885 | ||
1886 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
1887 | } | |
1888 | ||
1889 | irq = platform_get_irq_byname(pdev, "tx"); | |
1890 | if (irq >= 0) { | |
ab1fffe3 | 1891 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", |
a7a3324a MLC |
1892 | dev_name(&pdev->dev)); |
1893 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1894 | davinci_mcasp_tx_irq_handler, | |
1895 | IRQF_ONESHOT, irq_name, mcasp); | |
1896 | if (ret) { | |
1897 | dev_err(&pdev->dev, "TX IRQ request failed\n"); | |
1898 | goto err; | |
1899 | } | |
1900 | ||
1901 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
1902 | } | |
1903 | ||
256ba181 | 1904 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1905 | if (dat) |
1906 | mcasp->dat_port = true; | |
256ba181 | 1907 | |
8de131f2 | 1908 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
cbc7956c | 1909 | if (dat) |
9759e7ef | 1910 | dma_data->addr = dat->start; |
cbc7956c | 1911 | else |
8e1cc0e4 | 1912 | dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata); |
453c4990 | 1913 | |
9759e7ef | 1914 | dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; |
b67f4487 | 1915 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 1916 | if (res) |
9759e7ef | 1917 | *dma = res->start; |
4023fe6f | 1918 | else |
9759e7ef | 1919 | *dma = pdata->tx_dma_channel; |
92e2a6f6 | 1920 | |
8de131f2 PU |
1921 | /* dmaengine filter data for DT and non-DT boot */ |
1922 | if (pdev->dev.of_node) | |
1923 | dma_data->filter_data = "tx"; | |
1924 | else | |
9759e7ef | 1925 | dma_data->filter_data = dma; |
8de131f2 | 1926 | |
caa1d794 PU |
1927 | /* RX is not valid in DIT mode */ |
1928 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { | |
caa1d794 | 1929 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
caa1d794 | 1930 | if (dat) |
9759e7ef | 1931 | dma_data->addr = dat->start; |
caa1d794 | 1932 | else |
8e1cc0e4 PU |
1933 | dma_data->addr = |
1934 | mem->start + davinci_mcasp_rxdma_offset(pdata); | |
caa1d794 | 1935 | |
9759e7ef | 1936 | dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; |
caa1d794 PU |
1937 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
1938 | if (res) | |
9759e7ef | 1939 | *dma = res->start; |
caa1d794 | 1940 | else |
9759e7ef | 1941 | *dma = pdata->rx_dma_channel; |
caa1d794 PU |
1942 | |
1943 | /* dmaengine filter data for DT and non-DT boot */ | |
1944 | if (pdev->dev.of_node) | |
1945 | dma_data->filter_data = "rx"; | |
1946 | else | |
9759e7ef | 1947 | dma_data->filter_data = dma; |
caa1d794 | 1948 | } |
453c4990 | 1949 | |
cbc7956c PU |
1950 | if (mcasp->version < MCASP_VERSION_3) { |
1951 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 1952 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
1953 | mcasp->dat_port = true; |
1954 | } else { | |
1955 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1956 | } | |
b67f4487 | 1957 | |
dd55ff83 JS |
1958 | /* Allocate memory for long enough list for all possible |
1959 | * scenarios. Maximum number tdm slots is 32 and there cannot | |
1960 | * be more serializers than given in the configuration. The | |
1961 | * serializer directions could be taken into account, but it | |
1962 | * would make code much more complex and save only couple of | |
1963 | * bytes. | |
1964 | */ | |
1965 | mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = | |
1966 | devm_kzalloc(mcasp->dev, sizeof(unsigned int) * | |
1967 | (32 + mcasp->num_serializer - 2), | |
1968 | GFP_KERNEL); | |
1969 | ||
1970 | mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = | |
1971 | devm_kzalloc(mcasp->dev, sizeof(unsigned int) * | |
1972 | (32 + mcasp->num_serializer - 2), | |
1973 | GFP_KERNEL); | |
1974 | ||
1975 | if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || | |
1976 | !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) | |
1977 | return -ENOMEM; | |
1978 | ||
1979 | ret = davinci_mcasp_set_ch_constraints(mcasp); | |
5935a056 JS |
1980 | if (ret) |
1981 | goto err; | |
1982 | ||
70091a3e | 1983 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1984 | |
1985 | mcasp_reparent_fck(pdev); | |
1986 | ||
b6bb3709 PU |
1987 | ret = devm_snd_soc_register_component(&pdev->dev, |
1988 | &davinci_mcasp_component, | |
1989 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1990 | |
1991 | if (ret != 0) | |
b6bb3709 | 1992 | goto err; |
f08095a4 | 1993 | |
9fbd58cf JS |
1994 | ret = davinci_mcasp_get_dma_type(mcasp); |
1995 | switch (ret) { | |
1996 | case PCM_EDMA: | |
f3f9cfa8 PU |
1997 | #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \ |
1998 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1999 | IS_MODULE(CONFIG_SND_EDMA_SOC)) | |
f3f9cfa8 | 2000 | ret = edma_pcm_platform_register(&pdev->dev); |
9fbd58cf JS |
2001 | #else |
2002 | dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n"); | |
2003 | ret = -EINVAL; | |
2004 | goto err; | |
f3f9cfa8 | 2005 | #endif |
9fbd58cf JS |
2006 | break; |
2007 | case PCM_SDMA: | |
7f28f357 JS |
2008 | #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \ |
2009 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
2010 | IS_MODULE(CONFIG_SND_OMAP_SOC)) | |
d5c6c59a | 2011 | ret = omap_pcm_platform_register(&pdev->dev); |
9fbd58cf JS |
2012 | #else |
2013 | dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n"); | |
2014 | ret = -EINVAL; | |
2015 | goto err; | |
7f28f357 | 2016 | #endif |
9fbd58cf | 2017 | break; |
d5c6c59a | 2018 | default: |
9fbd58cf JS |
2019 | dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); |
2020 | case -EPROBE_DEFER: | |
2021 | goto err; | |
d5c6c59a PU |
2022 | break; |
2023 | } | |
2024 | ||
2025 | if (ret) { | |
2026 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
b6bb3709 | 2027 | goto err; |
f08095a4 HG |
2028 | } |
2029 | ||
b67f4487 C |
2030 | return 0; |
2031 | ||
b6bb3709 | 2032 | err: |
10884347 | 2033 | pm_runtime_disable(&pdev->dev); |
b67f4487 C |
2034 | return ret; |
2035 | } | |
2036 | ||
2037 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
2038 | { | |
10884347 | 2039 | pm_runtime_disable(&pdev->dev); |
b67f4487 | 2040 | |
b67f4487 C |
2041 | return 0; |
2042 | } | |
2043 | ||
2044 | static struct platform_driver davinci_mcasp_driver = { | |
2045 | .probe = davinci_mcasp_probe, | |
2046 | .remove = davinci_mcasp_remove, | |
2047 | .driver = { | |
2048 | .name = "davinci-mcasp", | |
ea421eb1 | 2049 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
2050 | }, |
2051 | }; | |
2052 | ||
f9b8a514 | 2053 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
2054 | |
2055 | MODULE_AUTHOR("Steve Chen"); | |
2056 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
2057 | MODULE_LICENSE("GPL"); |