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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jesse/openvswitch
[deliverable/linux.git] / sound / soc / davinci / davinci-mcasp.c
CommitLineData
b67f4487
C		 1/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
5a0e3ad6 21#include <linux/slab.h>
b67f4487
C		 22#include <linux/delay.h>
23#include <linux/io.h>
10884347 24#include <linux/pm_runtime.h>
3e3b8c34
HG		 25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/of_device.h>
b67f4487
C		 28
29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/initval.h>
33#include <sound/soc.h>
34
35#include "davinci-pcm.h"
36#include "davinci-mcasp.h"
37
38/*
39 * McASP register definitions
40 */
41#define DAVINCI_MCASP_PID_REG 0x00
42#define DAVINCI_MCASP_PWREMUMGT_REG 0x04
43
44#define DAVINCI_MCASP_PFUNC_REG 0x10
45#define DAVINCI_MCASP_PDIR_REG 0x14
46#define DAVINCI_MCASP_PDOUT_REG 0x18
47#define DAVINCI_MCASP_PDSET_REG 0x1c
48
49#define DAVINCI_MCASP_PDCLR_REG 0x20
50
51#define DAVINCI_MCASP_TLGC_REG 0x30
52#define DAVINCI_MCASP_TLMR_REG 0x34
53
54#define DAVINCI_MCASP_GBLCTL_REG 0x44
55#define DAVINCI_MCASP_AMUTE_REG 0x48
56#define DAVINCI_MCASP_LBCTL_REG 0x4c
57
58#define DAVINCI_MCASP_TXDITCTL_REG 0x50
59
60#define DAVINCI_MCASP_GBLCTLR_REG 0x60
61#define DAVINCI_MCASP_RXMASK_REG 0x64
62#define DAVINCI_MCASP_RXFMT_REG 0x68
63#define DAVINCI_MCASP_RXFMCTL_REG 0x6c
64
65#define DAVINCI_MCASP_ACLKRCTL_REG 0x70
66#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
67#define DAVINCI_MCASP_RXTDM_REG 0x78
68#define DAVINCI_MCASP_EVTCTLR_REG 0x7c
69
70#define DAVINCI_MCASP_RXSTAT_REG 0x80
71#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
72#define DAVINCI_MCASP_RXCLKCHK_REG 0x88
73#define DAVINCI_MCASP_REVTCTL_REG 0x8c
74
75#define DAVINCI_MCASP_GBLCTLX_REG 0xa0
76#define DAVINCI_MCASP_TXMASK_REG 0xa4
77#define DAVINCI_MCASP_TXFMT_REG 0xa8
78#define DAVINCI_MCASP_TXFMCTL_REG 0xac
79
80#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
81#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
82#define DAVINCI_MCASP_TXTDM_REG 0xb8
83#define DAVINCI_MCASP_EVTCTLX_REG 0xbc
84
85#define DAVINCI_MCASP_TXSTAT_REG 0xc0
86#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
87#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
88#define DAVINCI_MCASP_XEVTCTL_REG 0xcc
89
90/* Left(even TDM Slot) Channel Status Register File */
91#define DAVINCI_MCASP_DITCSRA_REG 0x100
92/* Right(odd TDM slot) Channel Status Register File */
93#define DAVINCI_MCASP_DITCSRB_REG 0x118
94/* Left(even TDM slot) User Data Register File */
95#define DAVINCI_MCASP_DITUDRA_REG 0x130
96/* Right(odd TDM Slot) User Data Register File */
97#define DAVINCI_MCASP_DITUDRB_REG 0x148
98
99/* Serializer n Control Register */
100#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
101#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
102 (n << 2))
103
104/* Transmit Buffer for Serializer n */
105#define DAVINCI_MCASP_TXBUF_REG 0x200
106/* Receive Buffer for Serializer n */
107#define DAVINCI_MCASP_RXBUF_REG 0x280
108
6a99fb5f
C		 109/* McASP FIFO Registers */
110#define DAVINCI_MCASP_WFIFOCTL (0x1010)
111#define DAVINCI_MCASP_WFIFOSTS (0x1014)
112#define DAVINCI_MCASP_RFIFOCTL (0x1018)
113#define DAVINCI_MCASP_RFIFOSTS (0x101C)
e5ec69da
HG		 114#define MCASP_VER3_WFIFOCTL (0x1000)
115#define MCASP_VER3_WFIFOSTS (0x1004)
116#define MCASP_VER3_RFIFOCTL (0x1008)
117#define MCASP_VER3_RFIFOSTS (0x100C)
b67f4487
C		 118
119/*
120 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
121 * Register Bits
122 */
123#define MCASP_FREE BIT(0)
124#define MCASP_SOFT BIT(1)
125
126/*
127 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
128 */
129#define AXR(n) (1<<n)
130#define PFUNC_AMUTE BIT(25)
131#define ACLKX BIT(26)
132#define AHCLKX BIT(27)
133#define AFSX BIT(28)
134#define ACLKR BIT(29)
135#define AHCLKR BIT(30)
136#define AFSR BIT(31)
137
138/*
139 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
140 */
141#define AXR(n) (1<<n)
142#define PDIR_AMUTE BIT(25)
143#define ACLKX BIT(26)
144#define AHCLKX BIT(27)
145#define AFSX BIT(28)
146#define ACLKR BIT(29)
147#define AHCLKR BIT(30)
148#define AFSR BIT(31)
149
150/*
151 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
152 */
153#define DITEN BIT(0) /* Transmit DIT mode enable/disable */
154#define VA BIT(2)
155#define VB BIT(3)
156
157/*
158 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
159 */
160#define TXROT(val) (val)
161#define TXSEL BIT(3)
162#define TXSSZ(val) (val<<4)
163#define TXPBIT(val) (val<<8)
164#define TXPAD(val) (val<<13)
165#define TXORD BIT(15)
166#define FSXDLY(val) (val<<16)
167
168/*
169 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
170 */
171#define RXROT(val) (val)
172#define RXSEL BIT(3)
173#define RXSSZ(val) (val<<4)
174#define RXPBIT(val) (val<<8)
175#define RXPAD(val) (val<<13)
176#define RXORD BIT(15)
177#define FSRDLY(val) (val<<16)
178
179/*
180 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
181 */
182#define FSXPOL BIT(0)
183#define AFSXE BIT(1)
184#define FSXDUR BIT(4)
185#define FSXMOD(val) (val<<7)
186
187/*
188 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
189 */
190#define FSRPOL BIT(0)
191#define AFSRE BIT(1)
192#define FSRDUR BIT(4)
193#define FSRMOD(val) (val<<7)
194
195/*
196 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
197 */
198#define ACLKXDIV(val) (val)
199#define ACLKXE BIT(5)
200#define TX_ASYNC BIT(6)
201#define ACLKXPOL BIT(7)
202
203/*
204 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
205 */
206#define ACLKRDIV(val) (val)
207#define ACLKRE BIT(5)
208#define RX_ASYNC BIT(6)
209#define ACLKRPOL BIT(7)
210
211/*
212 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
213 * Register Bits
214 */
215#define AHCLKXDIV(val) (val)
216#define AHCLKXPOL BIT(14)
217#define AHCLKXE BIT(15)
218
219/*
220 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
221 * Register Bits
222 */
223#define AHCLKRDIV(val) (val)
224#define AHCLKRPOL BIT(14)
225#define AHCLKRE BIT(15)
226
227/*
228 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
229 */
230#define MODE(val) (val)
231#define DISMOD (val)(val<<2)
232#define TXSTATE BIT(4)
233#define RXSTATE BIT(5)
234
235/*
236 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
237 */
238#define LBEN BIT(0)
239#define LBORD BIT(1)
240#define LBGENMODE(val) (val<<2)
241
242/*
243 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
244 */
245#define TXTDMS(n) (1<<n)
246
247/*
248 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
249 */
250#define RXTDMS(n) (1<<n)
251
252/*
253 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
254 */
255#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
256#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
257#define RXSERCLR BIT(2) /* Receiver Serializer Clear */
258#define RXSMRST BIT(3) /* Receiver State Machine Reset */
259#define RXFSRST BIT(4) /* Frame Sync Generator Reset */
260#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
261#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
262#define TXSERCLR BIT(10) /* Transmit Serializer Clear */
263#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
264#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
265
266/*
267 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
268 */
269#define MUTENA(val) (val)
270#define MUTEINPOL BIT(2)
271#define MUTEINENA BIT(3)
272#define MUTEIN BIT(4)
273#define MUTER BIT(5)
274#define MUTEX BIT(6)
275#define MUTEFSR BIT(7)
276#define MUTEFSX BIT(8)
277#define MUTEBADCLKR BIT(9)
278#define MUTEBADCLKX BIT(10)
279#define MUTERXDMAERR BIT(11)
280#define MUTETXDMAERR BIT(12)
281
282/*
283 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
284 */
285#define RXDATADMADIS BIT(0)
286
287/*
288 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
289 */
290#define TXDATADMADIS BIT(0)
291
6a99fb5f
C		 292/*
293 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
294 */
295#define FIFO_ENABLE BIT(16)
296#define NUMEVT_MASK (0xFF << 8)
297#define NUMDMA_MASK (0xFF)
298
b67f4487
C		 299#define DAVINCI_MCASP_NUM_SERIALIZER 16
300
301static inline void mcasp_set_bits(void __iomem *reg, u32 val)
302{
303 __raw_writel(__raw_readl(reg) | val, reg);
304}
305
306static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
307{
308 __raw_writel((__raw_readl(reg) & ~(val)), reg);
309}
310
311static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
312{
313 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
314}
315
316static inline void mcasp_set_reg(void __iomem *reg, u32 val)
317{
318 __raw_writel(val, reg);
319}
320
321static inline u32 mcasp_get_reg(void __iomem *reg)
322{
323 return (unsigned int)__raw_readl(reg);
324}
325
326static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
327{
328 int i = 0;
329
330 mcasp_set_bits(regs, val);
331
332 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
333 /* loop count is to avoid the lock-up */
334 for (i = 0; i < 1000; i++) {
335 if ((mcasp_get_reg(regs) & val) == val)
336 break;
337 }
338
339 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
340 printk(KERN_ERR "GBLCTL write error\n");
341}
342
b67f4487
C		 343static void mcasp_start_rx(struct davinci_audio_dev *dev)
344{
345 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
346 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
348 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
349
350 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
352 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
353
354 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
355 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
356}
357
358static void mcasp_start_tx(struct davinci_audio_dev *dev)
359{
6a99fb5f
C		 360 u8 offset = 0, i;
361 u32 cnt;
362
b67f4487
C		 363 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
364 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
365 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
366 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
367
368 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
369 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
370 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
6a99fb5f
C		 371 for (i = 0; i < dev->num_serializer; i++) {
372 if (dev->serial_dir[i] == TX_MODE) {
373 offset = i;
374 break;
375 }
376 }
377
378 /* wait for TX ready */
379 cnt = 0;
380 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
381 TXSTATE) && (cnt < 100000))
382 cnt++;
383
b67f4487
C		 384 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
385}
386
387static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
388{
539d3d8c 389 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0d624275 390 if (dev->txnumevt) { /* enable FIFO */
e5ec69da
HG		 391 switch (dev->version) {
392 case MCASP_VERSION_3:
393 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
0d624275 394 FIFO_ENABLE);
e5ec69da 395 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
539d3d8c 396 FIFO_ENABLE);
e5ec69da
HG		 397 break;
398 default:
399 mcasp_clr_bits(dev->base +
400 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
401 mcasp_set_bits(dev->base +
402 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
403 }
0d624275 404 }
b67f4487 405 mcasp_start_tx(dev);
539d3d8c 406 } else {
0d624275 407 if (dev->rxnumevt) { /* enable FIFO */
e5ec69da
HG		 408 switch (dev->version) {
409 case MCASP_VERSION_3:
410 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
0d624275 411 FIFO_ENABLE);
e5ec69da 412 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
539d3d8c 413 FIFO_ENABLE);
e5ec69da
HG		 414 break;
415 default:
416 mcasp_clr_bits(dev->base +
417 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
418 mcasp_set_bits(dev->base +
419 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
420 }
0d624275 421 }
b67f4487 422 mcasp_start_rx(dev);
539d3d8c 423 }
b67f4487
C		 424}
425
426static void mcasp_stop_rx(struct davinci_audio_dev *dev)
427{
428 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
429 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
430}
431
432static void mcasp_stop_tx(struct davinci_audio_dev *dev)
433{
434 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
435 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
436}
437
438static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
439{
539d3d8c 440 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
e5ec69da
HG		 441 if (dev->txnumevt) { /* disable FIFO */
442 switch (dev->version) {
443 case MCASP_VERSION_3:
444 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
539d3d8c 445 FIFO_ENABLE);
e5ec69da
HG		 446 break;
447 default:
448 mcasp_clr_bits(dev->base +
449 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
450 }
451 }
b67f4487 452 mcasp_stop_tx(dev);
539d3d8c 453 } else {
e5ec69da
HG		 454 if (dev->rxnumevt) { /* disable FIFO */
455 switch (dev->version) {
456 case MCASP_VERSION_3:
457 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
539d3d8c 458 FIFO_ENABLE);
e5ec69da
HG		 459 break;
460
461 default:
462 mcasp_clr_bits(dev->base +
463 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
464 }
465 }
b67f4487 466 mcasp_stop_rx(dev);
539d3d8c 467 }
b67f4487
C		 468}
469
470static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
471 unsigned int fmt)
472{
f0fba2ad 473 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 474 void __iomem *base = dev->base;
475
476 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
477 case SND_SOC_DAIFMT_CBS_CFS:
478 /* codec is clock and frame slave */
479 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
480 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
481
482 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
483 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
484
9595c8f0
BG		 485 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
486 ACLKX | AHCLKX | AFSX);
b67f4487 487 break;
517ee6cf
C		 488 case SND_SOC_DAIFMT_CBM_CFS:
489 /* codec is clock master and frame slave */
a90f549e 490 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
517ee6cf
C		 491 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
492
a90f549e 493 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
517ee6cf
C		 494 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
495
db92f437
BG		 496 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
497 ACLKX | ACLKR);
9595c8f0 498 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
db92f437 499 AFSX | AFSR);
517ee6cf 500 break;
b67f4487
C		 501 case SND_SOC_DAIFMT_CBM_CFM:
502 /* codec is clock and frame master */
503 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
504 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
505
506 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
507 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
508
9595c8f0
BG		 509 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
510 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
b67f4487
C		 511 break;
512
513 default:
514 return -EINVAL;
515 }
516
517 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
518 case SND_SOC_DAIFMT_IB_NF:
519 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
520 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
521
522 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
523 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
524 break;
525
526 case SND_SOC_DAIFMT_NB_IF:
527 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
528 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
529
530 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
531 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
532 break;
533
534 case SND_SOC_DAIFMT_IB_IF:
535 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
536 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
537
538 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
539 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
540 break;
541
542 case SND_SOC_DAIFMT_NB_NF:
543 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
544 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
545
546 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
547 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
548 break;
549
550 default:
551 return -EINVAL;
552 }
553
554 return 0;
555}
556
557static int davinci_config_channel_size(struct davinci_audio_dev *dev,
558 int channel_size)
559{
560 u32 fmt = 0;
0c31cf3e 561 u32 mask, rotate;
b67f4487
C		 562
563 switch (channel_size) {
564 case DAVINCI_AUDIO_WORD_8:
565 fmt = 0x03;
0c31cf3e
C		 566 rotate = 6;
567 mask = 0x000000ff;
b67f4487
C		 568 break;
569
570 case DAVINCI_AUDIO_WORD_12:
571 fmt = 0x05;
0c31cf3e
C		 572 rotate = 5;
573 mask = 0x00000fff;
b67f4487
C		 574 break;
575
576 case DAVINCI_AUDIO_WORD_16:
577 fmt = 0x07;
0c31cf3e
C		 578 rotate = 4;
579 mask = 0x0000ffff;
b67f4487
C		 580 break;
581
582 case DAVINCI_AUDIO_WORD_20:
583 fmt = 0x09;
0c31cf3e
C		 584 rotate = 3;
585 mask = 0x000fffff;
b67f4487
C		 586 break;
587
588 case DAVINCI_AUDIO_WORD_24:
589 fmt = 0x0B;
0c31cf3e
C		 590 rotate = 2;
591 mask = 0x00ffffff;
b67f4487
C		 592 break;
593
594 case DAVINCI_AUDIO_WORD_28:
595 fmt = 0x0D;
0c31cf3e
C		 596 rotate = 1;
597 mask = 0x0fffffff;
b67f4487
C		 598 break;
599
600 case DAVINCI_AUDIO_WORD_32:
601 fmt = 0x0F;
0c31cf3e
C		 602 rotate = 0;
603 mask = 0xffffffff;
b67f4487
C		 604 break;
605
606 default:
607 return -EINVAL;
608 }
609
610 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
611 RXSSZ(fmt), RXSSZ(0x0F));
612 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
613 TXSSZ(fmt), TXSSZ(0x0F));
0c31cf3e
C		 614 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
615 TXROT(7));
616 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
617 RXROT(7));
618 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
619 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
620
b67f4487
C		 621 return 0;
622}
623
624static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
625{
626 int i;
6a99fb5f
C		 627 u8 tx_ser = 0;
628 u8 rx_ser = 0;
b67f4487
C		 629
630 /* Default configuration */
631 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
632
633 /* All PINS as McASP */
634 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
635
636 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
637 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
638 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
639 TXDATADMADIS);
640 } else {
641 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
642 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
643 RXDATADMADIS);
644 }
645
646 for (i = 0; i < dev->num_serializer; i++) {
647 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
648 dev->serial_dir[i]);
6a99fb5f 649 if (dev->serial_dir[i] == TX_MODE) {
b67f4487
C		 650 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
651 AXR(i));
6a99fb5f
C		 652 tx_ser++;
653 } else if (dev->serial_dir[i] == RX_MODE) {
b67f4487
C		 654 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
655 AXR(i));
6a99fb5f
C		 656 rx_ser++;
657 }
658 }
659
660 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
661 if (dev->txnumevt * tx_ser > 64)
662 dev->txnumevt = 1;
663
e5ec69da
HG		 664 switch (dev->version) {
665 case MCASP_VERSION_3:
666 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
6a99fb5f 667 NUMDMA_MASK);
e5ec69da 668 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
6a99fb5f 669 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
e5ec69da
HG		 670 break;
671 default:
672 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
673 tx_ser, NUMDMA_MASK);
674 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
675 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
676 }
6a99fb5f
C		 677 }
678
679 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
680 if (dev->rxnumevt * rx_ser > 64)
681 dev->rxnumevt = 1;
e5ec69da
HG		 682 switch (dev->version) {
683 case MCASP_VERSION_3:
684 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
6a99fb5f 685 NUMDMA_MASK);
e5ec69da
HG		 686 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
687 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
688 break;
689 default:
690 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
691 rx_ser, NUMDMA_MASK);
692 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
6a99fb5f 693 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
e5ec69da 694 }
b67f4487
C		 695 }
696}
697
698static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
699{
700 int i, active_slots;
701 u32 mask = 0;
702
703 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
704 for (i = 0; i < active_slots; i++)
705 mask |= (1 << i);
706
6a99fb5f
C		 707 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
708
b67f4487
C		 709 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
710 /* bit stream is MSB first with no delay */
711 /* DSP_B mode */
712 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
713 AHCLKXE);
714 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
715 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
716
049cfaaa 717 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
b67f4487
C		 718 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
719 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
720 else
721 printk(KERN_ERR "playback tdm slot %d not supported\n",
722 dev->tdm_slots);
723
b67f4487
C		 724 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
725 } else {
726 /* bit stream is MSB first with no delay */
727 /* DSP_B mode */
728 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
729 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
730 AHCLKRE);
731 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
732
049cfaaa 733 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
b67f4487
C		 734 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
735 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
736 else
737 printk(KERN_ERR "capture tdm slot %d not supported\n",
738 dev->tdm_slots);
739
b67f4487
C		 740 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
741 }
742}
743
744/* S/PDIF */
745static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
746{
747 /* Set the PDIR for Serialiser as output */
748 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
749
750 /* TXMASK for 24 bits */
751 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
752
753 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
754 and LSB first */
755 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
756 TXROT(6) | TXSSZ(15));
757
758 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
759 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
760 AFSXE | FSXMOD(0x180));
761
762 /* Set the TX tdm : for all the slots */
763 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
764
765 /* Set the TX clock controls : div = 1 and internal */
766 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
767 ACLKXE | TX_ASYNC);
768
769 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
770
771 /* Only 44100 and 48000 are valid, both have the same setting */
772 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
773
774 /* Enable the DIT */
775 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
776}
777
778static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
779 struct snd_pcm_hw_params *params,
780 struct snd_soc_dai *cpu_dai)
781{
f0fba2ad 782 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487 783 struct davinci_pcm_dma_params *dma_params =
92e2a6f6 784 &dev->dma_params[substream->stream];
b67f4487 785 int word_length;
4fa9c1a5 786 u8 fifo_level;
b67f4487
C		 787
788 davinci_hw_common_param(dev, substream->stream);
6a99fb5f 789 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4fa9c1a5 790 fifo_level = dev->txnumevt;
6a99fb5f 791 else
4fa9c1a5 792 fifo_level = dev->rxnumevt;
b67f4487
C		 793
794 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
795 davinci_hw_dit_param(dev);
796 else
797 davinci_hw_param(dev, substream->stream);
798
799 switch (params_format(params)) {
0a9d1385 800 case SNDRV_PCM_FORMAT_U8:
b67f4487
C		 801 case SNDRV_PCM_FORMAT_S8:
802 dma_params->data_type = 1;
803 word_length = DAVINCI_AUDIO_WORD_8;
804 break;
805
0a9d1385 806 case SNDRV_PCM_FORMAT_U16_LE:
b67f4487
C		 807 case SNDRV_PCM_FORMAT_S16_LE:
808 dma_params->data_type = 2;
809 word_length = DAVINCI_AUDIO_WORD_16;
810 break;
811
0a9d1385 812 case SNDRV_PCM_FORMAT_U32_LE:
b67f4487
C		 813 case SNDRV_PCM_FORMAT_S32_LE:
814 dma_params->data_type = 4;
815 word_length = DAVINCI_AUDIO_WORD_32;
816 break;
817
818 default:
819 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
820 return -EINVAL;
821 }
6a99fb5f 822
4fa9c1a5
C		 823 if (dev->version == MCASP_VERSION_2 && !fifo_level)
824 dma_params->acnt = 4;
825 else
6a99fb5f
C		 826 dma_params->acnt = dma_params->data_type;
827
4fa9c1a5 828 dma_params->fifo_level = fifo_level;
b67f4487
C		 829 davinci_config_channel_size(dev, word_length);
830
831 return 0;
832}
833
834static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
835 int cmd, struct snd_soc_dai *cpu_dai)
836{
f0fba2ad 837 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 838 int ret = 0;
839
840 switch (cmd) {
b67f4487 841 case SNDRV_PCM_TRIGGER_RESUME:
e473b847
C		 842 case SNDRV_PCM_TRIGGER_START:
843 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
10884347
HG		 844 ret = pm_runtime_get_sync(dev->dev);
845 if (IS_ERR_VALUE(ret))
846 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
b67f4487
C		 847 davinci_mcasp_start(dev, substream->stream);
848 break;
849
b67f4487 850 case SNDRV_PCM_TRIGGER_SUSPEND:
a47979b5 851 davinci_mcasp_stop(dev, substream->stream);
10884347
HG		 852 ret = pm_runtime_put_sync(dev->dev);
853 if (IS_ERR_VALUE(ret))
854 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
a47979b5
C		 855 break;
856
857 case SNDRV_PCM_TRIGGER_STOP:
b67f4487
C		 858 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
859 davinci_mcasp_stop(dev, substream->stream);
860 break;
861
862 default:
863 ret = -EINVAL;
864 }
865
866 return ret;
867}
868
bedad0ca
CPE		 869static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
870 struct snd_soc_dai *dai)
871{
872 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
873
874 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
875 return 0;
876}
877
85e7652d 878static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
bedad0ca 879 .startup = davinci_mcasp_startup,
b67f4487
C		 880 .trigger = davinci_mcasp_trigger,
881 .hw_params = davinci_mcasp_hw_params,
882 .set_fmt = davinci_mcasp_set_dai_fmt,
883
884};
885
0a9d1385
BG		 886#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
887 SNDRV_PCM_FMTBIT_U8 | \
888 SNDRV_PCM_FMTBIT_S16_LE | \
889 SNDRV_PCM_FMTBIT_U16_LE | \
890 SNDRV_PCM_FMTBIT_S32_LE | \
891 SNDRV_PCM_FMTBIT_U32_LE)
892
f0fba2ad 893static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
b67f4487 894 {
f0fba2ad 895 .name = "davinci-mcasp.0",
b67f4487
C		 896 .playback = {
897 .channels_min = 2,
898 .channels_max = 2,
899 .rates = DAVINCI_MCASP_RATES,
0a9d1385 900 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 901 },
902 .capture = {
903 .channels_min = 2,
904 .channels_max = 2,
905 .rates = DAVINCI_MCASP_RATES,
0a9d1385 906 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 907 },
908 .ops = &davinci_mcasp_dai_ops,
909
910 },
911 {
f0fba2ad 912 "davinci-mcasp.1",
b67f4487
C		 913 .playback = {
914 .channels_min = 1,
915 .channels_max = 384,
916 .rates = DAVINCI_MCASP_RATES,
0a9d1385 917 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 918 },
919 .ops = &davinci_mcasp_dai_ops,
920 },
921
922};
b67f4487 923
3e3b8c34
HG		 924static const struct of_device_id mcasp_dt_ids[] = {
925 {
926 .compatible = "ti,dm646x-mcasp-audio",
927 .data = (void *)MCASP_VERSION_1,
928 },
929 {
930 .compatible = "ti,da830-mcasp-audio",
931 .data = (void *)MCASP_VERSION_2,
932 },
e5ec69da
HG		 933 {
934 .compatible = "ti,omap2-mcasp-audio",
935 .data = (void *)MCASP_VERSION_3,
936 },
3e3b8c34
HG		 937 { /* sentinel */ }
938};
939MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
940
941static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
942 struct platform_device *pdev)
943{
944 struct device_node *np = pdev->dev.of_node;
945 struct snd_platform_data *pdata = NULL;
946 const struct of_device_id *match =
947 of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev);
948
949 const u32 *of_serial_dir32;
950 u8 *of_serial_dir;
951 u32 val;
952 int i, ret = 0;
953
954 if (pdev->dev.platform_data) {
955 pdata = pdev->dev.platform_data;
956 return pdata;
957 } else if (match) {
958 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
959 if (!pdata) {
960 ret = -ENOMEM;
961 goto nodata;
962 }
963 } else {
964 /* control shouldn't reach here. something is wrong */
965 ret = -EINVAL;
966 goto nodata;
967 }
968
969 if (match->data)
970 pdata->version = (u8)((int)match->data);
971
972 ret = of_property_read_u32(np, "op-mode", &val);
973 if (ret >= 0)
974 pdata->op_mode = val;
975
976 ret = of_property_read_u32(np, "tdm-slots", &val);
977 if (ret >= 0)
978 pdata->tdm_slots = val;
979
980 ret = of_property_read_u32(np, "num-serializer", &val);
981 if (ret >= 0)
982 pdata->num_serializer = val;
983
984 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
985 val /= sizeof(u32);
986 if (val != pdata->num_serializer) {
987 dev_err(&pdev->dev,
988 "num-serializer(%d) != serial-dir size(%d)\n",
989 pdata->num_serializer, val);
990 ret = -EINVAL;
991 goto nodata;
992 }
993
994 if (of_serial_dir32) {
995 of_serial_dir = devm_kzalloc(&pdev->dev,
996 (sizeof(*of_serial_dir) * val),
997 GFP_KERNEL);
998 if (!of_serial_dir) {
999 ret = -ENOMEM;
1000 goto nodata;
1001 }
1002
1003 for (i = 0; i < pdata->num_serializer; i++)
1004 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1005
1006 pdata->serial_dir = of_serial_dir;
1007 }
1008
1009 ret = of_property_read_u32(np, "tx-num-evt", &val);
1010 if (ret >= 0)
1011 pdata->txnumevt = val;
1012
1013 ret = of_property_read_u32(np, "rx-num-evt", &val);
1014 if (ret >= 0)
1015 pdata->rxnumevt = val;
1016
1017 ret = of_property_read_u32(np, "sram-size-playback", &val);
1018 if (ret >= 0)
1019 pdata->sram_size_playback = val;
1020
1021 ret = of_property_read_u32(np, "sram-size-capture", &val);
1022 if (ret >= 0)
1023 pdata->sram_size_capture = val;
1024
1025 return pdata;
1026
1027nodata:
1028 if (ret < 0) {
1029 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1030 ret);
1031 pdata = NULL;
1032 }
1033 return pdata;
1034}
1035
b67f4487
C		 1036static int davinci_mcasp_probe(struct platform_device *pdev)
1037{
1038 struct davinci_pcm_dma_params *dma_data;
1039 struct resource *mem, *ioarea, *res;
1040 struct snd_platform_data *pdata;
1041 struct davinci_audio_dev *dev;
96d31e2b 1042 int ret;
b67f4487 1043
3e3b8c34
HG		 1044 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1045 dev_err(&pdev->dev, "No platform data supplied\n");
1046 return -EINVAL;
1047 }
1048
96d31e2b
JL		 1049 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
1050 GFP_KERNEL);
b67f4487
C		 1051 if (!dev)
1052 return -ENOMEM;
1053
3e3b8c34
HG		 1054 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1055 if (!pdata) {
1056 dev_err(&pdev->dev, "no platform data\n");
1057 return -EINVAL;
1058 }
1059
b67f4487
C		 1060 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1061 if (!mem) {
1062 dev_err(&pdev->dev, "no mem resource?\n");
96d31e2b 1063 return -ENODEV;
b67f4487
C		 1064 }
1065
96d31e2b 1066 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
d852f446 1067 resource_size(mem), pdev->name);
b67f4487
C		 1068 if (!ioarea) {
1069 dev_err(&pdev->dev, "Audio region already claimed\n");
96d31e2b 1070 return -EBUSY;
b67f4487
C		 1071 }
1072
10884347 1073 pm_runtime_enable(&pdev->dev);
b67f4487 1074
10884347
HG		 1075 ret = pm_runtime_get_sync(&pdev->dev);
1076 if (IS_ERR_VALUE(ret)) {
1077 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1078 return ret;
1079 }
b67f4487 1080
96d31e2b 1081 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
4f82f028
VB		 1082 if (!dev->base) {
1083 dev_err(&pdev->dev, "ioremap failed\n");
1084 ret = -ENOMEM;
1085 goto err_release_clk;
1086 }
1087
b67f4487
C		 1088 dev->op_mode = pdata->op_mode;
1089 dev->tdm_slots = pdata->tdm_slots;
1090 dev->num_serializer = pdata->num_serializer;
1091 dev->serial_dir = pdata->serial_dir;
1092 dev->codec_fmt = pdata->codec_fmt;
6a99fb5f
C		 1093 dev->version = pdata->version;
1094 dev->txnumevt = pdata->txnumevt;
1095 dev->rxnumevt = pdata->rxnumevt;
10884347 1096 dev->dev = &pdev->dev;
b67f4487 1097
92e2a6f6 1098 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
48519f0a
SN		 1099 dma_data->asp_chan_q = pdata->asp_chan_q;
1100 dma_data->ram_chan_q = pdata->ram_chan_q;
a0c83263 1101 dma_data->sram_size = pdata->sram_size_playback;
92e2a6f6 1102 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
4f82f028 1103 mem->start);
b67f4487
C		 1104
1105 /* first TX, then RX */
1106 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1107 if (!res) {
1108 dev_err(&pdev->dev, "no DMA resource\n");
02ffc5f3 1109 ret = -ENODEV;
96d31e2b 1110 goto err_release_clk;
b67f4487
C		 1111 }
1112
92e2a6f6
TK		 1113 dma_data->channel = res->start;
1114
1115 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
48519f0a
SN		 1116 dma_data->asp_chan_q = pdata->asp_chan_q;
1117 dma_data->ram_chan_q = pdata->ram_chan_q;
a0c83263 1118 dma_data->sram_size = pdata->sram_size_capture;
92e2a6f6 1119 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
4f82f028 1120 mem->start);
b67f4487
C		 1121
1122 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1123 if (!res) {
1124 dev_err(&pdev->dev, "no DMA resource\n");
02ffc5f3 1125 ret = -ENODEV;
96d31e2b 1126 goto err_release_clk;
b67f4487
C		 1127 }
1128
92e2a6f6 1129 dma_data->channel = res->start;
f0fba2ad
LG		 1130 dev_set_drvdata(&pdev->dev, dev);
1131 ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
b67f4487
C		 1132
1133 if (ret != 0)
96d31e2b 1134 goto err_release_clk;
f08095a4
HG		 1135
1136 ret = davinci_soc_platform_register(&pdev->dev);
1137 if (ret) {
1138 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1139 goto err_unregister_dai;
1140 }
1141
b67f4487
C		 1142 return 0;
1143
f08095a4
HG		 1144err_unregister_dai:
1145 snd_soc_unregister_dai(&pdev->dev);
eef6d7b8 1146err_release_clk:
10884347
HG		 1147 pm_runtime_put_sync(&pdev->dev);
1148 pm_runtime_disable(&pdev->dev);
b67f4487
C		 1149 return ret;
1150}
1151
1152static int davinci_mcasp_remove(struct platform_device *pdev)
1153{
b67f4487 1154
f0fba2ad 1155 snd_soc_unregister_dai(&pdev->dev);
f08095a4 1156 davinci_soc_platform_unregister(&pdev->dev);
10884347
HG		 1157
1158 pm_runtime_put_sync(&pdev->dev);
1159 pm_runtime_disable(&pdev->dev);
b67f4487 1160
b67f4487
C		 1161 return 0;
1162}
1163
1164static struct platform_driver davinci_mcasp_driver = {
1165 .probe = davinci_mcasp_probe,
1166 .remove = davinci_mcasp_remove,
1167 .driver = {
1168 .name = "davinci-mcasp",
1169 .owner = THIS_MODULE,
3e3b8c34 1170 .of_match_table = of_match_ptr(mcasp_dt_ids),
b67f4487
C		 1171 },
1172};
1173
f9b8a514 1174module_platform_driver(davinci_mcasp_driver);
b67f4487
C		 1175
1176MODULE_AUTHOR("Steve Chen");
1177MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1178MODULE_LICENSE("GPL");
1179
Linux kernel - Deliverables
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