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Merge tag 'perf-core-for-mingo-3' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / sound / soc / davinci / davinci-mcasp.c
CommitLineData
b67f4487
C		 1/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
5a0e3ad6 21#include <linux/slab.h>
b67f4487
C		 22#include <linux/delay.h>
23#include <linux/io.h>
ae726e93 24#include <linux/clk.h>
10884347 25#include <linux/pm_runtime.h>
3e3b8c34
HG		 26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
9759e7ef 29#include <linux/platform_data/davinci_asp.h>
a75a053f 30#include <linux/math64.h>
b67f4487 31
6479285d 32#include <sound/asoundef.h>
b67f4487
C		 33#include <sound/core.h>
34#include <sound/pcm.h>
35#include <sound/pcm_params.h>
36#include <sound/initval.h>
37#include <sound/soc.h>
453c4990 38#include <sound/dmaengine_pcm.h>
87c19364 39#include <sound/omap-pcm.h>
b67f4487 40
f3f9cfa8 41#include "edma-pcm.h"
b67f4487
C		 42#include "davinci-mcasp.h"
43
0bf0e8ae
PU		 44#define MCASP_MAX_AFIFO_DEPTH 64
45
1cc0c054
PU		 46static u32 context_regs[] = {
47 DAVINCI_MCASP_TXFMCTL_REG,
48 DAVINCI_MCASP_RXFMCTL_REG,
49 DAVINCI_MCASP_TXFMT_REG,
50 DAVINCI_MCASP_RXFMT_REG,
51 DAVINCI_MCASP_ACLKXCTL_REG,
52 DAVINCI_MCASP_ACLKRCTL_REG,
f114ce60
PU		 53 DAVINCI_MCASP_AHCLKXCTL_REG,
54 DAVINCI_MCASP_AHCLKRCTL_REG,
1cc0c054 55 DAVINCI_MCASP_PDIR_REG,
f114ce60
PU		 56 DAVINCI_MCASP_RXMASK_REG,
57 DAVINCI_MCASP_TXMASK_REG,
58 DAVINCI_MCASP_RXTDM_REG,
59 DAVINCI_MCASP_TXTDM_REG,
1cc0c054
PU		 60};
61
790bb94b 62struct davinci_mcasp_context {
1cc0c054 63 u32 config_regs[ARRAY_SIZE(context_regs)];
f114ce60
PU		 64 u32 afifo_regs[2]; /* for read/write fifo control registers */
65 u32 *xrsr_regs; /* for serializer configuration */
6afda7f5 66 bool pm_state;
790bb94b
PU		 67};
68
a75a053f
JS		 69struct davinci_mcasp_ruledata {
70 struct davinci_mcasp *mcasp;
71 int serializers;
72};
73
70091a3e 74struct davinci_mcasp {
453c4990 75 struct snd_dmaengine_dai_dma_data dma_data[2];
21400a72 76 void __iomem *base;
487dce88 77 u32 fifo_base;
21400a72 78 struct device *dev;
a7a3324a 79 struct snd_pcm_substream *substreams[2];
21400a72
PU		 80
81 /* McASP specific data */
82 int tdm_slots;
83 u8 op_mode;
84 u8 num_serializer;
85 u8 *serial_dir;
86 u8 version;
8267525c 87 u8 bclk_div;
21400a72 88 u16 bclk_lrclk_ratio;
4dcb5a0b 89 int streams;
a7a3324a 90 u32 irq_request[2];
9759e7ef 91 int dma_request[2];
21400a72 92
ab8b14b6
JS		 93 int sysclk_freq;
94 bool bclk_master;
95
21400a72
PU		 96 /* McASP FIFO related */
97 u8 txnumevt;
98 u8 rxnumevt;
99
cbc7956c
PU		 100 bool dat_port;
101
11277833
PU		 102 /* Used for comstraint setting on the second stream */
103 u32 channels;
104
21400a72 105#ifdef CONFIG_PM_SLEEP
790bb94b 106 struct davinci_mcasp_context context;
21400a72 107#endif
a75a053f
JS		 108
109 struct davinci_mcasp_ruledata ruledata[2];
21400a72
PU		 110};
111
f68205a7
PU		 112static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
113 u32 val)
b67f4487 114{
f68205a7 115 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 116 __raw_writel(__raw_readl(reg) | val, reg);
117}
118
f68205a7
PU		 119static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
120 u32 val)
b67f4487 121{
f68205a7 122 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 123 __raw_writel((__raw_readl(reg) & ~(val)), reg);
124}
125
f68205a7
PU		 126static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
127 u32 val, u32 mask)
b67f4487 128{
f68205a7 129 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 130 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
131}
132
f68205a7
PU		 133static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
134 u32 val)
b67f4487 135{
f68205a7 136 __raw_writel(val, mcasp->base + offset);
b67f4487
C		 137}
138
f68205a7 139static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
b67f4487 140{
f68205a7 141 return (u32)__raw_readl(mcasp->base + offset);
b67f4487
C		 142}
143
f68205a7 144static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
b67f4487
C		 145{
146 int i = 0;
147
f68205a7 148 mcasp_set_bits(mcasp, ctl_reg, val);
b67f4487
C		 149
150 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
151 /* loop count is to avoid the lock-up */
152 for (i = 0; i < 1000; i++) {
f68205a7 153 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
b67f4487
C		 154 break;
155 }
156
f68205a7 157 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
b67f4487
C		 158 printk(KERN_ERR "GBLCTL write error\n");
159}
160
4dcb5a0b
PU		 161static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
162{
f68205a7
PU		 163 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
164 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
4dcb5a0b
PU		 165
166 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
167}
168
70091a3e 169static void mcasp_start_rx(struct davinci_mcasp *mcasp)
b67f4487 170{
bb372af0
PU		 171 if (mcasp->rxnumevt) { /* enable FIFO */
172 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
173
174 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
175 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
176 }
177
44982735 178 /* Start clocks */
f68205a7
PU		 179 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
180 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
4dcb5a0b
PU		 181 /*
182 * When ASYNC == 0 the transmit and receive sections operate
183 * synchronously from the transmit clock and frame sync. We need to make
184 * sure that the TX signlas are enabled when starting reception.
185 */
186 if (mcasp_is_synchronous(mcasp)) {
f68205a7
PU		 187 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
188 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
4dcb5a0b
PU		 189 }
190
44982735 191 /* Activate serializer(s) */
f68205a7 192 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
44982735 193 /* Release RX state machine */
f68205a7 194 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
44982735 195 /* Release Frame Sync generator */
f68205a7 196 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
4dcb5a0b 197 if (mcasp_is_synchronous(mcasp))
f68205a7 198 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
a7a3324a
MLC		 199
200 /* enable receive IRQs */
201 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
202 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
b67f4487
C		 203}
204
70091a3e 205static void mcasp_start_tx(struct davinci_mcasp *mcasp)
b67f4487 206{
6a99fb5f
C		 207 u32 cnt;
208
bb372af0
PU		 209 if (mcasp->txnumevt) { /* enable FIFO */
210 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
211
212 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
213 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
214 }
215
36bcecd0 216 /* Start clocks */
f68205a7
PU		 217 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
218 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
36bcecd0 219 /* Activate serializer(s) */
f68205a7 220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
b67f4487 221
36bcecd0 222 /* wait for XDATA to be cleared */
6a99fb5f 223 cnt = 0;
36bcecd0
PU		 224 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) &
225 ~XRDATA) && (cnt < 100000))
6a99fb5f
C		 226 cnt++;
227
36bcecd0
PU		 228 /* Release TX state machine */
229 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
230 /* Release Frame Sync generator */
231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
a7a3324a
MLC		 232
233 /* enable transmit IRQs */
234 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
235 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
b67f4487
C		 236}
237
70091a3e 238static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
b67f4487 239{
4dcb5a0b
PU		 240 mcasp->streams++;
241
bb372af0 242 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
70091a3e 243 mcasp_start_tx(mcasp);
bb372af0 244 else
70091a3e 245 mcasp_start_rx(mcasp);
b67f4487
C		 246}
247
70091a3e 248static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
b67f4487 249{
a7a3324a
MLC		 250 /* disable IRQ sources */
251 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
252 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
253
4dcb5a0b
PU		 254 /*
255 * In synchronous mode stop the TX clocks if no other stream is
256 * running
257 */
258 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
f68205a7 259 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
4dcb5a0b 260
f68205a7
PU		 261 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
262 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
0380866a
PU		 263
264 if (mcasp->rxnumevt) { /* disable FIFO */
265 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
266
267 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
268 }
b67f4487
C		 269}
270
70091a3e 271static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
b67f4487 272{
4dcb5a0b
PU		 273 u32 val = 0;
274
a7a3324a
MLC		 275 /* disable IRQ sources */
276 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
277 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
278
4dcb5a0b
PU		 279 /*
280 * In synchronous mode keep TX clocks running if the capture stream is
281 * still running.
282 */
283 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
284 val = TXHCLKRST | TXCLKRST | TXFSRST;
285
f68205a7
PU		 286 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
287 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
0380866a
PU		 288
289 if (mcasp->txnumevt) { /* disable FIFO */
290 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
291
292 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
293 }
b67f4487
C		 294}
295
70091a3e 296static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
b67f4487 297{
4dcb5a0b
PU		 298 mcasp->streams--;
299
0380866a 300 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
70091a3e 301 mcasp_stop_tx(mcasp);
0380866a 302 else
70091a3e 303 mcasp_stop_rx(mcasp);
b67f4487
C		 304}
305
a7a3324a
MLC		 306static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
307{
308 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
309 struct snd_pcm_substream *substream;
310 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
311 u32 handled_mask = 0;
312 u32 stat;
313
314 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
315 if (stat & XUNDRN & irq_mask) {
316 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
317 handled_mask |= XUNDRN;
318
319 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
320 if (substream) {
321 snd_pcm_stream_lock_irq(substream);
322 if (snd_pcm_running(substream))
323 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
324 snd_pcm_stream_unlock_irq(substream);
325 }
326 }
327
328 if (!handled_mask)
329 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
330 stat);
331
332 if (stat & XRERR)
333 handled_mask |= XRERR;
334
335 /* Ack the handled event only */
336 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
337
338 return IRQ_RETVAL(handled_mask);
339}
340
341static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
342{
343 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
344 struct snd_pcm_substream *substream;
345 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
346 u32 handled_mask = 0;
347 u32 stat;
348
349 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
350 if (stat & ROVRN & irq_mask) {
351 dev_warn(mcasp->dev, "Receive buffer overflow\n");
352 handled_mask |= ROVRN;
353
354 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
355 if (substream) {
356 snd_pcm_stream_lock_irq(substream);
357 if (snd_pcm_running(substream))
358 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
359 snd_pcm_stream_unlock_irq(substream);
360 }
361 }
362
363 if (!handled_mask)
364 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
365 stat);
366
367 if (stat & XRERR)
368 handled_mask |= XRERR;
369
370 /* Ack the handled event only */
371 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
372
373 return IRQ_RETVAL(handled_mask);
374}
375
5a1b8a80
PU		 376static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
377{
378 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
379 irqreturn_t ret = IRQ_NONE;
380
381 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
382 ret = davinci_mcasp_tx_irq_handler(irq, data);
383
384 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
385 ret |= davinci_mcasp_rx_irq_handler(irq, data);
386
387 return ret;
388}
389
b67f4487
C		 390static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
391 unsigned int fmt)
392{
70091a3e 393 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1d17a04e 394 int ret = 0;
6dfa9a4e 395 u32 data_delay;
83f12503 396 bool fs_pol_rising;
ffd950f7 397 bool inv_fs = false;
b67f4487 398
1d17a04e 399 pm_runtime_get_sync(mcasp->dev);
5296cf2d 400 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
188edc59
PU		 401 case SND_SOC_DAIFMT_DSP_A:
402 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
403 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
188edc59
PU		 404 /* 1st data bit occur one ACLK cycle after the frame sync */
405 data_delay = 1;
406 break;
5296cf2d
DM		 407 case SND_SOC_DAIFMT_DSP_B:
408 case SND_SOC_DAIFMT_AC97:
f68205a7
PU		 409 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 411 /* No delay after FS */
412 data_delay = 0;
5296cf2d 413 break;
ffd950f7 414 case SND_SOC_DAIFMT_I2S:
5296cf2d 415 /* configure a full-word SYNC pulse (LRCLK) */
f68205a7
PU		 416 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
417 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 418 /* 1st data bit occur one ACLK cycle after the frame sync */
419 data_delay = 1;
ffd950f7
PU		 420 /* FS need to be inverted */
421 inv_fs = true;
5296cf2d 422 break;
423761e0
PU		 423 case SND_SOC_DAIFMT_LEFT_J:
424 /* configure a full-word SYNC pulse (LRCLK) */
425 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
426 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
427 /* No delay after FS */
428 data_delay = 0;
429 break;
ffd950f7
PU		 430 default:
431 ret = -EINVAL;
432 goto out;
5296cf2d
DM		 433 }
434
6dfa9a4e
PU		 435 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
436 FSXDLY(3));
437 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
438 FSRDLY(3));
439
b67f4487
C		 440 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
441 case SND_SOC_DAIFMT_CBS_CFS:
442 /* codec is clock and frame slave */
f68205a7
PU		 443 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
444 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 445
f68205a7
PU		 446 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
447 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 448
f68205a7
PU		 449 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
450 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
ab8b14b6 451 mcasp->bclk_master = 1;
b67f4487 452 break;
226e2f1b
PU		 453 case SND_SOC_DAIFMT_CBS_CFM:
454 /* codec is clock slave and frame master */
455 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
456 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
457
458 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
459 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
460
461 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
463 mcasp->bclk_master = 1;
464 break;
517ee6cf
C		 465 case SND_SOC_DAIFMT_CBM_CFS:
466 /* codec is clock master and frame slave */
f68205a7
PU		 467 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
468 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517ee6cf 469
f68205a7
PU		 470 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
471 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
517ee6cf 472
f68205a7
PU		 473 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
474 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
ab8b14b6 475 mcasp->bclk_master = 0;
517ee6cf 476 break;
b67f4487
C		 477 case SND_SOC_DAIFMT_CBM_CFM:
478 /* codec is clock and frame master */
f68205a7
PU		 479 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
480 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 481
f68205a7
PU		 482 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
483 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 484
f68205a7
PU		 485 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
486 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
ab8b14b6 487 mcasp->bclk_master = 0;
b67f4487 488 break;
b67f4487 489 default:
1d17a04e
PU		 490 ret = -EINVAL;
491 goto out;
b67f4487
C		 492 }
493
494 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
495 case SND_SOC_DAIFMT_IB_NF:
f68205a7 496 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 497 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 498 fs_pol_rising = true;
b67f4487 499 break;
b67f4487 500 case SND_SOC_DAIFMT_NB_IF:
f68205a7 501 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 502 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 503 fs_pol_rising = false;
b67f4487 504 break;
b67f4487 505 case SND_SOC_DAIFMT_IB_IF:
f68205a7 506 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 507 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 508 fs_pol_rising = false;
b67f4487 509 break;
b67f4487 510 case SND_SOC_DAIFMT_NB_NF:
f68205a7 511 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
f68205a7 512 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 513 fs_pol_rising = true;
b67f4487 514 break;
b67f4487 515 default:
1d17a04e 516 ret = -EINVAL;
83f12503
PU		 517 goto out;
518 }
519
ffd950f7
PU		 520 if (inv_fs)
521 fs_pol_rising = !fs_pol_rising;
522
83f12503
PU		 523 if (fs_pol_rising) {
524 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
525 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
526 } else {
527 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
528 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
b67f4487 529 }
1d17a04e 530out:
6afda7f5 531 pm_runtime_put(mcasp->dev);
1d17a04e 532 return ret;
b67f4487
C		 533}
534
8813543e
JS		 535static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
536 int div, bool explicit)
4ed8c9b7 537{
70091a3e 538 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
4ed8c9b7 539
6afda7f5 540 pm_runtime_get_sync(mcasp->dev);
4ed8c9b7
DM		 541 switch (div_id) {
542 case 0: /* MCLK divider */
f68205a7 543 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
4ed8c9b7 544 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
f68205a7 545 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
4ed8c9b7
DM		 546 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
547 break;
548
549 case 1: /* BCLK divider */
f68205a7 550 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
4ed8c9b7 551 ACLKXDIV(div - 1), ACLKXDIV_MASK);
f68205a7 552 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
4ed8c9b7 553 ACLKRDIV(div - 1), ACLKRDIV_MASK);
8813543e
JS		 554 if (explicit)
555 mcasp->bclk_div = div;
4ed8c9b7
DM		 556 break;
557
1b3bc060 558 case 2: /* BCLK/LRCLK ratio */
70091a3e 559 mcasp->bclk_lrclk_ratio = div;
1b3bc060
DM		 560 break;
561
4ed8c9b7
DM		 562 default:
563 return -EINVAL;
564 }
565
6afda7f5 566 pm_runtime_put(mcasp->dev);
4ed8c9b7
DM		 567 return 0;
568}
569
8813543e
JS		 570static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
571 int div)
572{
573 return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
574}
575
5b66aa2d
DM		 576static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
577 unsigned int freq, int dir)
578{
70091a3e 579 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
5b66aa2d 580
6afda7f5 581 pm_runtime_get_sync(mcasp->dev);
5b66aa2d 582 if (dir == SND_SOC_CLOCK_OUT) {
f68205a7
PU		 583 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
584 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
585 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
5b66aa2d 586 } else {
f68205a7
PU		 587 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
588 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
589 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
5b66aa2d
DM		 590 }
591
ab8b14b6
JS		 592 mcasp->sysclk_freq = freq;
593
6afda7f5 594 pm_runtime_put(mcasp->dev);
5b66aa2d
DM		 595 return 0;
596}
597
70091a3e 598static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
ba764b3d 599 int word_length)
b67f4487 600{
ba764b3d 601 u32 fmt;
79671892 602 u32 tx_rotate = (word_length / 4) & 0x7;
ba764b3d 603 u32 mask = (1ULL << word_length) - 1;
fe0a29e1
PU		 604 /*
605 * For captured data we should not rotate, inversion and masking is
606 * enoguh to get the data to the right position:
607 * Format data from bus after reverse (XRBUF)
608 * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
609 * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
610 * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
611 * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
612 */
613 u32 rx_rotate = 0;
b67f4487 614
1b3bc060
DM		 615 /*
616 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
617 * callback, take it into account here. That allows us to for example
618 * send 32 bits per channel to the codec, while only 16 of them carry
619 * audio payload.
d486fea6
MB		 620 * The clock ratio is given for a full period of data (for I2S format
621 * both left and right channels), so it has to be divided by number of
622 * tdm-slots (for I2S - divided by 2).
1b3bc060 623 */
d742b925
PU		 624 if (mcasp->bclk_lrclk_ratio) {
625 u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
626
627 /*
628 * When we have more bclk then it is needed for the data, we
629 * need to use the rotation to move the received samples to have
630 * correct alignment.
631 */
632 rx_rotate = (slot_length - word_length) / 4;
633 word_length = slot_length;
634 }
1b3bc060 635
ba764b3d
DM		 636 /* mapping of the XSSZ bit-field as described in the datasheet */
637 fmt = (word_length >> 1) - 1;
b67f4487 638
70091a3e 639 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
f68205a7
PU		 640 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
641 RXSSZ(0x0F));
642 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
643 TXSSZ(0x0F));
644 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
645 TXROT(7));
646 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
647 RXROT(7));
648 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
f5023af6
YY		 649 }
650
f68205a7 651 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
0c31cf3e 652
b67f4487
C		 653 return 0;
654}
655
662ffae9 656static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
dd093a0f 657 int period_words, int channels)
b67f4487 658{
5f04c603 659 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
b67f4487 660 int i;
6a99fb5f
C		 661 u8 tx_ser = 0;
662 u8 rx_ser = 0;
70091a3e 663 u8 slots = mcasp->tdm_slots;
2952b27e 664 u8 max_active_serializers = (channels + slots - 1) / slots;
dd093a0f 665 int active_serializers, numevt, n;
487dce88 666 u32 reg;
b67f4487 667 /* Default configuration */
40448e5e 668 if (mcasp->version < MCASP_VERSION_3)
f68205a7 669 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
b67f4487
C		 670
671 /* All PINS as McASP */
f68205a7 672 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
b67f4487
C		 673
674 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f68205a7
PU		 675 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
676 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487 677 } else {
f68205a7
PU		 678 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
679 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
b67f4487
C		 680 }
681
70091a3e 682 for (i = 0; i < mcasp->num_serializer; i++) {
f68205a7
PU		 683 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
684 mcasp->serial_dir[i]);
70091a3e 685 if (mcasp->serial_dir[i] == TX_MODE &&
2952b27e 686 tx_ser < max_active_serializers) {
f68205a7 687 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
6a99fb5f 688 tx_ser++;
70091a3e 689 } else if (mcasp->serial_dir[i] == RX_MODE &&
2952b27e 690 rx_ser < max_active_serializers) {
f68205a7 691 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
6a99fb5f 692 rx_ser++;
2952b27e 693 } else {
f68205a7
PU		 694 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
695 SRMOD_INACTIVE, SRMOD_MASK);
6a99fb5f
C		 696 }
697 }
698
0bf0e8ae
PU		 699 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
700 active_serializers = tx_ser;
701 numevt = mcasp->txnumevt;
702 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
703 } else {
704 active_serializers = rx_ser;
705 numevt = mcasp->rxnumevt;
706 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
707 }
ecf327c7 708
0bf0e8ae 709 if (active_serializers < max_active_serializers) {
70091a3e 710 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
0bf0e8ae
PU		 711 "enabled in mcasp (%d)\n", channels,
712 active_serializers * slots);
ecf327c7
DM		 713 return -EINVAL;
714 }
715
0bf0e8ae 716 /* AFIFO is not in use */
5f04c603
PU		 717 if (!numevt) {
718 /* Configure the burst size for platform drivers */
33445643
PU		 719 if (active_serializers > 1) {
720 /*
721 * If more than one serializers are in use we have one
722 * DMA request to provide data for all serializers.
723 * For example if three serializers are enabled the DMA
724 * need to transfer three words per DMA request.
725 */
33445643
PU		 726 dma_data->maxburst = active_serializers;
727 } else {
33445643
PU		 728 dma_data->maxburst = 0;
729 }
0bf0e8ae 730 return 0;
5f04c603 731 }
6a99fb5f 732
dd093a0f
PU		 733 if (period_words % active_serializers) {
734 dev_err(mcasp->dev, "Invalid combination of period words and "
735 "active serializers: %d, %d\n", period_words,
736 active_serializers);
737 return -EINVAL;
738 }
739
740 /*
741 * Calculate the optimal AFIFO depth for platform side:
742 * The number of words for numevt need to be in steps of active
743 * serializers.
744 */
745 n = numevt % active_serializers;
746 if (n)
747 numevt += (active_serializers - n);
748 while (period_words % numevt && numevt > 0)
749 numevt -= active_serializers;
750 if (numevt <= 0)
0bf0e8ae 751 numevt = active_serializers;
487dce88 752
0bf0e8ae
PU		 753 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
754 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
2952b27e 755
5f04c603 756 /* Configure the burst size for platform drivers */
33445643
PU		 757 if (numevt == 1)
758 numevt = 0;
5f04c603
PU		 759 dma_data->maxburst = numevt;
760
2952b27e 761 return 0;
b67f4487
C		 762}
763
18a4f557
MLC		 764static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
765 int channels)
b67f4487
C		 766{
767 int i, active_slots;
18a4f557
MLC		 768 int total_slots;
769 int active_serializers;
b67f4487 770 u32 mask = 0;
cbc7956c 771 u32 busel = 0;
b67f4487 772
18a4f557
MLC		 773 total_slots = mcasp->tdm_slots;
774
775 /*
776 * If more than one serializer is needed, then use them with
777 * their specified tdm_slots count. Otherwise, one serializer
778 * can cope with the transaction using as many slots as channels
779 * in the stream, requires channels symmetry
780 */
781 active_serializers = (channels + total_slots - 1) / total_slots;
782 if (active_serializers == 1)
783 active_slots = channels;
784 else
785 active_slots = total_slots;
786
b67f4487
C		 787 for (i = 0; i < active_slots; i++)
788 mask |= (1 << i);
789
f68205a7 790 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
6a99fb5f 791
cbc7956c
PU		 792 if (!mcasp->dat_port)
793 busel = TXSEL;
794
2c56c4c2
PU		 795 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
796 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
797 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
18a4f557 798 FSXMOD(total_slots), FSXMOD(0x1FF));
2c56c4c2
PU		 799
800 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
801 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
802 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
18a4f557 803 FSRMOD(total_slots), FSRMOD(0x1FF));
2c56c4c2
PU		 804
805 return 0;
b67f4487
C		 806}
807
808/* S/PDIF */
6479285d
DM		 809static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
810 unsigned int rate)
b67f4487 811{
6479285d
DM		 812 u32 cs_value = 0;
813 u8 *cs_bytes = (u8*) &cs_value;
814
b67f4487
C		 815 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
816 and LSB first */
f68205a7 817 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
b67f4487
C		 818
819 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
f68205a7 820 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
b67f4487
C		 821
822 /* Set the TX tdm : for all the slots */
f68205a7 823 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
b67f4487
C		 824
825 /* Set the TX clock controls : div = 1 and internal */
f68205a7 826 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
b67f4487 827
f68205a7 828 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487
C		 829
830 /* Only 44100 and 48000 are valid, both have the same setting */
f68205a7 831 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
b67f4487
C		 832
833 /* Enable the DIT */
f68205a7 834 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
2c56c4c2 835
6479285d
DM		 836 /* Set S/PDIF channel status bits */
837 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
838 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
839
840 switch (rate) {
841 case 22050:
842 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
843 break;
844 case 24000:
845 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
846 break;
847 case 32000:
848 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
849 break;
850 case 44100:
851 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
852 break;
853 case 48000:
854 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
855 break;
856 case 88200:
857 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
858 break;
859 case 96000:
860 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
861 break;
862 case 176400:
863 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
864 break;
865 case 192000:
866 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
867 break;
868 default:
869 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
870 return -EINVAL;
871 }
872
873 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
874 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
875
2c56c4c2 876 return 0;
b67f4487
C		 877}
878
a75a053f
JS		 879static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
880 unsigned int bclk_freq,
881 int *error_ppm)
882{
883 int div = mcasp->sysclk_freq / bclk_freq;
884 int rem = mcasp->sysclk_freq % bclk_freq;
885
886 if (rem != 0) {
887 if (div == 0 ||
888 ((mcasp->sysclk_freq / div) - bclk_freq) >
889 (bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
890 div++;
891 rem = rem - bclk_freq;
892 }
893 }
894 if (error_ppm)
895 *error_ppm =
896 (div*1000000 + (int)div64_long(1000000LL*rem,
897 (int)bclk_freq))
898 /div - 1000000;
899
900 return div;
901}
902
b67f4487
C		 903static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
904 struct snd_pcm_hw_params *params,
905 struct snd_soc_dai *cpu_dai)
906{
70091a3e 907 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487 908 int word_length;
a7e46bd9 909 int channels = params_channels(params);
dd093a0f 910 int period_size = params_period_size(params);
2c56c4c2 911 int ret;
ab8b14b6 912
8267525c
DM		 913 /*
914 * If mcasp is BCLK master, and a BCLK divider was not provided by
915 * the machine driver, we need to calculate the ratio.
916 */
917 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
a75a053f
JS		 918 int channels = params_channels(params);
919 int rate = params_rate(params);
920 int sbits = params_width(params);
921 int ppm, div;
922
923 if (channels > mcasp->tdm_slots)
924 channels = mcasp->tdm_slots;
925
926 div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*channels,
927 &ppm);
928 if (ppm)
929 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
930 ppm);
931
8813543e 932 __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
ab8b14b6
JS		 933 }
934
dd093a0f
PU		 935 ret = mcasp_common_hw_param(mcasp, substream->stream,
936 period_size * channels, channels);
0f7d9a63
PU		 937 if (ret)
938 return ret;
939
70091a3e 940 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
6479285d 941 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
b67f4487 942 else
18a4f557
MLC		 943 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
944 channels);
2c56c4c2
PU		 945
946 if (ret)
947 return ret;
b67f4487
C		 948
949 switch (params_format(params)) {
0a9d1385 950 case SNDRV_PCM_FORMAT_U8:
b67f4487 951 case SNDRV_PCM_FORMAT_S8:
ba764b3d 952 word_length = 8;
b67f4487
C		 953 break;
954
0a9d1385 955 case SNDRV_PCM_FORMAT_U16_LE:
b67f4487 956 case SNDRV_PCM_FORMAT_S16_LE:
ba764b3d 957 word_length = 16;
b67f4487
C		 958 break;
959
21eb24d8
DM		 960 case SNDRV_PCM_FORMAT_U24_3LE:
961 case SNDRV_PCM_FORMAT_S24_3LE:
ba764b3d 962 word_length = 24;
21eb24d8
DM		 963 break;
964
6b7fa011
DM		 965 case SNDRV_PCM_FORMAT_U24_LE:
966 case SNDRV_PCM_FORMAT_S24_LE:
182bef86
PU		 967 word_length = 24;
968 break;
969
0a9d1385 970 case SNDRV_PCM_FORMAT_U32_LE:
b67f4487 971 case SNDRV_PCM_FORMAT_S32_LE:
ba764b3d 972 word_length = 32;
b67f4487
C		 973 break;
974
975 default:
976 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
977 return -EINVAL;
978 }
6a99fb5f 979
70091a3e 980 davinci_config_channel_size(mcasp, word_length);
b67f4487 981
11277833
PU		 982 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
983 mcasp->channels = channels;
984
b67f4487
C		 985 return 0;
986}
987
988static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
989 int cmd, struct snd_soc_dai *cpu_dai)
990{
70091a3e 991 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 992 int ret = 0;
993
994 switch (cmd) {
b67f4487 995 case SNDRV_PCM_TRIGGER_RESUME:
e473b847
C		 996 case SNDRV_PCM_TRIGGER_START:
997 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
70091a3e 998 davinci_mcasp_start(mcasp, substream->stream);
b67f4487 999 break;
b67f4487 1000 case SNDRV_PCM_TRIGGER_SUSPEND:
a47979b5 1001 case SNDRV_PCM_TRIGGER_STOP:
b67f4487 1002 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
70091a3e 1003 davinci_mcasp_stop(mcasp, substream->stream);
b67f4487
C		 1004 break;
1005
1006 default:
1007 ret = -EINVAL;
1008 }
1009
1010 return ret;
1011}
1012
a75a053f
JS		 1013static const unsigned int davinci_mcasp_dai_rates[] = {
1014 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1015 88200, 96000, 176400, 192000,
1016};
1017
1018#define DAVINCI_MAX_RATE_ERROR_PPM 1000
1019
1020static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1021 struct snd_pcm_hw_rule *rule)
1022{
1023 struct davinci_mcasp_ruledata *rd = rule->private;
1024 struct snd_interval *ri =
1025 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1026 int sbits = params_width(params);
1027 int channels = params_channels(params);
1028 unsigned int list[ARRAY_SIZE(davinci_mcasp_dai_rates)];
1029 int i, count = 0;
1030
1031 if (channels > rd->mcasp->tdm_slots)
1032 channels = rd->mcasp->tdm_slots;
1033
1034 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1035 if (ri->min <= davinci_mcasp_dai_rates[i] &&
1036 ri->max >= davinci_mcasp_dai_rates[i]) {
1037 uint bclk_freq = sbits*channels*
1038 davinci_mcasp_dai_rates[i];
1039 int ppm;
1040
1041 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1042 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM)
1043 list[count++] = davinci_mcasp_dai_rates[i];
1044 }
1045 }
1046 dev_dbg(rd->mcasp->dev,
1047 "%d frequencies (%d-%d) for %d sbits and %d channels\n",
1048 count, ri->min, ri->max, sbits, channels);
1049
1050 return snd_interval_list(hw_param_interval(params, rule->var),
1051 count, list, 0);
1052}
1053
1054static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1055 struct snd_pcm_hw_rule *rule)
1056{
1057 struct davinci_mcasp_ruledata *rd = rule->private;
1058 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1059 struct snd_mask nfmt;
1060 int rate = params_rate(params);
1061 int channels = params_channels(params);
1062 int i, count = 0;
1063
1064 snd_mask_none(&nfmt);
1065
1066 if (channels > rd->mcasp->tdm_slots)
1067 channels = rd->mcasp->tdm_slots;
1068
1069 for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
1070 if (snd_mask_test(fmt, i)) {
1071 uint bclk_freq = snd_pcm_format_width(i)*channels*rate;
1072 int ppm;
1073
1074 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1075 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1076 snd_mask_set(&nfmt, i);
1077 count++;
1078 }
1079 }
1080 }
1081 dev_dbg(rd->mcasp->dev,
1082 "%d possible sample format for %d Hz and %d channels\n",
1083 count, rate, channels);
1084
1085 return snd_mask_refine(fmt, &nfmt);
1086}
1087
1088static int davinci_mcasp_hw_rule_channels(struct snd_pcm_hw_params *params,
1089 struct snd_pcm_hw_rule *rule)
1090{
1091 struct davinci_mcasp_ruledata *rd = rule->private;
1092 struct snd_interval *ci =
1093 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
1094 int sbits = params_width(params);
1095 int rate = params_rate(params);
1096 int max_chan_per_wire = rd->mcasp->tdm_slots < ci->max ?
1097 rd->mcasp->tdm_slots : ci->max;
1098 unsigned int list[ci->max - ci->min + 1];
1099 int c1, c, count = 0;
1100
1101 for (c1 = ci->min; c1 <= max_chan_per_wire; c1++) {
1102 uint bclk_freq = c1*sbits*rate;
1103 int ppm;
1104
1105 davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
1106 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1107 /* If we can use all tdm_slots, we can put any
1108 amount of channels to remaining wires as
1109 long as they fit in. */
1110 if (c1 == rd->mcasp->tdm_slots) {
1111 for (c = c1; c <= rd->serializers*c1 &&
1112 c <= ci->max; c++)
1113 list[count++] = c;
1114 } else {
1115 list[count++] = c1;
1116 }
1117 }
1118 }
1119 dev_dbg(rd->mcasp->dev,
1120 "%d possible channel counts (%d-%d) for %d Hz and %d sbits\n",
1121 count, ci->min, ci->max, rate, sbits);
1122
1123 return snd_interval_list(hw_param_interval(params, rule->var),
1124 count, list, 0);
1125}
1126
11277833
PU		 1127static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1128 struct snd_soc_dai *cpu_dai)
1129{
1130 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
4cd9db08
PU		 1131 struct davinci_mcasp_ruledata *ruledata =
1132 &mcasp->ruledata[substream->stream];
11277833
PU		 1133 u32 max_channels = 0;
1134 int i, dir;
1135
a7a3324a
MLC		 1136 mcasp->substreams[substream->stream] = substream;
1137
11277833
PU		 1138 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1139 return 0;
1140
1141 /*
1142 * Limit the maximum allowed channels for the first stream:
1143 * number of serializers for the direction * tdm slots per serializer
1144 */
1145 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1146 dir = TX_MODE;
1147 else
1148 dir = RX_MODE;
1149
1150 for (i = 0; i < mcasp->num_serializer; i++) {
1151 if (mcasp->serial_dir[i] == dir)
1152 max_channels++;
1153 }
4cd9db08 1154 ruledata->serializers = max_channels;
11277833
PU		 1155 max_channels *= mcasp->tdm_slots;
1156 /*
1157 * If the already active stream has less channels than the calculated
1158 * limnit based on the seirializers * tdm_slots, we need to use that as
1159 * a constraint for the second stream.
1160 * Otherwise (first stream or less allowed channels) we use the
1161 * calculated constraint.
1162 */
1163 if (mcasp->channels && mcasp->channels < max_channels)
1164 max_channels = mcasp->channels;
1165
1166 snd_pcm_hw_constraint_minmax(substream->runtime,
1167 SNDRV_PCM_HW_PARAM_CHANNELS,
1168 2, max_channels);
a75a053f
JS		 1169
1170 /*
1171 * If we rely on implicit BCLK divider setting we should
1172 * set constraints based on what we can provide.
1173 */
1174 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1175 int ret;
1176
4cd9db08 1177 ruledata->mcasp = mcasp;
a75a053f
JS		 1178
1179 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1180 SNDRV_PCM_HW_PARAM_RATE,
1181 davinci_mcasp_hw_rule_rate,
4cd9db08 1182 ruledata,
a75a053f
JS		 1183 SNDRV_PCM_HW_PARAM_FORMAT,
1184 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
1185 if (ret)
1186 return ret;
1187 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1188 SNDRV_PCM_HW_PARAM_FORMAT,
1189 davinci_mcasp_hw_rule_format,
4cd9db08 1190 ruledata,
a75a053f
JS		 1191 SNDRV_PCM_HW_PARAM_RATE,
1192 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
1193 if (ret)
1194 return ret;
1195 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1196 SNDRV_PCM_HW_PARAM_CHANNELS,
1197 davinci_mcasp_hw_rule_channels,
4cd9db08 1198 ruledata,
a75a053f
JS		 1199 SNDRV_PCM_HW_PARAM_RATE,
1200 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1201 if (ret)
1202 return ret;
1203 }
1204
11277833
PU		 1205 return 0;
1206}
1207
1208static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1209 struct snd_soc_dai *cpu_dai)
1210{
1211 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1212
a7a3324a
MLC		 1213 mcasp->substreams[substream->stream] = NULL;
1214
11277833
PU		 1215 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1216 return;
1217
1218 if (!cpu_dai->active)
1219 mcasp->channels = 0;
1220}
1221
85e7652d 1222static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
11277833
PU		 1223 .startup = davinci_mcasp_startup,
1224 .shutdown = davinci_mcasp_shutdown,
b67f4487
C		 1225 .trigger = davinci_mcasp_trigger,
1226 .hw_params = davinci_mcasp_hw_params,
1227 .set_fmt = davinci_mcasp_set_dai_fmt,
4ed8c9b7 1228 .set_clkdiv = davinci_mcasp_set_clkdiv,
5b66aa2d 1229 .set_sysclk = davinci_mcasp_set_sysclk,
b67f4487
C		 1230};
1231
d5902f69
PU		 1232static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1233{
1234 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1235
9759e7ef
PU		 1236 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1237 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
d5902f69
PU		 1238
1239 return 0;
1240}
1241
135014ad
PU		 1242#ifdef CONFIG_PM_SLEEP
1243static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
1244{
1245 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
790bb94b 1246 struct davinci_mcasp_context *context = &mcasp->context;
f114ce60 1247 u32 reg;
1cc0c054 1248 int i;
135014ad 1249
66e61885 1250 context->pm_state = pm_runtime_enabled(mcasp->dev);
6afda7f5
PU		 1251 if (!context->pm_state)
1252 pm_runtime_get_sync(mcasp->dev);
1253
1cc0c054
PU		 1254 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1255 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
135014ad 1256
f114ce60
PU		 1257 if (mcasp->txnumevt) {
1258 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1259 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
1260 }
1261 if (mcasp->rxnumevt) {
1262 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1263 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
1264 }
135014ad 1265
f114ce60
PU		 1266 for (i = 0; i < mcasp->num_serializer; i++)
1267 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
1268 DAVINCI_MCASP_XRSRCTL_REG(i));
135014ad 1269
6afda7f5
PU		 1270 pm_runtime_put_sync(mcasp->dev);
1271
135014ad
PU		 1272 return 0;
1273}
1274
1275static int davinci_mcasp_resume(struct snd_soc_dai *dai)
1276{
1277 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
790bb94b 1278 struct davinci_mcasp_context *context = &mcasp->context;
f114ce60 1279 u32 reg;
1cc0c054 1280 int i;
790bb94b 1281
6afda7f5
PU		 1282 pm_runtime_get_sync(mcasp->dev);
1283
1cc0c054
PU		 1284 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
1285 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
135014ad 1286
f114ce60
PU		 1287 if (mcasp->txnumevt) {
1288 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
1289 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
1290 }
1291 if (mcasp->rxnumevt) {
1292 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
1293 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
1294 }
790bb94b 1295
f114ce60
PU		 1296 for (i = 0; i < mcasp->num_serializer; i++)
1297 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
1298 context->xrsr_regs[i]);
135014ad 1299
6afda7f5
PU		 1300 if (!context->pm_state)
1301 pm_runtime_put_sync(mcasp->dev);
1302
135014ad
PU		 1303 return 0;
1304}
1305#else
1306#define davinci_mcasp_suspend NULL
1307#define davinci_mcasp_resume NULL
1308#endif
1309
ed29cd5e
PU		 1310#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1311
0a9d1385
BG		 1312#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1313 SNDRV_PCM_FMTBIT_U8 | \
1314 SNDRV_PCM_FMTBIT_S16_LE | \
1315 SNDRV_PCM_FMTBIT_U16_LE | \
21eb24d8
DM		 1316 SNDRV_PCM_FMTBIT_S24_LE | \
1317 SNDRV_PCM_FMTBIT_U24_LE | \
1318 SNDRV_PCM_FMTBIT_S24_3LE | \
1319 SNDRV_PCM_FMTBIT_U24_3LE | \
0a9d1385
BG		 1320 SNDRV_PCM_FMTBIT_S32_LE | \
1321 SNDRV_PCM_FMTBIT_U32_LE)
1322
f0fba2ad 1323static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
b67f4487 1324 {
f0fba2ad 1325 .name = "davinci-mcasp.0",
d5902f69 1326 .probe = davinci_mcasp_dai_probe,
135014ad
PU		 1327 .suspend = davinci_mcasp_suspend,
1328 .resume = davinci_mcasp_resume,
b67f4487
C		 1329 .playback = {
1330 .channels_min = 2,
2952b27e 1331 .channels_max = 32 * 16,
b67f4487 1332 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1333 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1334 },
1335 .capture = {
1336 .channels_min = 2,
2952b27e 1337 .channels_max = 32 * 16,
b67f4487 1338 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1339 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1340 },
1341 .ops = &davinci_mcasp_dai_ops,
1342
d75249f5 1343 .symmetric_samplebits = 1,
b67f4487
C		 1344 },
1345 {
58e48d97 1346 .name = "davinci-mcasp.1",
d5902f69 1347 .probe = davinci_mcasp_dai_probe,
b67f4487
C		 1348 .playback = {
1349 .channels_min = 1,
1350 .channels_max = 384,
1351 .rates = DAVINCI_MCASP_RATES,
0a9d1385 1352 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 1353 },
1354 .ops = &davinci_mcasp_dai_ops,
1355 },
1356
1357};
b67f4487 1358
eeef0eda
KM		 1359static const struct snd_soc_component_driver davinci_mcasp_component = {
1360 .name = "davinci-mcasp",
1361};
1362
256ba181 1363/* Some HW specific values and defaults. The rest is filled in from DT. */
d1debafc 1364static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
256ba181
JS		 1365 .tx_dma_offset = 0x400,
1366 .rx_dma_offset = 0x400,
256ba181
JS		 1367 .version = MCASP_VERSION_1,
1368};
1369
d1debafc 1370static struct davinci_mcasp_pdata da830_mcasp_pdata = {
256ba181
JS		 1371 .tx_dma_offset = 0x2000,
1372 .rx_dma_offset = 0x2000,
256ba181
JS		 1373 .version = MCASP_VERSION_2,
1374};
1375
d1debafc 1376static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
256ba181
JS		 1377 .tx_dma_offset = 0,
1378 .rx_dma_offset = 0,
256ba181
JS		 1379 .version = MCASP_VERSION_3,
1380};
1381
d1debafc 1382static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
453c4990
PU		 1383 .tx_dma_offset = 0x200,
1384 .rx_dma_offset = 0x284,
453c4990
PU		 1385 .version = MCASP_VERSION_4,
1386};
1387
3e3b8c34
HG		 1388static const struct of_device_id mcasp_dt_ids[] = {
1389 {
1390 .compatible = "ti,dm646x-mcasp-audio",
256ba181 1391 .data = &dm646x_mcasp_pdata,
3e3b8c34
HG		 1392 },
1393 {
1394 .compatible = "ti,da830-mcasp-audio",
256ba181 1395 .data = &da830_mcasp_pdata,
3e3b8c34 1396 },
e5ec69da 1397 {
3af9e031 1398 .compatible = "ti,am33xx-mcasp-audio",
b14899da 1399 .data = &am33xx_mcasp_pdata,
e5ec69da 1400 },
453c4990
PU		 1401 {
1402 .compatible = "ti,dra7-mcasp-audio",
1403 .data = &dra7_mcasp_pdata,
1404 },
3e3b8c34
HG		 1405 { /* sentinel */ }
1406};
1407MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1408
ae726e93
PU		 1409static int mcasp_reparent_fck(struct platform_device *pdev)
1410{
1411 struct device_node *node = pdev->dev.of_node;
1412 struct clk *gfclk, *parent_clk;
1413 const char *parent_name;
1414 int ret;
1415
1416 if (!node)
1417 return 0;
1418
1419 parent_name = of_get_property(node, "fck_parent", NULL);
1420 if (!parent_name)
1421 return 0;
1422
1423 gfclk = clk_get(&pdev->dev, "fck");
1424 if (IS_ERR(gfclk)) {
1425 dev_err(&pdev->dev, "failed to get fck\n");
1426 return PTR_ERR(gfclk);
1427 }
1428
1429 parent_clk = clk_get(NULL, parent_name);
1430 if (IS_ERR(parent_clk)) {
1431 dev_err(&pdev->dev, "failed to get parent clock\n");
1432 ret = PTR_ERR(parent_clk);
1433 goto err1;
1434 }
1435
1436 ret = clk_set_parent(gfclk, parent_clk);
1437 if (ret) {
1438 dev_err(&pdev->dev, "failed to reparent fck\n");
1439 goto err2;
1440 }
1441
1442err2:
1443 clk_put(parent_clk);
1444err1:
1445 clk_put(gfclk);
1446 return ret;
1447}
1448
d1debafc 1449static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
3e3b8c34
HG		 1450 struct platform_device *pdev)
1451{
1452 struct device_node *np = pdev->dev.of_node;
d1debafc 1453 struct davinci_mcasp_pdata *pdata = NULL;
3e3b8c34 1454 const struct of_device_id *match =
ea421eb1 1455 of_match_device(mcasp_dt_ids, &pdev->dev);
4023fe6f 1456 struct of_phandle_args dma_spec;
3e3b8c34
HG		 1457
1458 const u32 *of_serial_dir32;
3e3b8c34
HG		 1459 u32 val;
1460 int i, ret = 0;
1461
1462 if (pdev->dev.platform_data) {
1463 pdata = pdev->dev.platform_data;
1464 return pdata;
1465 } else if (match) {
d1debafc 1466 pdata = (struct davinci_mcasp_pdata*) match->data;
3e3b8c34
HG		 1467 } else {
1468 /* control shouldn't reach here. something is wrong */
1469 ret = -EINVAL;
1470 goto nodata;
1471 }
1472
3e3b8c34
HG		 1473 ret = of_property_read_u32(np, "op-mode", &val);
1474 if (ret >= 0)
1475 pdata->op_mode = val;
1476
1477 ret = of_property_read_u32(np, "tdm-slots", &val);
2952b27e
MB		 1478 if (ret >= 0) {
1479 if (val < 2 || val > 32) {
1480 dev_err(&pdev->dev,
1481 "tdm-slots must be in rage [2-32]\n");
1482 ret = -EINVAL;
1483 goto nodata;
1484 }
1485
3e3b8c34 1486 pdata->tdm_slots = val;
2952b27e 1487 }
3e3b8c34 1488
3e3b8c34
HG		 1489 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1490 val /= sizeof(u32);
3e3b8c34 1491 if (of_serial_dir32) {
1427e660
PU		 1492 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1493 (sizeof(*of_serial_dir) * val),
1494 GFP_KERNEL);
3e3b8c34
HG		 1495 if (!of_serial_dir) {
1496 ret = -ENOMEM;
1497 goto nodata;
1498 }
1499
1427e660 1500 for (i = 0; i < val; i++)
3e3b8c34
HG		 1501 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1502
1427e660 1503 pdata->num_serializer = val;
3e3b8c34
HG		 1504 pdata->serial_dir = of_serial_dir;
1505 }
1506
4023fe6f
JS		 1507 ret = of_property_match_string(np, "dma-names", "tx");
1508 if (ret < 0)
1509 goto nodata;
1510
1511 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1512 &dma_spec);
1513 if (ret < 0)
1514 goto nodata;
1515
1516 pdata->tx_dma_channel = dma_spec.args[0];
1517
caa1d794
PU		 1518 /* RX is not valid in DIT mode */
1519 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1520 ret = of_property_match_string(np, "dma-names", "rx");
1521 if (ret < 0)
1522 goto nodata;
4023fe6f 1523
caa1d794
PU		 1524 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1525 &dma_spec);
1526 if (ret < 0)
1527 goto nodata;
4023fe6f 1528
caa1d794
PU		 1529 pdata->rx_dma_channel = dma_spec.args[0];
1530 }
4023fe6f 1531
3e3b8c34
HG		 1532 ret = of_property_read_u32(np, "tx-num-evt", &val);
1533 if (ret >= 0)
1534 pdata->txnumevt = val;
1535
1536 ret = of_property_read_u32(np, "rx-num-evt", &val);
1537 if (ret >= 0)
1538 pdata->rxnumevt = val;
1539
1540 ret = of_property_read_u32(np, "sram-size-playback", &val);
1541 if (ret >= 0)
1542 pdata->sram_size_playback = val;
1543
1544 ret = of_property_read_u32(np, "sram-size-capture", &val);
1545 if (ret >= 0)
1546 pdata->sram_size_capture = val;
1547
1548 return pdata;
1549
1550nodata:
1551 if (ret < 0) {
1552 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1553 ret);
1554 pdata = NULL;
1555 }
1556 return pdata;
1557}
1558
b67f4487
C		 1559static int davinci_mcasp_probe(struct platform_device *pdev)
1560{
8de131f2 1561 struct snd_dmaengine_dai_dma_data *dma_data;
256ba181 1562 struct resource *mem, *ioarea, *res, *dat;
d1debafc 1563 struct davinci_mcasp_pdata *pdata;
70091a3e 1564 struct davinci_mcasp *mcasp;
a7a3324a 1565 char *irq_name;
9759e7ef 1566 int *dma;
a7a3324a 1567 int irq;
96d31e2b 1568 int ret;
b67f4487 1569
3e3b8c34
HG		 1570 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1571 dev_err(&pdev->dev, "No platform data supplied\n");
1572 return -EINVAL;
1573 }
1574
70091a3e 1575 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
96d31e2b 1576 GFP_KERNEL);
70091a3e 1577 if (!mcasp)
b67f4487
C		 1578 return -ENOMEM;
1579
3e3b8c34
HG		 1580 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1581 if (!pdata) {
1582 dev_err(&pdev->dev, "no platform data\n");
1583 return -EINVAL;
1584 }
1585
256ba181 1586 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
b67f4487 1587 if (!mem) {
70091a3e 1588 dev_warn(mcasp->dev,
256ba181
JS		 1589 "\"mpu\" mem resource not found, using index 0\n");
1590 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1591 if (!mem) {
1592 dev_err(&pdev->dev, "no mem resource?\n");
1593 return -ENODEV;
1594 }
b67f4487
C		 1595 }
1596
96d31e2b 1597 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
d852f446 1598 resource_size(mem), pdev->name);
b67f4487
C		 1599 if (!ioarea) {
1600 dev_err(&pdev->dev, "Audio region already claimed\n");
96d31e2b 1601 return -EBUSY;
b67f4487
C		 1602 }
1603
10884347 1604 pm_runtime_enable(&pdev->dev);
b67f4487 1605
70091a3e
PU		 1606 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1607 if (!mcasp->base) {
4f82f028
VB		 1608 dev_err(&pdev->dev, "ioremap failed\n");
1609 ret = -ENOMEM;
b6bb3709 1610 goto err;
4f82f028
VB		 1611 }
1612
70091a3e 1613 mcasp->op_mode = pdata->op_mode;
1a5923da
PU		 1614 /* sanity check for tdm slots parameter */
1615 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1616 if (pdata->tdm_slots < 2) {
1617 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1618 pdata->tdm_slots);
1619 mcasp->tdm_slots = 2;
1620 } else if (pdata->tdm_slots > 32) {
1621 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
1622 pdata->tdm_slots);
1623 mcasp->tdm_slots = 32;
1624 } else {
1625 mcasp->tdm_slots = pdata->tdm_slots;
1626 }
1627 }
1628
70091a3e 1629 mcasp->num_serializer = pdata->num_serializer;
f114ce60
PU		 1630#ifdef CONFIG_PM_SLEEP
1631 mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev,
1632 sizeof(u32) * mcasp->num_serializer,
1633 GFP_KERNEL);
1634#endif
70091a3e
PU		 1635 mcasp->serial_dir = pdata->serial_dir;
1636 mcasp->version = pdata->version;
1637 mcasp->txnumevt = pdata->txnumevt;
1638 mcasp->rxnumevt = pdata->rxnumevt;
487dce88 1639
70091a3e 1640 mcasp->dev = &pdev->dev;
b67f4487 1641
5a1b8a80
PU		 1642 irq = platform_get_irq_byname(pdev, "common");
1643 if (irq >= 0) {
1644 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common\n",
1645 dev_name(&pdev->dev));
1646 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1647 davinci_mcasp_common_irq_handler,
8f511ffb
PU		 1648 IRQF_ONESHOT | IRQF_SHARED,
1649 irq_name, mcasp);
5a1b8a80
PU		 1650 if (ret) {
1651 dev_err(&pdev->dev, "common IRQ request failed\n");
1652 goto err;
1653 }
1654
1655 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1656 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1657 }
1658
a7a3324a
MLC		 1659 irq = platform_get_irq_byname(pdev, "rx");
1660 if (irq >= 0) {
1661 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx\n",
1662 dev_name(&pdev->dev));
1663 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1664 davinci_mcasp_rx_irq_handler,
1665 IRQF_ONESHOT, irq_name, mcasp);
1666 if (ret) {
1667 dev_err(&pdev->dev, "RX IRQ request failed\n");
1668 goto err;
1669 }
1670
1671 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
1672 }
1673
1674 irq = platform_get_irq_byname(pdev, "tx");
1675 if (irq >= 0) {
1676 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx\n",
1677 dev_name(&pdev->dev));
1678 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1679 davinci_mcasp_tx_irq_handler,
1680 IRQF_ONESHOT, irq_name, mcasp);
1681 if (ret) {
1682 dev_err(&pdev->dev, "TX IRQ request failed\n");
1683 goto err;
1684 }
1685
1686 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
1687 }
1688
256ba181 1689 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
cbc7956c
PU		 1690 if (dat)
1691 mcasp->dat_port = true;
256ba181 1692
8de131f2 1693 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
cbc7956c 1694 if (dat)
9759e7ef 1695 dma_data->addr = dat->start;
cbc7956c 1696 else
9759e7ef 1697 dma_data->addr = mem->start + pdata->tx_dma_offset;
453c4990 1698
9759e7ef 1699 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
b67f4487 1700 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
4023fe6f 1701 if (res)
9759e7ef 1702 *dma = res->start;
4023fe6f 1703 else
9759e7ef 1704 *dma = pdata->tx_dma_channel;
92e2a6f6 1705
8de131f2
PU		 1706 /* dmaengine filter data for DT and non-DT boot */
1707 if (pdev->dev.of_node)
1708 dma_data->filter_data = "tx";
1709 else
9759e7ef 1710 dma_data->filter_data = dma;
8de131f2 1711
caa1d794
PU		 1712 /* RX is not valid in DIT mode */
1713 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
caa1d794 1714 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
caa1d794 1715 if (dat)
9759e7ef 1716 dma_data->addr = dat->start;
caa1d794 1717 else
9759e7ef 1718 dma_data->addr = mem->start + pdata->rx_dma_offset;
caa1d794 1719
9759e7ef 1720 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
caa1d794
PU		 1721 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1722 if (res)
9759e7ef 1723 *dma = res->start;
caa1d794 1724 else
9759e7ef 1725 *dma = pdata->rx_dma_channel;
caa1d794
PU		 1726
1727 /* dmaengine filter data for DT and non-DT boot */
1728 if (pdev->dev.of_node)
1729 dma_data->filter_data = "rx";
1730 else
9759e7ef 1731 dma_data->filter_data = dma;
caa1d794 1732 }
453c4990 1733
cbc7956c
PU		 1734 if (mcasp->version < MCASP_VERSION_3) {
1735 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
64ebdec3 1736 /* dma_params->dma_addr is pointing to the data port address */
cbc7956c
PU		 1737 mcasp->dat_port = true;
1738 } else {
1739 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1740 }
b67f4487 1741
70091a3e 1742 dev_set_drvdata(&pdev->dev, mcasp);
ae726e93
PU		 1743
1744 mcasp_reparent_fck(pdev);
1745
b6bb3709
PU		 1746 ret = devm_snd_soc_register_component(&pdev->dev,
1747 &davinci_mcasp_component,
1748 &davinci_mcasp_dai[pdata->op_mode], 1);
b67f4487
C		 1749
1750 if (ret != 0)
b6bb3709 1751 goto err;
f08095a4 1752
d5c6c59a 1753 switch (mcasp->version) {
f3f9cfa8
PU		 1754#if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
1755 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1756 IS_MODULE(CONFIG_SND_EDMA_SOC))
9759e7ef
PU		 1757 case MCASP_VERSION_1:
1758 case MCASP_VERSION_2:
f3f9cfa8
PU		 1759 case MCASP_VERSION_3:
1760 ret = edma_pcm_platform_register(&pdev->dev);
1761 break;
1762#endif
7f28f357
JS		 1763#if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
1764 (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
1765 IS_MODULE(CONFIG_SND_OMAP_SOC))
d5c6c59a
PU		 1766 case MCASP_VERSION_4:
1767 ret = omap_pcm_platform_register(&pdev->dev);
1768 break;
7f28f357 1769#endif
d5c6c59a
PU		 1770 default:
1771 dev_err(&pdev->dev, "Invalid McASP version: %d\n",
1772 mcasp->version);
1773 ret = -EINVAL;
1774 break;
1775 }
1776
1777 if (ret) {
1778 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
b6bb3709 1779 goto err;
f08095a4
HG		 1780 }
1781
b67f4487
C		 1782 return 0;
1783
b6bb3709 1784err:
10884347 1785 pm_runtime_disable(&pdev->dev);
b67f4487
C		 1786 return ret;
1787}
1788
1789static int davinci_mcasp_remove(struct platform_device *pdev)
1790{
10884347 1791 pm_runtime_disable(&pdev->dev);
b67f4487 1792
b67f4487
C		 1793 return 0;
1794}
1795
1796static struct platform_driver davinci_mcasp_driver = {
1797 .probe = davinci_mcasp_probe,
1798 .remove = davinci_mcasp_remove,
1799 .driver = {
1800 .name = "davinci-mcasp",
ea421eb1 1801 .of_match_table = mcasp_dt_ids,
b67f4487
C		 1802 },
1803};
1804
f9b8a514 1805module_platform_driver(davinci_mcasp_driver);
b67f4487
C		 1806
1807MODULE_AUTHOR("Steve Chen");
1808MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1809MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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