Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
9759e7ef | 29 | #include <linux/platform_data/davinci_asp.h> |
b67f4487 | 30 | |
6479285d | 31 | #include <sound/asoundef.h> |
b67f4487 C |
32 | #include <sound/core.h> |
33 | #include <sound/pcm.h> | |
34 | #include <sound/pcm_params.h> | |
35 | #include <sound/initval.h> | |
36 | #include <sound/soc.h> | |
453c4990 | 37 | #include <sound/dmaengine_pcm.h> |
87c19364 | 38 | #include <sound/omap-pcm.h> |
b67f4487 | 39 | |
f3f9cfa8 | 40 | #include "edma-pcm.h" |
b67f4487 C |
41 | #include "davinci-mcasp.h" |
42 | ||
0bf0e8ae PU |
43 | #define MCASP_MAX_AFIFO_DEPTH 64 |
44 | ||
1cc0c054 PU |
45 | static u32 context_regs[] = { |
46 | DAVINCI_MCASP_TXFMCTL_REG, | |
47 | DAVINCI_MCASP_RXFMCTL_REG, | |
48 | DAVINCI_MCASP_TXFMT_REG, | |
49 | DAVINCI_MCASP_RXFMT_REG, | |
50 | DAVINCI_MCASP_ACLKXCTL_REG, | |
51 | DAVINCI_MCASP_ACLKRCTL_REG, | |
f114ce60 PU |
52 | DAVINCI_MCASP_AHCLKXCTL_REG, |
53 | DAVINCI_MCASP_AHCLKRCTL_REG, | |
1cc0c054 | 54 | DAVINCI_MCASP_PDIR_REG, |
f114ce60 PU |
55 | DAVINCI_MCASP_RXMASK_REG, |
56 | DAVINCI_MCASP_TXMASK_REG, | |
57 | DAVINCI_MCASP_RXTDM_REG, | |
58 | DAVINCI_MCASP_TXTDM_REG, | |
1cc0c054 PU |
59 | }; |
60 | ||
790bb94b | 61 | struct davinci_mcasp_context { |
1cc0c054 | 62 | u32 config_regs[ARRAY_SIZE(context_regs)]; |
f114ce60 PU |
63 | u32 afifo_regs[2]; /* for read/write fifo control registers */ |
64 | u32 *xrsr_regs; /* for serializer configuration */ | |
790bb94b PU |
65 | }; |
66 | ||
70091a3e | 67 | struct davinci_mcasp { |
453c4990 | 68 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 69 | void __iomem *base; |
487dce88 | 70 | u32 fifo_base; |
21400a72 | 71 | struct device *dev; |
a7a3324a | 72 | struct snd_pcm_substream *substreams[2]; |
21400a72 PU |
73 | |
74 | /* McASP specific data */ | |
75 | int tdm_slots; | |
76 | u8 op_mode; | |
77 | u8 num_serializer; | |
78 | u8 *serial_dir; | |
79 | u8 version; | |
8267525c | 80 | u8 bclk_div; |
21400a72 | 81 | u16 bclk_lrclk_ratio; |
4dcb5a0b | 82 | int streams; |
a7a3324a | 83 | u32 irq_request[2]; |
9759e7ef | 84 | int dma_request[2]; |
21400a72 | 85 | |
ab8b14b6 JS |
86 | int sysclk_freq; |
87 | bool bclk_master; | |
88 | ||
21400a72 PU |
89 | /* McASP FIFO related */ |
90 | u8 txnumevt; | |
91 | u8 rxnumevt; | |
92 | ||
cbc7956c PU |
93 | bool dat_port; |
94 | ||
11277833 PU |
95 | /* Used for comstraint setting on the second stream */ |
96 | u32 channels; | |
97 | ||
21400a72 | 98 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 99 | struct davinci_mcasp_context context; |
21400a72 PU |
100 | #endif |
101 | }; | |
102 | ||
f68205a7 PU |
103 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
104 | u32 val) | |
b67f4487 | 105 | { |
f68205a7 | 106 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
107 | __raw_writel(__raw_readl(reg) | val, reg); |
108 | } | |
109 | ||
f68205a7 PU |
110 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
111 | u32 val) | |
b67f4487 | 112 | { |
f68205a7 | 113 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
114 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
115 | } | |
116 | ||
f68205a7 PU |
117 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
118 | u32 val, u32 mask) | |
b67f4487 | 119 | { |
f68205a7 | 120 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
121 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
122 | } | |
123 | ||
f68205a7 PU |
124 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
125 | u32 val) | |
b67f4487 | 126 | { |
f68205a7 | 127 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
128 | } |
129 | ||
f68205a7 | 130 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 131 | { |
f68205a7 | 132 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
133 | } |
134 | ||
f68205a7 | 135 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
136 | { |
137 | int i = 0; | |
138 | ||
f68205a7 | 139 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
140 | |
141 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
142 | /* loop count is to avoid the lock-up */ | |
143 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 144 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
145 | break; |
146 | } | |
147 | ||
f68205a7 | 148 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
149 | printk(KERN_ERR "GBLCTL write error\n"); |
150 | } | |
151 | ||
4dcb5a0b PU |
152 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
153 | { | |
f68205a7 PU |
154 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
155 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
156 | |
157 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
158 | } | |
159 | ||
70091a3e | 160 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 161 | { |
bb372af0 PU |
162 | if (mcasp->rxnumevt) { /* enable FIFO */ |
163 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
164 | ||
165 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
166 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
167 | } | |
168 | ||
44982735 | 169 | /* Start clocks */ |
f68205a7 PU |
170 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
171 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
172 | /* |
173 | * When ASYNC == 0 the transmit and receive sections operate | |
174 | * synchronously from the transmit clock and frame sync. We need to make | |
175 | * sure that the TX signlas are enabled when starting reception. | |
176 | */ | |
177 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
178 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
179 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
180 | } |
181 | ||
44982735 | 182 | /* Activate serializer(s) */ |
f68205a7 | 183 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
44982735 | 184 | /* Release RX state machine */ |
f68205a7 | 185 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
44982735 | 186 | /* Release Frame Sync generator */ |
f68205a7 | 187 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
4dcb5a0b | 188 | if (mcasp_is_synchronous(mcasp)) |
f68205a7 | 189 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
a7a3324a MLC |
190 | |
191 | /* enable receive IRQs */ | |
192 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
193 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
b67f4487 C |
194 | } |
195 | ||
70091a3e | 196 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 197 | { |
6a99fb5f C |
198 | u32 cnt; |
199 | ||
bb372af0 PU |
200 | if (mcasp->txnumevt) { /* enable FIFO */ |
201 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
202 | ||
203 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
204 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
205 | } | |
206 | ||
36bcecd0 | 207 | /* Start clocks */ |
f68205a7 PU |
208 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
209 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
36bcecd0 | 210 | /* Activate serializer(s) */ |
f68205a7 | 211 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); |
b67f4487 | 212 | |
36bcecd0 | 213 | /* wait for XDATA to be cleared */ |
6a99fb5f | 214 | cnt = 0; |
36bcecd0 PU |
215 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & |
216 | ~XRDATA) && (cnt < 100000)) | |
6a99fb5f C |
217 | cnt++; |
218 | ||
36bcecd0 PU |
219 | /* Release TX state machine */ |
220 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); | |
221 | /* Release Frame Sync generator */ | |
222 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
a7a3324a MLC |
223 | |
224 | /* enable transmit IRQs */ | |
225 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
226 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
b67f4487 C |
227 | } |
228 | ||
70091a3e | 229 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 230 | { |
4dcb5a0b PU |
231 | mcasp->streams++; |
232 | ||
bb372af0 | 233 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 234 | mcasp_start_tx(mcasp); |
bb372af0 | 235 | else |
70091a3e | 236 | mcasp_start_rx(mcasp); |
b67f4487 C |
237 | } |
238 | ||
70091a3e | 239 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 240 | { |
a7a3324a MLC |
241 | /* disable IRQ sources */ |
242 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
243 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
244 | ||
4dcb5a0b PU |
245 | /* |
246 | * In synchronous mode stop the TX clocks if no other stream is | |
247 | * running | |
248 | */ | |
249 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 250 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 251 | |
f68205a7 PU |
252 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
253 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
254 | |
255 | if (mcasp->rxnumevt) { /* disable FIFO */ | |
256 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
257 | ||
258 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
259 | } | |
b67f4487 C |
260 | } |
261 | ||
70091a3e | 262 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 263 | { |
4dcb5a0b PU |
264 | u32 val = 0; |
265 | ||
a7a3324a MLC |
266 | /* disable IRQ sources */ |
267 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
268 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
269 | ||
4dcb5a0b PU |
270 | /* |
271 | * In synchronous mode keep TX clocks running if the capture stream is | |
272 | * still running. | |
273 | */ | |
274 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
275 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
276 | ||
f68205a7 PU |
277 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
278 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
279 | |
280 | if (mcasp->txnumevt) { /* disable FIFO */ | |
281 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
282 | ||
283 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
284 | } | |
b67f4487 C |
285 | } |
286 | ||
70091a3e | 287 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 288 | { |
4dcb5a0b PU |
289 | mcasp->streams--; |
290 | ||
0380866a | 291 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 292 | mcasp_stop_tx(mcasp); |
0380866a | 293 | else |
70091a3e | 294 | mcasp_stop_rx(mcasp); |
b67f4487 C |
295 | } |
296 | ||
a7a3324a MLC |
297 | static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) |
298 | { | |
299 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
300 | struct snd_pcm_substream *substream; | |
301 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; | |
302 | u32 handled_mask = 0; | |
303 | u32 stat; | |
304 | ||
305 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); | |
306 | if (stat & XUNDRN & irq_mask) { | |
307 | dev_warn(mcasp->dev, "Transmit buffer underflow\n"); | |
308 | handled_mask |= XUNDRN; | |
309 | ||
310 | substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; | |
311 | if (substream) { | |
312 | snd_pcm_stream_lock_irq(substream); | |
313 | if (snd_pcm_running(substream)) | |
314 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); | |
315 | snd_pcm_stream_unlock_irq(substream); | |
316 | } | |
317 | } | |
318 | ||
319 | if (!handled_mask) | |
320 | dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", | |
321 | stat); | |
322 | ||
323 | if (stat & XRERR) | |
324 | handled_mask |= XRERR; | |
325 | ||
326 | /* Ack the handled event only */ | |
327 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); | |
328 | ||
329 | return IRQ_RETVAL(handled_mask); | |
330 | } | |
331 | ||
332 | static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) | |
333 | { | |
334 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
335 | struct snd_pcm_substream *substream; | |
336 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; | |
337 | u32 handled_mask = 0; | |
338 | u32 stat; | |
339 | ||
340 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); | |
341 | if (stat & ROVRN & irq_mask) { | |
342 | dev_warn(mcasp->dev, "Receive buffer overflow\n"); | |
343 | handled_mask |= ROVRN; | |
344 | ||
345 | substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; | |
346 | if (substream) { | |
347 | snd_pcm_stream_lock_irq(substream); | |
348 | if (snd_pcm_running(substream)) | |
349 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); | |
350 | snd_pcm_stream_unlock_irq(substream); | |
351 | } | |
352 | } | |
353 | ||
354 | if (!handled_mask) | |
355 | dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", | |
356 | stat); | |
357 | ||
358 | if (stat & XRERR) | |
359 | handled_mask |= XRERR; | |
360 | ||
361 | /* Ack the handled event only */ | |
362 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); | |
363 | ||
364 | return IRQ_RETVAL(handled_mask); | |
365 | } | |
366 | ||
5a1b8a80 PU |
367 | static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) |
368 | { | |
369 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
370 | irqreturn_t ret = IRQ_NONE; | |
371 | ||
372 | if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) | |
373 | ret = davinci_mcasp_tx_irq_handler(irq, data); | |
374 | ||
375 | if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) | |
376 | ret |= davinci_mcasp_rx_irq_handler(irq, data); | |
377 | ||
378 | return ret; | |
379 | } | |
380 | ||
b67f4487 C |
381 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
382 | unsigned int fmt) | |
383 | { | |
70091a3e | 384 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 385 | int ret = 0; |
6dfa9a4e | 386 | u32 data_delay; |
83f12503 | 387 | bool fs_pol_rising; |
ffd950f7 | 388 | bool inv_fs = false; |
b67f4487 | 389 | |
1d17a04e | 390 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d | 391 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
188edc59 PU |
392 | case SND_SOC_DAIFMT_DSP_A: |
393 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
394 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
188edc59 PU |
395 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
396 | data_delay = 1; | |
397 | break; | |
5296cf2d DM |
398 | case SND_SOC_DAIFMT_DSP_B: |
399 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
400 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
401 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
402 | /* No delay after FS */ |
403 | data_delay = 0; | |
5296cf2d | 404 | break; |
ffd950f7 | 405 | case SND_SOC_DAIFMT_I2S: |
5296cf2d | 406 | /* configure a full-word SYNC pulse (LRCLK) */ |
f68205a7 PU |
407 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
408 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
409 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
410 | data_delay = 1; | |
ffd950f7 PU |
411 | /* FS need to be inverted */ |
412 | inv_fs = true; | |
5296cf2d | 413 | break; |
423761e0 PU |
414 | case SND_SOC_DAIFMT_LEFT_J: |
415 | /* configure a full-word SYNC pulse (LRCLK) */ | |
416 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
417 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
418 | /* No delay after FS */ | |
419 | data_delay = 0; | |
420 | break; | |
ffd950f7 PU |
421 | default: |
422 | ret = -EINVAL; | |
423 | goto out; | |
5296cf2d DM |
424 | } |
425 | ||
6dfa9a4e PU |
426 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), |
427 | FSXDLY(3)); | |
428 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), | |
429 | FSRDLY(3)); | |
430 | ||
b67f4487 C |
431 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
432 | case SND_SOC_DAIFMT_CBS_CFS: | |
433 | /* codec is clock and frame slave */ | |
f68205a7 PU |
434 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
435 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 436 | |
f68205a7 PU |
437 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
438 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 439 | |
f68205a7 PU |
440 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
441 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 442 | mcasp->bclk_master = 1; |
b67f4487 | 443 | break; |
226e2f1b PU |
444 | case SND_SOC_DAIFMT_CBS_CFM: |
445 | /* codec is clock slave and frame master */ | |
446 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); | |
447 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
448 | ||
449 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); | |
450 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
451 | ||
452 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); | |
453 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
454 | mcasp->bclk_master = 1; | |
455 | break; | |
517ee6cf C |
456 | case SND_SOC_DAIFMT_CBM_CFS: |
457 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
458 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
459 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 460 | |
f68205a7 PU |
461 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
462 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 463 | |
f68205a7 PU |
464 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
465 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 466 | mcasp->bclk_master = 0; |
517ee6cf | 467 | break; |
b67f4487 C |
468 | case SND_SOC_DAIFMT_CBM_CFM: |
469 | /* codec is clock and frame master */ | |
f68205a7 PU |
470 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
471 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 472 | |
f68205a7 PU |
473 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
474 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 475 | |
f68205a7 PU |
476 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
477 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
ab8b14b6 | 478 | mcasp->bclk_master = 0; |
b67f4487 | 479 | break; |
b67f4487 | 480 | default: |
1d17a04e PU |
481 | ret = -EINVAL; |
482 | goto out; | |
b67f4487 C |
483 | } |
484 | ||
485 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
486 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 | 487 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 488 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 489 | fs_pol_rising = true; |
b67f4487 | 490 | break; |
b67f4487 | 491 | case SND_SOC_DAIFMT_NB_IF: |
f68205a7 | 492 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 493 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 494 | fs_pol_rising = false; |
b67f4487 | 495 | break; |
b67f4487 | 496 | case SND_SOC_DAIFMT_IB_IF: |
f68205a7 | 497 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 498 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 499 | fs_pol_rising = false; |
b67f4487 | 500 | break; |
b67f4487 | 501 | case SND_SOC_DAIFMT_NB_NF: |
f68205a7 | 502 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
f68205a7 | 503 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 504 | fs_pol_rising = true; |
b67f4487 | 505 | break; |
b67f4487 | 506 | default: |
1d17a04e | 507 | ret = -EINVAL; |
83f12503 PU |
508 | goto out; |
509 | } | |
510 | ||
ffd950f7 PU |
511 | if (inv_fs) |
512 | fs_pol_rising = !fs_pol_rising; | |
513 | ||
83f12503 PU |
514 | if (fs_pol_rising) { |
515 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
516 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
517 | } else { | |
518 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
519 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 | 520 | } |
1d17a04e PU |
521 | out: |
522 | pm_runtime_put_sync(mcasp->dev); | |
523 | return ret; | |
b67f4487 C |
524 | } |
525 | ||
8813543e JS |
526 | static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
527 | int div, bool explicit) | |
4ed8c9b7 | 528 | { |
70091a3e | 529 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
4ed8c9b7 DM |
530 | |
531 | switch (div_id) { | |
532 | case 0: /* MCLK divider */ | |
f68205a7 | 533 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 534 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 535 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
536 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
537 | break; | |
538 | ||
539 | case 1: /* BCLK divider */ | |
f68205a7 | 540 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 541 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 542 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 | 543 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
8813543e JS |
544 | if (explicit) |
545 | mcasp->bclk_div = div; | |
4ed8c9b7 DM |
546 | break; |
547 | ||
1b3bc060 | 548 | case 2: /* BCLK/LRCLK ratio */ |
70091a3e | 549 | mcasp->bclk_lrclk_ratio = div; |
1b3bc060 DM |
550 | break; |
551 | ||
4ed8c9b7 DM |
552 | default: |
553 | return -EINVAL; | |
554 | } | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
8813543e JS |
559 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
560 | int div) | |
561 | { | |
562 | return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1); | |
563 | } | |
564 | ||
5b66aa2d DM |
565 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
566 | unsigned int freq, int dir) | |
567 | { | |
70091a3e | 568 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d DM |
569 | |
570 | if (dir == SND_SOC_CLOCK_OUT) { | |
f68205a7 PU |
571 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
572 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
573 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 574 | } else { |
f68205a7 PU |
575 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
576 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
577 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
578 | } |
579 | ||
ab8b14b6 JS |
580 | mcasp->sysclk_freq = freq; |
581 | ||
5b66aa2d DM |
582 | return 0; |
583 | } | |
584 | ||
70091a3e | 585 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
ba764b3d | 586 | int word_length) |
b67f4487 | 587 | { |
ba764b3d | 588 | u32 fmt; |
79671892 | 589 | u32 tx_rotate = (word_length / 4) & 0x7; |
ba764b3d | 590 | u32 mask = (1ULL << word_length) - 1; |
fe0a29e1 PU |
591 | /* |
592 | * For captured data we should not rotate, inversion and masking is | |
593 | * enoguh to get the data to the right position: | |
594 | * Format data from bus after reverse (XRBUF) | |
595 | * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| | |
596 | * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
597 | * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
598 | * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| | |
599 | */ | |
600 | u32 rx_rotate = 0; | |
b67f4487 | 601 | |
1b3bc060 DM |
602 | /* |
603 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() | |
604 | * callback, take it into account here. That allows us to for example | |
605 | * send 32 bits per channel to the codec, while only 16 of them carry | |
606 | * audio payload. | |
d486fea6 MB |
607 | * The clock ratio is given for a full period of data (for I2S format |
608 | * both left and right channels), so it has to be divided by number of | |
609 | * tdm-slots (for I2S - divided by 2). | |
1b3bc060 | 610 | */ |
d742b925 PU |
611 | if (mcasp->bclk_lrclk_ratio) { |
612 | u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; | |
613 | ||
614 | /* | |
615 | * When we have more bclk then it is needed for the data, we | |
616 | * need to use the rotation to move the received samples to have | |
617 | * correct alignment. | |
618 | */ | |
619 | rx_rotate = (slot_length - word_length) / 4; | |
620 | word_length = slot_length; | |
621 | } | |
1b3bc060 | 622 | |
ba764b3d DM |
623 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
624 | fmt = (word_length >> 1) - 1; | |
b67f4487 | 625 | |
70091a3e | 626 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
627 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
628 | RXSSZ(0x0F)); | |
629 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
630 | TXSSZ(0x0F)); | |
631 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
632 | TXROT(7)); | |
633 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
634 | RXROT(7)); | |
635 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
636 | } |
637 | ||
f68205a7 | 638 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 639 | |
b67f4487 C |
640 | return 0; |
641 | } | |
642 | ||
662ffae9 | 643 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
dd093a0f | 644 | int period_words, int channels) |
b67f4487 | 645 | { |
5f04c603 | 646 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; |
b67f4487 | 647 | int i; |
6a99fb5f C |
648 | u8 tx_ser = 0; |
649 | u8 rx_ser = 0; | |
70091a3e | 650 | u8 slots = mcasp->tdm_slots; |
2952b27e | 651 | u8 max_active_serializers = (channels + slots - 1) / slots; |
dd093a0f | 652 | int active_serializers, numevt, n; |
487dce88 | 653 | u32 reg; |
b67f4487 | 654 | /* Default configuration */ |
40448e5e | 655 | if (mcasp->version < MCASP_VERSION_3) |
f68205a7 | 656 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
657 | |
658 | /* All PINS as McASP */ | |
f68205a7 | 659 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
660 | |
661 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
662 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
663 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 664 | } else { |
f68205a7 PU |
665 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
666 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
667 | } |
668 | ||
70091a3e | 669 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
670 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
671 | mcasp->serial_dir[i]); | |
70091a3e | 672 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 673 | tx_ser < max_active_serializers) { |
f68205a7 | 674 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 675 | tx_ser++; |
70091a3e | 676 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 677 | rx_ser < max_active_serializers) { |
f68205a7 | 678 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 679 | rx_ser++; |
2952b27e | 680 | } else { |
f68205a7 PU |
681 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
682 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
683 | } |
684 | } | |
685 | ||
0bf0e8ae PU |
686 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
687 | active_serializers = tx_ser; | |
688 | numevt = mcasp->txnumevt; | |
689 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
690 | } else { | |
691 | active_serializers = rx_ser; | |
692 | numevt = mcasp->rxnumevt; | |
693 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
694 | } | |
ecf327c7 | 695 | |
0bf0e8ae | 696 | if (active_serializers < max_active_serializers) { |
70091a3e | 697 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
0bf0e8ae PU |
698 | "enabled in mcasp (%d)\n", channels, |
699 | active_serializers * slots); | |
ecf327c7 DM |
700 | return -EINVAL; |
701 | } | |
702 | ||
0bf0e8ae | 703 | /* AFIFO is not in use */ |
5f04c603 PU |
704 | if (!numevt) { |
705 | /* Configure the burst size for platform drivers */ | |
33445643 PU |
706 | if (active_serializers > 1) { |
707 | /* | |
708 | * If more than one serializers are in use we have one | |
709 | * DMA request to provide data for all serializers. | |
710 | * For example if three serializers are enabled the DMA | |
711 | * need to transfer three words per DMA request. | |
712 | */ | |
33445643 PU |
713 | dma_data->maxburst = active_serializers; |
714 | } else { | |
33445643 PU |
715 | dma_data->maxburst = 0; |
716 | } | |
0bf0e8ae | 717 | return 0; |
5f04c603 | 718 | } |
6a99fb5f | 719 | |
dd093a0f PU |
720 | if (period_words % active_serializers) { |
721 | dev_err(mcasp->dev, "Invalid combination of period words and " | |
722 | "active serializers: %d, %d\n", period_words, | |
723 | active_serializers); | |
724 | return -EINVAL; | |
725 | } | |
726 | ||
727 | /* | |
728 | * Calculate the optimal AFIFO depth for platform side: | |
729 | * The number of words for numevt need to be in steps of active | |
730 | * serializers. | |
731 | */ | |
732 | n = numevt % active_serializers; | |
733 | if (n) | |
734 | numevt += (active_serializers - n); | |
735 | while (period_words % numevt && numevt > 0) | |
736 | numevt -= active_serializers; | |
737 | if (numevt <= 0) | |
0bf0e8ae | 738 | numevt = active_serializers; |
487dce88 | 739 | |
0bf0e8ae PU |
740 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
741 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); | |
2952b27e | 742 | |
5f04c603 | 743 | /* Configure the burst size for platform drivers */ |
33445643 PU |
744 | if (numevt == 1) |
745 | numevt = 0; | |
5f04c603 PU |
746 | dma_data->maxburst = numevt; |
747 | ||
2952b27e | 748 | return 0; |
b67f4487 C |
749 | } |
750 | ||
18a4f557 MLC |
751 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, |
752 | int channels) | |
b67f4487 C |
753 | { |
754 | int i, active_slots; | |
18a4f557 MLC |
755 | int total_slots; |
756 | int active_serializers; | |
b67f4487 | 757 | u32 mask = 0; |
cbc7956c | 758 | u32 busel = 0; |
b67f4487 | 759 | |
18a4f557 MLC |
760 | total_slots = mcasp->tdm_slots; |
761 | ||
762 | /* | |
763 | * If more than one serializer is needed, then use them with | |
764 | * their specified tdm_slots count. Otherwise, one serializer | |
765 | * can cope with the transaction using as many slots as channels | |
766 | * in the stream, requires channels symmetry | |
767 | */ | |
768 | active_serializers = (channels + total_slots - 1) / total_slots; | |
769 | if (active_serializers == 1) | |
770 | active_slots = channels; | |
771 | else | |
772 | active_slots = total_slots; | |
773 | ||
b67f4487 C |
774 | for (i = 0; i < active_slots; i++) |
775 | mask |= (1 << i); | |
776 | ||
f68205a7 | 777 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 778 | |
cbc7956c PU |
779 | if (!mcasp->dat_port) |
780 | busel = TXSEL; | |
781 | ||
2c56c4c2 PU |
782 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
783 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
784 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
18a4f557 | 785 | FSXMOD(total_slots), FSXMOD(0x1FF)); |
2c56c4c2 PU |
786 | |
787 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
788 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
789 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
18a4f557 | 790 | FSRMOD(total_slots), FSRMOD(0x1FF)); |
2c56c4c2 PU |
791 | |
792 | return 0; | |
b67f4487 C |
793 | } |
794 | ||
795 | /* S/PDIF */ | |
6479285d DM |
796 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, |
797 | unsigned int rate) | |
b67f4487 | 798 | { |
6479285d DM |
799 | u32 cs_value = 0; |
800 | u8 *cs_bytes = (u8*) &cs_value; | |
801 | ||
b67f4487 C |
802 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
803 | and LSB first */ | |
f68205a7 | 804 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
805 | |
806 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 807 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
808 | |
809 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 810 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
811 | |
812 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 813 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 814 | |
f68205a7 | 815 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
816 | |
817 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 818 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
819 | |
820 | /* Enable the DIT */ | |
f68205a7 | 821 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 | 822 | |
6479285d DM |
823 | /* Set S/PDIF channel status bits */ |
824 | cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; | |
825 | cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; | |
826 | ||
827 | switch (rate) { | |
828 | case 22050: | |
829 | cs_bytes[3] |= IEC958_AES3_CON_FS_22050; | |
830 | break; | |
831 | case 24000: | |
832 | cs_bytes[3] |= IEC958_AES3_CON_FS_24000; | |
833 | break; | |
834 | case 32000: | |
835 | cs_bytes[3] |= IEC958_AES3_CON_FS_32000; | |
836 | break; | |
837 | case 44100: | |
838 | cs_bytes[3] |= IEC958_AES3_CON_FS_44100; | |
839 | break; | |
840 | case 48000: | |
841 | cs_bytes[3] |= IEC958_AES3_CON_FS_48000; | |
842 | break; | |
843 | case 88200: | |
844 | cs_bytes[3] |= IEC958_AES3_CON_FS_88200; | |
845 | break; | |
846 | case 96000: | |
847 | cs_bytes[3] |= IEC958_AES3_CON_FS_96000; | |
848 | break; | |
849 | case 176400: | |
850 | cs_bytes[3] |= IEC958_AES3_CON_FS_176400; | |
851 | break; | |
852 | case 192000: | |
853 | cs_bytes[3] |= IEC958_AES3_CON_FS_192000; | |
854 | break; | |
855 | default: | |
856 | printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); | |
857 | return -EINVAL; | |
858 | } | |
859 | ||
860 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); | |
861 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); | |
862 | ||
2c56c4c2 | 863 | return 0; |
b67f4487 C |
864 | } |
865 | ||
866 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, | |
867 | struct snd_pcm_hw_params *params, | |
868 | struct snd_soc_dai *cpu_dai) | |
869 | { | |
70091a3e | 870 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 871 | int word_length; |
a7e46bd9 | 872 | int channels = params_channels(params); |
dd093a0f | 873 | int period_size = params_period_size(params); |
2c56c4c2 | 874 | int ret; |
ab8b14b6 | 875 | |
8267525c DM |
876 | /* |
877 | * If mcasp is BCLK master, and a BCLK divider was not provided by | |
878 | * the machine driver, we need to calculate the ratio. | |
879 | */ | |
880 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
ab8b14b6 | 881 | unsigned int bclk_freq = snd_soc_params_to_bclk(params); |
0929878f | 882 | unsigned int div = mcasp->sysclk_freq / bclk_freq; |
ab8b14b6 | 883 | if (mcasp->sysclk_freq % bclk_freq != 0) { |
0929878f JS |
884 | if (((mcasp->sysclk_freq / div) - bclk_freq) > |
885 | (bclk_freq - (mcasp->sysclk_freq / (div+1)))) | |
886 | div++; | |
887 | dev_warn(mcasp->dev, | |
888 | "Inaccurate BCLK: %u Hz / %u != %u Hz\n", | |
889 | mcasp->sysclk_freq, div, bclk_freq); | |
ab8b14b6 | 890 | } |
8813543e | 891 | __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0); |
ab8b14b6 JS |
892 | } |
893 | ||
dd093a0f PU |
894 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
895 | period_size * channels, channels); | |
0f7d9a63 PU |
896 | if (ret) |
897 | return ret; | |
898 | ||
70091a3e | 899 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
6479285d | 900 | ret = mcasp_dit_hw_param(mcasp, params_rate(params)); |
b67f4487 | 901 | else |
18a4f557 MLC |
902 | ret = mcasp_i2s_hw_param(mcasp, substream->stream, |
903 | channels); | |
2c56c4c2 PU |
904 | |
905 | if (ret) | |
906 | return ret; | |
b67f4487 C |
907 | |
908 | switch (params_format(params)) { | |
0a9d1385 | 909 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 | 910 | case SNDRV_PCM_FORMAT_S8: |
ba764b3d | 911 | word_length = 8; |
b67f4487 C |
912 | break; |
913 | ||
0a9d1385 | 914 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 | 915 | case SNDRV_PCM_FORMAT_S16_LE: |
ba764b3d | 916 | word_length = 16; |
b67f4487 C |
917 | break; |
918 | ||
21eb24d8 DM |
919 | case SNDRV_PCM_FORMAT_U24_3LE: |
920 | case SNDRV_PCM_FORMAT_S24_3LE: | |
ba764b3d | 921 | word_length = 24; |
21eb24d8 DM |
922 | break; |
923 | ||
6b7fa011 DM |
924 | case SNDRV_PCM_FORMAT_U24_LE: |
925 | case SNDRV_PCM_FORMAT_S24_LE: | |
182bef86 PU |
926 | word_length = 24; |
927 | break; | |
928 | ||
0a9d1385 | 929 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 | 930 | case SNDRV_PCM_FORMAT_S32_LE: |
ba764b3d | 931 | word_length = 32; |
b67f4487 C |
932 | break; |
933 | ||
934 | default: | |
935 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
936 | return -EINVAL; | |
937 | } | |
6a99fb5f | 938 | |
70091a3e | 939 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 | 940 | |
11277833 PU |
941 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) |
942 | mcasp->channels = channels; | |
943 | ||
b67f4487 C |
944 | return 0; |
945 | } | |
946 | ||
947 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
948 | int cmd, struct snd_soc_dai *cpu_dai) | |
949 | { | |
70091a3e | 950 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
951 | int ret = 0; |
952 | ||
953 | switch (cmd) { | |
b67f4487 | 954 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
955 | case SNDRV_PCM_TRIGGER_START: |
956 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 957 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 958 | break; |
b67f4487 | 959 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 960 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 961 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 962 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
963 | break; |
964 | ||
965 | default: | |
966 | ret = -EINVAL; | |
967 | } | |
968 | ||
969 | return ret; | |
970 | } | |
971 | ||
11277833 PU |
972 | static int davinci_mcasp_startup(struct snd_pcm_substream *substream, |
973 | struct snd_soc_dai *cpu_dai) | |
974 | { | |
975 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
976 | u32 max_channels = 0; | |
977 | int i, dir; | |
978 | ||
a7a3324a MLC |
979 | mcasp->substreams[substream->stream] = substream; |
980 | ||
11277833 PU |
981 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
982 | return 0; | |
983 | ||
984 | /* | |
985 | * Limit the maximum allowed channels for the first stream: | |
986 | * number of serializers for the direction * tdm slots per serializer | |
987 | */ | |
988 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
989 | dir = TX_MODE; | |
990 | else | |
991 | dir = RX_MODE; | |
992 | ||
993 | for (i = 0; i < mcasp->num_serializer; i++) { | |
994 | if (mcasp->serial_dir[i] == dir) | |
995 | max_channels++; | |
996 | } | |
997 | max_channels *= mcasp->tdm_slots; | |
998 | /* | |
999 | * If the already active stream has less channels than the calculated | |
1000 | * limnit based on the seirializers * tdm_slots, we need to use that as | |
1001 | * a constraint for the second stream. | |
1002 | * Otherwise (first stream or less allowed channels) we use the | |
1003 | * calculated constraint. | |
1004 | */ | |
1005 | if (mcasp->channels && mcasp->channels < max_channels) | |
1006 | max_channels = mcasp->channels; | |
1007 | ||
1008 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1009 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1010 | 2, max_channels); | |
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, | |
1015 | struct snd_soc_dai *cpu_dai) | |
1016 | { | |
1017 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
1018 | ||
a7a3324a MLC |
1019 | mcasp->substreams[substream->stream] = NULL; |
1020 | ||
11277833 PU |
1021 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
1022 | return; | |
1023 | ||
1024 | if (!cpu_dai->active) | |
1025 | mcasp->channels = 0; | |
1026 | } | |
1027 | ||
85e7652d | 1028 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
11277833 PU |
1029 | .startup = davinci_mcasp_startup, |
1030 | .shutdown = davinci_mcasp_shutdown, | |
b67f4487 C |
1031 | .trigger = davinci_mcasp_trigger, |
1032 | .hw_params = davinci_mcasp_hw_params, | |
1033 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 1034 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 1035 | .set_sysclk = davinci_mcasp_set_sysclk, |
b67f4487 C |
1036 | }; |
1037 | ||
d5902f69 PU |
1038 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
1039 | { | |
1040 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
1041 | ||
9759e7ef PU |
1042 | dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
1043 | dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
d5902f69 PU |
1044 | |
1045 | return 0; | |
1046 | } | |
1047 | ||
135014ad PU |
1048 | #ifdef CONFIG_PM_SLEEP |
1049 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
1050 | { | |
1051 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1052 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1053 | u32 reg; |
1cc0c054 | 1054 | int i; |
135014ad | 1055 | |
1cc0c054 PU |
1056 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1057 | context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); | |
135014ad | 1058 | |
f114ce60 PU |
1059 | if (mcasp->txnumevt) { |
1060 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1061 | context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); | |
1062 | } | |
1063 | if (mcasp->rxnumevt) { | |
1064 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1065 | context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); | |
1066 | } | |
135014ad | 1067 | |
f114ce60 PU |
1068 | for (i = 0; i < mcasp->num_serializer; i++) |
1069 | context->xrsr_regs[i] = mcasp_get_reg(mcasp, | |
1070 | DAVINCI_MCASP_XRSRCTL_REG(i)); | |
135014ad PU |
1071 | |
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
1076 | { | |
1077 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1078 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1079 | u32 reg; |
1cc0c054 | 1080 | int i; |
790bb94b | 1081 | |
1cc0c054 PU |
1082 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1083 | mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); | |
135014ad | 1084 | |
f114ce60 PU |
1085 | if (mcasp->txnumevt) { |
1086 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1087 | mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); | |
1088 | } | |
1089 | if (mcasp->rxnumevt) { | |
1090 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1091 | mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); | |
1092 | } | |
790bb94b | 1093 | |
f114ce60 PU |
1094 | for (i = 0; i < mcasp->num_serializer; i++) |
1095 | mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), | |
1096 | context->xrsr_regs[i]); | |
135014ad PU |
1097 | |
1098 | return 0; | |
1099 | } | |
1100 | #else | |
1101 | #define davinci_mcasp_suspend NULL | |
1102 | #define davinci_mcasp_resume NULL | |
1103 | #endif | |
1104 | ||
ed29cd5e PU |
1105 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
1106 | ||
0a9d1385 BG |
1107 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
1108 | SNDRV_PCM_FMTBIT_U8 | \ | |
1109 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
1110 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
1111 | SNDRV_PCM_FMTBIT_S24_LE | \ |
1112 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
1113 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
1114 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
1115 | SNDRV_PCM_FMTBIT_S32_LE | \ |
1116 | SNDRV_PCM_FMTBIT_U32_LE) | |
1117 | ||
f0fba2ad | 1118 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 1119 | { |
f0fba2ad | 1120 | .name = "davinci-mcasp.0", |
d5902f69 | 1121 | .probe = davinci_mcasp_dai_probe, |
135014ad PU |
1122 | .suspend = davinci_mcasp_suspend, |
1123 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
1124 | .playback = { |
1125 | .channels_min = 2, | |
2952b27e | 1126 | .channels_max = 32 * 16, |
b67f4487 | 1127 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1128 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1129 | }, |
1130 | .capture = { | |
1131 | .channels_min = 2, | |
2952b27e | 1132 | .channels_max = 32 * 16, |
b67f4487 | 1133 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1134 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1135 | }, |
1136 | .ops = &davinci_mcasp_dai_ops, | |
1137 | ||
d75249f5 | 1138 | .symmetric_samplebits = 1, |
b67f4487 C |
1139 | }, |
1140 | { | |
58e48d97 | 1141 | .name = "davinci-mcasp.1", |
d5902f69 | 1142 | .probe = davinci_mcasp_dai_probe, |
b67f4487 C |
1143 | .playback = { |
1144 | .channels_min = 1, | |
1145 | .channels_max = 384, | |
1146 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 1147 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1148 | }, |
1149 | .ops = &davinci_mcasp_dai_ops, | |
1150 | }, | |
1151 | ||
1152 | }; | |
b67f4487 | 1153 | |
eeef0eda KM |
1154 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
1155 | .name = "davinci-mcasp", | |
1156 | }; | |
1157 | ||
256ba181 | 1158 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 1159 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
1160 | .tx_dma_offset = 0x400, |
1161 | .rx_dma_offset = 0x400, | |
256ba181 JS |
1162 | .version = MCASP_VERSION_1, |
1163 | }; | |
1164 | ||
d1debafc | 1165 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
1166 | .tx_dma_offset = 0x2000, |
1167 | .rx_dma_offset = 0x2000, | |
256ba181 JS |
1168 | .version = MCASP_VERSION_2, |
1169 | }; | |
1170 | ||
d1debafc | 1171 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
1172 | .tx_dma_offset = 0, |
1173 | .rx_dma_offset = 0, | |
256ba181 JS |
1174 | .version = MCASP_VERSION_3, |
1175 | }; | |
1176 | ||
d1debafc | 1177 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
453c4990 PU |
1178 | .tx_dma_offset = 0x200, |
1179 | .rx_dma_offset = 0x284, | |
453c4990 PU |
1180 | .version = MCASP_VERSION_4, |
1181 | }; | |
1182 | ||
3e3b8c34 HG |
1183 | static const struct of_device_id mcasp_dt_ids[] = { |
1184 | { | |
1185 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 1186 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
1187 | }, |
1188 | { | |
1189 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 1190 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 1191 | }, |
e5ec69da | 1192 | { |
3af9e031 | 1193 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 1194 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 1195 | }, |
453c4990 PU |
1196 | { |
1197 | .compatible = "ti,dra7-mcasp-audio", | |
1198 | .data = &dra7_mcasp_pdata, | |
1199 | }, | |
3e3b8c34 HG |
1200 | { /* sentinel */ } |
1201 | }; | |
1202 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
1203 | ||
ae726e93 PU |
1204 | static int mcasp_reparent_fck(struct platform_device *pdev) |
1205 | { | |
1206 | struct device_node *node = pdev->dev.of_node; | |
1207 | struct clk *gfclk, *parent_clk; | |
1208 | const char *parent_name; | |
1209 | int ret; | |
1210 | ||
1211 | if (!node) | |
1212 | return 0; | |
1213 | ||
1214 | parent_name = of_get_property(node, "fck_parent", NULL); | |
1215 | if (!parent_name) | |
1216 | return 0; | |
1217 | ||
1218 | gfclk = clk_get(&pdev->dev, "fck"); | |
1219 | if (IS_ERR(gfclk)) { | |
1220 | dev_err(&pdev->dev, "failed to get fck\n"); | |
1221 | return PTR_ERR(gfclk); | |
1222 | } | |
1223 | ||
1224 | parent_clk = clk_get(NULL, parent_name); | |
1225 | if (IS_ERR(parent_clk)) { | |
1226 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
1227 | ret = PTR_ERR(parent_clk); | |
1228 | goto err1; | |
1229 | } | |
1230 | ||
1231 | ret = clk_set_parent(gfclk, parent_clk); | |
1232 | if (ret) { | |
1233 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
1234 | goto err2; | |
1235 | } | |
1236 | ||
1237 | err2: | |
1238 | clk_put(parent_clk); | |
1239 | err1: | |
1240 | clk_put(gfclk); | |
1241 | return ret; | |
1242 | } | |
1243 | ||
d1debafc | 1244 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
1245 | struct platform_device *pdev) |
1246 | { | |
1247 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 1248 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 1249 | const struct of_device_id *match = |
ea421eb1 | 1250 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 1251 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
1252 | |
1253 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
1254 | u32 val; |
1255 | int i, ret = 0; | |
1256 | ||
1257 | if (pdev->dev.platform_data) { | |
1258 | pdata = pdev->dev.platform_data; | |
1259 | return pdata; | |
1260 | } else if (match) { | |
d1debafc | 1261 | pdata = (struct davinci_mcasp_pdata*) match->data; |
3e3b8c34 HG |
1262 | } else { |
1263 | /* control shouldn't reach here. something is wrong */ | |
1264 | ret = -EINVAL; | |
1265 | goto nodata; | |
1266 | } | |
1267 | ||
3e3b8c34 HG |
1268 | ret = of_property_read_u32(np, "op-mode", &val); |
1269 | if (ret >= 0) | |
1270 | pdata->op_mode = val; | |
1271 | ||
1272 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
1273 | if (ret >= 0) { |
1274 | if (val < 2 || val > 32) { | |
1275 | dev_err(&pdev->dev, | |
1276 | "tdm-slots must be in rage [2-32]\n"); | |
1277 | ret = -EINVAL; | |
1278 | goto nodata; | |
1279 | } | |
1280 | ||
3e3b8c34 | 1281 | pdata->tdm_slots = val; |
2952b27e | 1282 | } |
3e3b8c34 | 1283 | |
3e3b8c34 HG |
1284 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
1285 | val /= sizeof(u32); | |
3e3b8c34 | 1286 | if (of_serial_dir32) { |
1427e660 PU |
1287 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
1288 | (sizeof(*of_serial_dir) * val), | |
1289 | GFP_KERNEL); | |
3e3b8c34 HG |
1290 | if (!of_serial_dir) { |
1291 | ret = -ENOMEM; | |
1292 | goto nodata; | |
1293 | } | |
1294 | ||
1427e660 | 1295 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
1296 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
1297 | ||
1427e660 | 1298 | pdata->num_serializer = val; |
3e3b8c34 HG |
1299 | pdata->serial_dir = of_serial_dir; |
1300 | } | |
1301 | ||
4023fe6f JS |
1302 | ret = of_property_match_string(np, "dma-names", "tx"); |
1303 | if (ret < 0) | |
1304 | goto nodata; | |
1305 | ||
1306 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1307 | &dma_spec); | |
1308 | if (ret < 0) | |
1309 | goto nodata; | |
1310 | ||
1311 | pdata->tx_dma_channel = dma_spec.args[0]; | |
1312 | ||
caa1d794 PU |
1313 | /* RX is not valid in DIT mode */ |
1314 | if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) { | |
1315 | ret = of_property_match_string(np, "dma-names", "rx"); | |
1316 | if (ret < 0) | |
1317 | goto nodata; | |
4023fe6f | 1318 | |
caa1d794 PU |
1319 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, |
1320 | &dma_spec); | |
1321 | if (ret < 0) | |
1322 | goto nodata; | |
4023fe6f | 1323 | |
caa1d794 PU |
1324 | pdata->rx_dma_channel = dma_spec.args[0]; |
1325 | } | |
4023fe6f | 1326 | |
3e3b8c34 HG |
1327 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1328 | if (ret >= 0) | |
1329 | pdata->txnumevt = val; | |
1330 | ||
1331 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1332 | if (ret >= 0) | |
1333 | pdata->rxnumevt = val; | |
1334 | ||
1335 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1336 | if (ret >= 0) | |
1337 | pdata->sram_size_playback = val; | |
1338 | ||
1339 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1340 | if (ret >= 0) | |
1341 | pdata->sram_size_capture = val; | |
1342 | ||
1343 | return pdata; | |
1344 | ||
1345 | nodata: | |
1346 | if (ret < 0) { | |
1347 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1348 | ret); | |
1349 | pdata = NULL; | |
1350 | } | |
1351 | return pdata; | |
1352 | } | |
1353 | ||
b67f4487 C |
1354 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1355 | { | |
8de131f2 | 1356 | struct snd_dmaengine_dai_dma_data *dma_data; |
256ba181 | 1357 | struct resource *mem, *ioarea, *res, *dat; |
d1debafc | 1358 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1359 | struct davinci_mcasp *mcasp; |
a7a3324a | 1360 | char *irq_name; |
9759e7ef | 1361 | int *dma; |
a7a3324a | 1362 | int irq; |
96d31e2b | 1363 | int ret; |
b67f4487 | 1364 | |
3e3b8c34 HG |
1365 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1366 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1367 | return -EINVAL; | |
1368 | } | |
1369 | ||
70091a3e | 1370 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1371 | GFP_KERNEL); |
70091a3e | 1372 | if (!mcasp) |
b67f4487 C |
1373 | return -ENOMEM; |
1374 | ||
3e3b8c34 HG |
1375 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1376 | if (!pdata) { | |
1377 | dev_err(&pdev->dev, "no platform data\n"); | |
1378 | return -EINVAL; | |
1379 | } | |
1380 | ||
256ba181 | 1381 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1382 | if (!mem) { |
70091a3e | 1383 | dev_warn(mcasp->dev, |
256ba181 JS |
1384 | "\"mpu\" mem resource not found, using index 0\n"); |
1385 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1386 | if (!mem) { | |
1387 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1388 | return -ENODEV; | |
1389 | } | |
b67f4487 C |
1390 | } |
1391 | ||
96d31e2b | 1392 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
d852f446 | 1393 | resource_size(mem), pdev->name); |
b67f4487 C |
1394 | if (!ioarea) { |
1395 | dev_err(&pdev->dev, "Audio region already claimed\n"); | |
96d31e2b | 1396 | return -EBUSY; |
b67f4487 C |
1397 | } |
1398 | ||
10884347 | 1399 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1400 | |
10884347 HG |
1401 | ret = pm_runtime_get_sync(&pdev->dev); |
1402 | if (IS_ERR_VALUE(ret)) { | |
1403 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); | |
7771ef32 | 1404 | pm_runtime_disable(&pdev->dev); |
10884347 HG |
1405 | return ret; |
1406 | } | |
b67f4487 | 1407 | |
70091a3e PU |
1408 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
1409 | if (!mcasp->base) { | |
4f82f028 VB |
1410 | dev_err(&pdev->dev, "ioremap failed\n"); |
1411 | ret = -ENOMEM; | |
b6bb3709 | 1412 | goto err; |
4f82f028 VB |
1413 | } |
1414 | ||
70091a3e | 1415 | mcasp->op_mode = pdata->op_mode; |
1a5923da PU |
1416 | /* sanity check for tdm slots parameter */ |
1417 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { | |
1418 | if (pdata->tdm_slots < 2) { | |
1419 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1420 | pdata->tdm_slots); | |
1421 | mcasp->tdm_slots = 2; | |
1422 | } else if (pdata->tdm_slots > 32) { | |
1423 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1424 | pdata->tdm_slots); | |
1425 | mcasp->tdm_slots = 32; | |
1426 | } else { | |
1427 | mcasp->tdm_slots = pdata->tdm_slots; | |
1428 | } | |
1429 | } | |
1430 | ||
70091a3e | 1431 | mcasp->num_serializer = pdata->num_serializer; |
f114ce60 PU |
1432 | #ifdef CONFIG_PM_SLEEP |
1433 | mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev, | |
1434 | sizeof(u32) * mcasp->num_serializer, | |
1435 | GFP_KERNEL); | |
1436 | #endif | |
70091a3e PU |
1437 | mcasp->serial_dir = pdata->serial_dir; |
1438 | mcasp->version = pdata->version; | |
1439 | mcasp->txnumevt = pdata->txnumevt; | |
1440 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1441 | |
70091a3e | 1442 | mcasp->dev = &pdev->dev; |
b67f4487 | 1443 | |
5a1b8a80 PU |
1444 | irq = platform_get_irq_byname(pdev, "common"); |
1445 | if (irq >= 0) { | |
1446 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common\n", | |
1447 | dev_name(&pdev->dev)); | |
1448 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1449 | davinci_mcasp_common_irq_handler, | |
8f511ffb PU |
1450 | IRQF_ONESHOT | IRQF_SHARED, |
1451 | irq_name, mcasp); | |
5a1b8a80 PU |
1452 | if (ret) { |
1453 | dev_err(&pdev->dev, "common IRQ request failed\n"); | |
1454 | goto err; | |
1455 | } | |
1456 | ||
1457 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
1458 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
1459 | } | |
1460 | ||
a7a3324a MLC |
1461 | irq = platform_get_irq_byname(pdev, "rx"); |
1462 | if (irq >= 0) { | |
1463 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx\n", | |
1464 | dev_name(&pdev->dev)); | |
1465 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1466 | davinci_mcasp_rx_irq_handler, | |
1467 | IRQF_ONESHOT, irq_name, mcasp); | |
1468 | if (ret) { | |
1469 | dev_err(&pdev->dev, "RX IRQ request failed\n"); | |
1470 | goto err; | |
1471 | } | |
1472 | ||
1473 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
1474 | } | |
1475 | ||
1476 | irq = platform_get_irq_byname(pdev, "tx"); | |
1477 | if (irq >= 0) { | |
1478 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx\n", | |
1479 | dev_name(&pdev->dev)); | |
1480 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1481 | davinci_mcasp_tx_irq_handler, | |
1482 | IRQF_ONESHOT, irq_name, mcasp); | |
1483 | if (ret) { | |
1484 | dev_err(&pdev->dev, "TX IRQ request failed\n"); | |
1485 | goto err; | |
1486 | } | |
1487 | ||
1488 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
1489 | } | |
1490 | ||
256ba181 | 1491 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1492 | if (dat) |
1493 | mcasp->dat_port = true; | |
256ba181 | 1494 | |
8de131f2 | 1495 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
cbc7956c | 1496 | if (dat) |
9759e7ef | 1497 | dma_data->addr = dat->start; |
cbc7956c | 1498 | else |
9759e7ef | 1499 | dma_data->addr = mem->start + pdata->tx_dma_offset; |
453c4990 | 1500 | |
9759e7ef | 1501 | dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; |
b67f4487 | 1502 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 1503 | if (res) |
9759e7ef | 1504 | *dma = res->start; |
4023fe6f | 1505 | else |
9759e7ef | 1506 | *dma = pdata->tx_dma_channel; |
92e2a6f6 | 1507 | |
8de131f2 PU |
1508 | /* dmaengine filter data for DT and non-DT boot */ |
1509 | if (pdev->dev.of_node) | |
1510 | dma_data->filter_data = "tx"; | |
1511 | else | |
9759e7ef | 1512 | dma_data->filter_data = dma; |
8de131f2 | 1513 | |
caa1d794 PU |
1514 | /* RX is not valid in DIT mode */ |
1515 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { | |
caa1d794 | 1516 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
caa1d794 | 1517 | if (dat) |
9759e7ef | 1518 | dma_data->addr = dat->start; |
caa1d794 | 1519 | else |
9759e7ef | 1520 | dma_data->addr = mem->start + pdata->rx_dma_offset; |
caa1d794 | 1521 | |
9759e7ef | 1522 | dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; |
caa1d794 PU |
1523 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
1524 | if (res) | |
9759e7ef | 1525 | *dma = res->start; |
caa1d794 | 1526 | else |
9759e7ef | 1527 | *dma = pdata->rx_dma_channel; |
caa1d794 PU |
1528 | |
1529 | /* dmaengine filter data for DT and non-DT boot */ | |
1530 | if (pdev->dev.of_node) | |
1531 | dma_data->filter_data = "rx"; | |
1532 | else | |
9759e7ef | 1533 | dma_data->filter_data = dma; |
caa1d794 | 1534 | } |
453c4990 | 1535 | |
cbc7956c PU |
1536 | if (mcasp->version < MCASP_VERSION_3) { |
1537 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 1538 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
1539 | mcasp->dat_port = true; |
1540 | } else { | |
1541 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1542 | } | |
b67f4487 | 1543 | |
70091a3e | 1544 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1545 | |
1546 | mcasp_reparent_fck(pdev); | |
1547 | ||
b6bb3709 PU |
1548 | ret = devm_snd_soc_register_component(&pdev->dev, |
1549 | &davinci_mcasp_component, | |
1550 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1551 | |
1552 | if (ret != 0) | |
b6bb3709 | 1553 | goto err; |
f08095a4 | 1554 | |
d5c6c59a | 1555 | switch (mcasp->version) { |
f3f9cfa8 PU |
1556 | #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \ |
1557 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1558 | IS_MODULE(CONFIG_SND_EDMA_SOC)) | |
9759e7ef PU |
1559 | case MCASP_VERSION_1: |
1560 | case MCASP_VERSION_2: | |
f3f9cfa8 PU |
1561 | case MCASP_VERSION_3: |
1562 | ret = edma_pcm_platform_register(&pdev->dev); | |
1563 | break; | |
1564 | #endif | |
7f28f357 JS |
1565 | #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \ |
1566 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1567 | IS_MODULE(CONFIG_SND_OMAP_SOC)) | |
d5c6c59a PU |
1568 | case MCASP_VERSION_4: |
1569 | ret = omap_pcm_platform_register(&pdev->dev); | |
1570 | break; | |
7f28f357 | 1571 | #endif |
d5c6c59a PU |
1572 | default: |
1573 | dev_err(&pdev->dev, "Invalid McASP version: %d\n", | |
1574 | mcasp->version); | |
1575 | ret = -EINVAL; | |
1576 | break; | |
1577 | } | |
1578 | ||
1579 | if (ret) { | |
1580 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
b6bb3709 | 1581 | goto err; |
f08095a4 HG |
1582 | } |
1583 | ||
b67f4487 C |
1584 | return 0; |
1585 | ||
b6bb3709 | 1586 | err: |
10884347 HG |
1587 | pm_runtime_put_sync(&pdev->dev); |
1588 | pm_runtime_disable(&pdev->dev); | |
b67f4487 C |
1589 | return ret; |
1590 | } | |
1591 | ||
1592 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1593 | { | |
10884347 HG |
1594 | pm_runtime_put_sync(&pdev->dev); |
1595 | pm_runtime_disable(&pdev->dev); | |
b67f4487 | 1596 | |
b67f4487 C |
1597 | return 0; |
1598 | } | |
1599 | ||
1600 | static struct platform_driver davinci_mcasp_driver = { | |
1601 | .probe = davinci_mcasp_probe, | |
1602 | .remove = davinci_mcasp_remove, | |
1603 | .driver = { | |
1604 | .name = "davinci-mcasp", | |
ea421eb1 | 1605 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
1606 | }, |
1607 | }; | |
1608 | ||
f9b8a514 | 1609 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1610 | |
1611 | MODULE_AUTHOR("Steve Chen"); | |
1612 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1613 | MODULE_LICENSE("GPL"); |