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Merge tag 'dmaengine-fixes-3.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / sound / soc / davinci / davinci-mcasp.c
CommitLineData
b67f4487
C		 1/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
5a0e3ad6 21#include <linux/slab.h>
b67f4487
C		 22#include <linux/delay.h>
23#include <linux/io.h>
ae726e93 24#include <linux/clk.h>
10884347 25#include <linux/pm_runtime.h>
3e3b8c34
HG		 26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
b67f4487
C		 29
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/initval.h>
34#include <sound/soc.h>
453c4990 35#include <sound/dmaengine_pcm.h>
b67f4487
C		 36
37#include "davinci-pcm.h"
38#include "davinci-mcasp.h"
39
70091a3e 40struct davinci_mcasp {
21400a72 41 struct davinci_pcm_dma_params dma_params[2];
453c4990 42 struct snd_dmaengine_dai_dma_data dma_data[2];
21400a72 43 void __iomem *base;
487dce88 44 u32 fifo_base;
21400a72
PU		 45 struct device *dev;
46
47 /* McASP specific data */
48 int tdm_slots;
49 u8 op_mode;
50 u8 num_serializer;
51 u8 *serial_dir;
52 u8 version;
53 u16 bclk_lrclk_ratio;
4dcb5a0b 54 int streams;
21400a72
PU		 55
56 /* McASP FIFO related */
57 u8 txnumevt;
58 u8 rxnumevt;
59
cbc7956c
PU		 60 bool dat_port;
61
21400a72
PU		 62#ifdef CONFIG_PM_SLEEP
63 struct {
64 u32 txfmtctl;
65 u32 rxfmtctl;
66 u32 txfmt;
67 u32 rxfmt;
68 u32 aclkxctl;
69 u32 aclkrctl;
70 u32 pdir;
71 } context;
72#endif
73};
74
f68205a7
PU		 75static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
76 u32 val)
b67f4487 77{
f68205a7 78 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 79 __raw_writel(__raw_readl(reg) | val, reg);
80}
81
f68205a7
PU		 82static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
83 u32 val)
b67f4487 84{
f68205a7 85 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 86 __raw_writel((__raw_readl(reg) & ~(val)), reg);
87}
88
f68205a7
PU		 89static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
90 u32 val, u32 mask)
b67f4487 91{
f68205a7 92 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 93 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
94}
95
f68205a7
PU		 96static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
97 u32 val)
b67f4487 98{
f68205a7 99 __raw_writel(val, mcasp->base + offset);
b67f4487
C		 100}
101
f68205a7 102static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
b67f4487 103{
f68205a7 104 return (u32)__raw_readl(mcasp->base + offset);
b67f4487
C		 105}
106
f68205a7 107static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
b67f4487
C		 108{
109 int i = 0;
110
f68205a7 111 mcasp_set_bits(mcasp, ctl_reg, val);
b67f4487
C		 112
113 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
114 /* loop count is to avoid the lock-up */
115 for (i = 0; i < 1000; i++) {
f68205a7 116 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
b67f4487
C		 117 break;
118 }
119
f68205a7 120 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
b67f4487
C		 121 printk(KERN_ERR "GBLCTL write error\n");
122}
123
4dcb5a0b
PU		 124static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
125{
f68205a7
PU		 126 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
127 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
4dcb5a0b
PU		 128
129 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
130}
131
70091a3e 132static void mcasp_start_rx(struct davinci_mcasp *mcasp)
b67f4487 133{
f68205a7
PU		 134 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
135 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
4dcb5a0b
PU		 136
137 /*
138 * When ASYNC == 0 the transmit and receive sections operate
139 * synchronously from the transmit clock and frame sync. We need to make
140 * sure that the TX signlas are enabled when starting reception.
141 */
142 if (mcasp_is_synchronous(mcasp)) {
f68205a7
PU		 143 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
144 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
4dcb5a0b
PU		 145 }
146
f68205a7
PU		 147 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
148 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
b67f4487 149
f68205a7
PU		 150 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
151 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
152 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
b67f4487 153
f68205a7
PU		 154 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
155 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
4dcb5a0b
PU		 156
157 if (mcasp_is_synchronous(mcasp))
f68205a7 158 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
b67f4487
C		 159}
160
70091a3e 161static void mcasp_start_tx(struct davinci_mcasp *mcasp)
b67f4487 162{
6a99fb5f
C		 163 u8 offset = 0, i;
164 u32 cnt;
165
f68205a7
PU		 166 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
167 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
168 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
169 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
b67f4487 170
f68205a7
PU		 171 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
172 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
173 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
70091a3e
PU		 174 for (i = 0; i < mcasp->num_serializer; i++) {
175 if (mcasp->serial_dir[i] == TX_MODE) {
6a99fb5f
C		 176 offset = i;
177 break;
178 }
179 }
180
181 /* wait for TX ready */
182 cnt = 0;
f68205a7 183 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
6a99fb5f
C		 184 TXSTATE) && (cnt < 100000))
185 cnt++;
186
f68205a7 187 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
b67f4487
C		 188}
189
70091a3e 190static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
b67f4487 191{
487dce88
PU		 192 u32 reg;
193
4dcb5a0b
PU		 194 mcasp->streams++;
195
539d3d8c 196 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
70091a3e 197 if (mcasp->txnumevt) { /* enable FIFO */
487dce88 198 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
f68205a7
PU		 199 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
200 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
0d624275 201 }
70091a3e 202 mcasp_start_tx(mcasp);
539d3d8c 203 } else {
70091a3e 204 if (mcasp->rxnumevt) { /* enable FIFO */
487dce88 205 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
f68205a7
PU		 206 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
207 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
0d624275 208 }
70091a3e 209 mcasp_start_rx(mcasp);
539d3d8c 210 }
b67f4487
C		 211}
212
70091a3e 213static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
b67f4487 214{
4dcb5a0b
PU		 215 /*
216 * In synchronous mode stop the TX clocks if no other stream is
217 * running
218 */
219 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
f68205a7 220 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
4dcb5a0b 221
f68205a7
PU		 222 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
223 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
b67f4487
C		 224}
225
70091a3e 226static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
b67f4487 227{
4dcb5a0b
PU		 228 u32 val = 0;
229
230 /*
231 * In synchronous mode keep TX clocks running if the capture stream is
232 * still running.
233 */
234 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
235 val = TXHCLKRST | TXCLKRST | TXFSRST;
236
f68205a7
PU		 237 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
238 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
b67f4487
C		 239}
240
70091a3e 241static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
b67f4487 242{
487dce88
PU		 243 u32 reg;
244
4dcb5a0b
PU		 245 mcasp->streams--;
246
539d3d8c 247 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
70091a3e 248 if (mcasp->txnumevt) { /* disable FIFO */
487dce88 249 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
f68205a7 250 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
e5ec69da 251 }
70091a3e 252 mcasp_stop_tx(mcasp);
539d3d8c 253 } else {
70091a3e 254 if (mcasp->rxnumevt) { /* disable FIFO */
487dce88 255 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
f68205a7 256 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
e5ec69da 257 }
70091a3e 258 mcasp_stop_rx(mcasp);
539d3d8c 259 }
b67f4487
C		 260}
261
262static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
263 unsigned int fmt)
264{
70091a3e 265 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1d17a04e 266 int ret = 0;
b67f4487 267
1d17a04e 268 pm_runtime_get_sync(mcasp->dev);
5296cf2d
DM		 269 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
270 case SND_SOC_DAIFMT_DSP_B:
271 case SND_SOC_DAIFMT_AC97:
f68205a7
PU		 272 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
273 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
5296cf2d
DM		 274 break;
275 default:
276 /* configure a full-word SYNC pulse (LRCLK) */
f68205a7
PU		 277 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
278 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
5296cf2d
DM		 279
280 /* make 1st data bit occur one ACLK cycle after the frame sync */
f68205a7
PU		 281 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
282 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
5296cf2d
DM		 283 break;
284 }
285
b67f4487
C		 286 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
287 case SND_SOC_DAIFMT_CBS_CFS:
288 /* codec is clock and frame slave */
f68205a7
PU		 289 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
290 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 291
f68205a7
PU		 292 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
293 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 294
f68205a7
PU		 295 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
296 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
b67f4487 297 break;
517ee6cf
C		 298 case SND_SOC_DAIFMT_CBM_CFS:
299 /* codec is clock master and frame slave */
f68205a7
PU		 300 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
301 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517ee6cf 302
f68205a7
PU		 303 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
304 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
517ee6cf 305
f68205a7
PU		 306 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
307 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
517ee6cf 308 break;
b67f4487
C		 309 case SND_SOC_DAIFMT_CBM_CFM:
310 /* codec is clock and frame master */
f68205a7
PU		 311 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
312 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 313
f68205a7
PU		 314 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
315 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 316
f68205a7
PU		 317 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
318 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
b67f4487
C		 319 break;
320
321 default:
1d17a04e
PU		 322 ret = -EINVAL;
323 goto out;
b67f4487
C		 324 }
325
326 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
327 case SND_SOC_DAIFMT_IB_NF:
f68205a7
PU		 328 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
329 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
b67f4487 330
f68205a7
PU		 331 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
332 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
b67f4487
C		 333 break;
334
335 case SND_SOC_DAIFMT_NB_IF:
f68205a7
PU		 336 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
337 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
b67f4487 338
f68205a7
PU		 339 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
340 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
b67f4487
C		 341 break;
342
343 case SND_SOC_DAIFMT_IB_IF:
f68205a7
PU		 344 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
345 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
b67f4487 346
f68205a7
PU		 347 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
348 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
b67f4487
C		 349 break;
350
351 case SND_SOC_DAIFMT_NB_NF:
f68205a7
PU		 352 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
353 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
b67f4487 354
f68205a7
PU		 355 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
356 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
b67f4487
C		 357 break;
358
359 default:
1d17a04e
PU		 360 ret = -EINVAL;
361 break;
b67f4487 362 }
1d17a04e
PU		 363out:
364 pm_runtime_put_sync(mcasp->dev);
365 return ret;
b67f4487
C		 366}
367
4ed8c9b7
DM		 368static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
369{
70091a3e 370 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
4ed8c9b7
DM		 371
372 switch (div_id) {
373 case 0: /* MCLK divider */
f68205a7 374 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
4ed8c9b7 375 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
f68205a7 376 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
4ed8c9b7
DM		 377 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
378 break;
379
380 case 1: /* BCLK divider */
f68205a7 381 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
4ed8c9b7 382 ACLKXDIV(div - 1), ACLKXDIV_MASK);
f68205a7 383 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
4ed8c9b7
DM		 384 ACLKRDIV(div - 1), ACLKRDIV_MASK);
385 break;
386
1b3bc060 387 case 2: /* BCLK/LRCLK ratio */
70091a3e 388 mcasp->bclk_lrclk_ratio = div;
1b3bc060
DM		 389 break;
390
4ed8c9b7
DM		 391 default:
392 return -EINVAL;
393 }
394
395 return 0;
396}
397
5b66aa2d
DM		 398static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
399 unsigned int freq, int dir)
400{
70091a3e 401 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
5b66aa2d
DM		 402
403 if (dir == SND_SOC_CLOCK_OUT) {
f68205a7
PU		 404 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
405 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
406 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
5b66aa2d 407 } else {
f68205a7
PU		 408 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
409 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
410 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
5b66aa2d
DM		 411 }
412
413 return 0;
414}
415
70091a3e 416static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
ba764b3d 417 int word_length)
b67f4487 418{
ba764b3d 419 u32 fmt;
79671892
DM		 420 u32 tx_rotate = (word_length / 4) & 0x7;
421 u32 rx_rotate = (32 - word_length) / 4;
ba764b3d 422 u32 mask = (1ULL << word_length) - 1;
b67f4487 423
1b3bc060
DM		 424 /*
425 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
426 * callback, take it into account here. That allows us to for example
427 * send 32 bits per channel to the codec, while only 16 of them carry
428 * audio payload.
d486fea6
MB		 429 * The clock ratio is given for a full period of data (for I2S format
430 * both left and right channels), so it has to be divided by number of
431 * tdm-slots (for I2S - divided by 2).
1b3bc060 432 */
70091a3e
PU		 433 if (mcasp->bclk_lrclk_ratio)
434 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
1b3bc060 435
ba764b3d
DM		 436 /* mapping of the XSSZ bit-field as described in the datasheet */
437 fmt = (word_length >> 1) - 1;
b67f4487 438
70091a3e 439 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
f68205a7
PU		 440 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
441 RXSSZ(0x0F));
442 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
443 TXSSZ(0x0F));
444 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
445 TXROT(7));
446 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
447 RXROT(7));
448 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
f5023af6
YY		 449 }
450
f68205a7 451 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
0c31cf3e 452
b67f4487
C		 453 return 0;
454}
455
662ffae9 456static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
2952b27e 457 int channels)
b67f4487
C		 458{
459 int i;
6a99fb5f
C		 460 u8 tx_ser = 0;
461 u8 rx_ser = 0;
2952b27e 462 u8 ser;
70091a3e 463 u8 slots = mcasp->tdm_slots;
2952b27e 464 u8 max_active_serializers = (channels + slots - 1) / slots;
487dce88 465 u32 reg;
b67f4487 466 /* Default configuration */
453c4990 467 if (mcasp->version != MCASP_VERSION_4)
f68205a7 468 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
b67f4487
C		 469
470 /* All PINS as McASP */
f68205a7 471 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
b67f4487
C		 472
473 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f68205a7
PU		 474 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
475 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487 476 } else {
f68205a7
PU		 477 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
478 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
b67f4487
C		 479 }
480
70091a3e 481 for (i = 0; i < mcasp->num_serializer; i++) {
f68205a7
PU		 482 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
483 mcasp->serial_dir[i]);
70091a3e 484 if (mcasp->serial_dir[i] == TX_MODE &&
2952b27e 485 tx_ser < max_active_serializers) {
f68205a7 486 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
6a99fb5f 487 tx_ser++;
70091a3e 488 } else if (mcasp->serial_dir[i] == RX_MODE &&
2952b27e 489 rx_ser < max_active_serializers) {
f68205a7 490 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
6a99fb5f 491 rx_ser++;
2952b27e 492 } else {
f68205a7
PU		 493 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
494 SRMOD_INACTIVE, SRMOD_MASK);
6a99fb5f
C		 495 }
496 }
497
ecf327c7
DM		 498 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
499 ser = tx_ser;
500 else
501 ser = rx_ser;
502
503 if (ser < max_active_serializers) {
70091a3e 504 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
ecf327c7
DM		 505 "enabled in mcasp (%d)\n", channels, ser * slots);
506 return -EINVAL;
507 }
508
70091a3e
PU		 509 if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
510 if (mcasp->txnumevt * tx_ser > 64)
511 mcasp->txnumevt = 1;
6a99fb5f 512
487dce88 513 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
f68205a7
PU		 514 mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK);
515 mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8),
516 NUMEVT_MASK);
6a99fb5f
C		 517 }
518
70091a3e
PU		 519 if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
520 if (mcasp->rxnumevt * rx_ser > 64)
521 mcasp->rxnumevt = 1;
487dce88
PU		 522
523 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
f68205a7
PU		 524 mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK);
525 mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8),
526 NUMEVT_MASK);
b67f4487 527 }
2952b27e
MB		 528
529 return 0;
b67f4487
C		 530}
531
2c56c4c2 532static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
b67f4487
C		 533{
534 int i, active_slots;
535 u32 mask = 0;
cbc7956c 536 u32 busel = 0;
b67f4487 537
2c56c4c2
PU		 538 if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
539 dev_err(mcasp->dev, "tdm slot %d not supported\n",
540 mcasp->tdm_slots);
541 return -EINVAL;
542 }
543
70091a3e 544 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
b67f4487
C		 545 for (i = 0; i < active_slots; i++)
546 mask |= (1 << i);
547
f68205a7 548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
6a99fb5f 549
cbc7956c
PU		 550 if (!mcasp->dat_port)
551 busel = TXSEL;
552
2c56c4c2
PU		 553 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
554 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
555 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
556 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
557
558 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
559 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
560 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
561 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
562
563 return 0;
b67f4487
C		 564}
565
566/* S/PDIF */
2c56c4c2 567static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
b67f4487 568{
b67f4487
C		 569 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
570 and LSB first */
f68205a7 571 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
b67f4487
C		 572
573 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
f68205a7 574 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
b67f4487
C		 575
576 /* Set the TX tdm : for all the slots */
f68205a7 577 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
b67f4487
C		 578
579 /* Set the TX clock controls : div = 1 and internal */
f68205a7 580 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
b67f4487 581
f68205a7 582 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487
C		 583
584 /* Only 44100 and 48000 are valid, both have the same setting */
f68205a7 585 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
b67f4487
C		 586
587 /* Enable the DIT */
f68205a7 588 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
2c56c4c2
PU		 589
590 return 0;
b67f4487
C		 591}
592
593static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
594 struct snd_pcm_hw_params *params,
595 struct snd_soc_dai *cpu_dai)
596{
70091a3e 597 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487 598 struct davinci_pcm_dma_params *dma_params =
70091a3e 599 &mcasp->dma_params[substream->stream];
453c4990
PU		 600 struct snd_dmaengine_dai_dma_data *dma_data =
601 &mcasp->dma_data[substream->stream];
b67f4487 602 int word_length;
4fa9c1a5 603 u8 fifo_level;
70091a3e 604 u8 slots = mcasp->tdm_slots;
7c21a781 605 u8 active_serializers;
2952b27e 606 int channels;
2c56c4c2 607 int ret;
2952b27e
MB		 608 struct snd_interval *pcm_channels = hw_param_interval(params,
609 SNDRV_PCM_HW_PARAM_CHANNELS);
610 channels = pcm_channels->min;
b67f4487 611
7c21a781
MB		 612 active_serializers = (channels + slots - 1) / slots;
613
662ffae9 614 if (mcasp_common_hw_param(mcasp, substream->stream, channels) == -EINVAL)
2952b27e 615 return -EINVAL;
6a99fb5f 616 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
70091a3e 617 fifo_level = mcasp->txnumevt * active_serializers;
6a99fb5f 618 else
70091a3e 619 fifo_level = mcasp->rxnumevt * active_serializers;
b67f4487 620
70091a3e 621 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
2c56c4c2 622 ret = mcasp_dit_hw_param(mcasp);
b67f4487 623 else
2c56c4c2
PU		 624 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
625
626 if (ret)
627 return ret;
b67f4487
C		 628
629 switch (params_format(params)) {
0a9d1385 630 case SNDRV_PCM_FORMAT_U8:
b67f4487
C		 631 case SNDRV_PCM_FORMAT_S8:
632 dma_params->data_type = 1;
ba764b3d 633 word_length = 8;
b67f4487
C		 634 break;
635
0a9d1385 636 case SNDRV_PCM_FORMAT_U16_LE:
b67f4487
C		 637 case SNDRV_PCM_FORMAT_S16_LE:
638 dma_params->data_type = 2;
ba764b3d 639 word_length = 16;
b67f4487
C		 640 break;
641
21eb24d8
DM		 642 case SNDRV_PCM_FORMAT_U24_3LE:
643 case SNDRV_PCM_FORMAT_S24_3LE:
21eb24d8 644 dma_params->data_type = 3;
ba764b3d 645 word_length = 24;
21eb24d8
DM		 646 break;
647
6b7fa011
DM		 648 case SNDRV_PCM_FORMAT_U24_LE:
649 case SNDRV_PCM_FORMAT_S24_LE:
0a9d1385 650 case SNDRV_PCM_FORMAT_U32_LE:
b67f4487
C		 651 case SNDRV_PCM_FORMAT_S32_LE:
652 dma_params->data_type = 4;
ba764b3d 653 word_length = 32;
b67f4487
C		 654 break;
655
656 default:
657 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
658 return -EINVAL;
659 }
6a99fb5f 660
70091a3e 661 if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
4fa9c1a5
C		 662 dma_params->acnt = 4;
663 else
6a99fb5f
C		 664 dma_params->acnt = dma_params->data_type;
665
4fa9c1a5 666 dma_params->fifo_level = fifo_level;
453c4990
PU		 667 dma_data->maxburst = fifo_level;
668
70091a3e 669 davinci_config_channel_size(mcasp, word_length);
b67f4487
C		 670
671 return 0;
672}
673
674static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
675 int cmd, struct snd_soc_dai *cpu_dai)
676{
70091a3e 677 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 678 int ret = 0;
679
680 switch (cmd) {
b67f4487 681 case SNDRV_PCM_TRIGGER_RESUME:
e473b847
C		 682 case SNDRV_PCM_TRIGGER_START:
683 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
70091a3e 684 davinci_mcasp_start(mcasp, substream->stream);
b67f4487 685 break;
b67f4487 686 case SNDRV_PCM_TRIGGER_SUSPEND:
a47979b5 687 case SNDRV_PCM_TRIGGER_STOP:
b67f4487 688 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
70091a3e 689 davinci_mcasp_stop(mcasp, substream->stream);
b67f4487
C		 690 break;
691
692 default:
693 ret = -EINVAL;
694 }
695
696 return ret;
697}
698
bedad0ca
CPE		 699static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
700 struct snd_soc_dai *dai)
701{
70091a3e 702 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
bedad0ca 703
453c4990
PU		 704 if (mcasp->version == MCASP_VERSION_4)
705 snd_soc_dai_set_dma_data(dai, substream,
706 &mcasp->dma_data[substream->stream]);
707 else
708 snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params);
709
bedad0ca
CPE		 710 return 0;
711}
712
85e7652d 713static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
bedad0ca 714 .startup = davinci_mcasp_startup,
b67f4487
C		 715 .trigger = davinci_mcasp_trigger,
716 .hw_params = davinci_mcasp_hw_params,
717 .set_fmt = davinci_mcasp_set_dai_fmt,
4ed8c9b7 718 .set_clkdiv = davinci_mcasp_set_clkdiv,
5b66aa2d 719 .set_sysclk = davinci_mcasp_set_sysclk,
b67f4487
C		 720};
721
ed29cd5e
PU		 722#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
723
0a9d1385
BG		 724#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
725 SNDRV_PCM_FMTBIT_U8 | \
726 SNDRV_PCM_FMTBIT_S16_LE | \
727 SNDRV_PCM_FMTBIT_U16_LE | \
21eb24d8
DM		 728 SNDRV_PCM_FMTBIT_S24_LE | \
729 SNDRV_PCM_FMTBIT_U24_LE | \
730 SNDRV_PCM_FMTBIT_S24_3LE | \
731 SNDRV_PCM_FMTBIT_U24_3LE | \
0a9d1385
BG		 732 SNDRV_PCM_FMTBIT_S32_LE | \
733 SNDRV_PCM_FMTBIT_U32_LE)
734
f0fba2ad 735static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
b67f4487 736 {
f0fba2ad 737 .name = "davinci-mcasp.0",
b67f4487
C		 738 .playback = {
739 .channels_min = 2,
2952b27e 740 .channels_max = 32 * 16,
b67f4487 741 .rates = DAVINCI_MCASP_RATES,
0a9d1385 742 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 743 },
744 .capture = {
745 .channels_min = 2,
2952b27e 746 .channels_max = 32 * 16,
b67f4487 747 .rates = DAVINCI_MCASP_RATES,
0a9d1385 748 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 749 },
750 .ops = &davinci_mcasp_dai_ops,
751
752 },
753 {
58e48d97 754 .name = "davinci-mcasp.1",
b67f4487
C		 755 .playback = {
756 .channels_min = 1,
757 .channels_max = 384,
758 .rates = DAVINCI_MCASP_RATES,
0a9d1385 759 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 760 },
761 .ops = &davinci_mcasp_dai_ops,
762 },
763
764};
b67f4487 765
eeef0eda
KM		 766static const struct snd_soc_component_driver davinci_mcasp_component = {
767 .name = "davinci-mcasp",
768};
769
256ba181
JS		 770/* Some HW specific values and defaults. The rest is filled in from DT. */
771static struct snd_platform_data dm646x_mcasp_pdata = {
772 .tx_dma_offset = 0x400,
773 .rx_dma_offset = 0x400,
774 .asp_chan_q = EVENTQ_0,
775 .version = MCASP_VERSION_1,
776};
777
778static struct snd_platform_data da830_mcasp_pdata = {
779 .tx_dma_offset = 0x2000,
780 .rx_dma_offset = 0x2000,
781 .asp_chan_q = EVENTQ_0,
782 .version = MCASP_VERSION_2,
783};
784
b14899da 785static struct snd_platform_data am33xx_mcasp_pdata = {
256ba181
JS		 786 .tx_dma_offset = 0,
787 .rx_dma_offset = 0,
788 .asp_chan_q = EVENTQ_0,
789 .version = MCASP_VERSION_3,
790};
791
453c4990
PU		 792static struct snd_platform_data dra7_mcasp_pdata = {
793 .tx_dma_offset = 0x200,
794 .rx_dma_offset = 0x284,
795 .asp_chan_q = EVENTQ_0,
796 .version = MCASP_VERSION_4,
797};
798
3e3b8c34
HG		 799static const struct of_device_id mcasp_dt_ids[] = {
800 {
801 .compatible = "ti,dm646x-mcasp-audio",
256ba181 802 .data = &dm646x_mcasp_pdata,
3e3b8c34
HG		 803 },
804 {
805 .compatible = "ti,da830-mcasp-audio",
256ba181 806 .data = &da830_mcasp_pdata,
3e3b8c34 807 },
e5ec69da 808 {
3af9e031 809 .compatible = "ti,am33xx-mcasp-audio",
b14899da 810 .data = &am33xx_mcasp_pdata,
e5ec69da 811 },
453c4990
PU		 812 {
813 .compatible = "ti,dra7-mcasp-audio",
814 .data = &dra7_mcasp_pdata,
815 },
3e3b8c34
HG		 816 { /* sentinel */ }
817};
818MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
819
ae726e93
PU		 820static int mcasp_reparent_fck(struct platform_device *pdev)
821{
822 struct device_node *node = pdev->dev.of_node;
823 struct clk *gfclk, *parent_clk;
824 const char *parent_name;
825 int ret;
826
827 if (!node)
828 return 0;
829
830 parent_name = of_get_property(node, "fck_parent", NULL);
831 if (!parent_name)
832 return 0;
833
834 gfclk = clk_get(&pdev->dev, "fck");
835 if (IS_ERR(gfclk)) {
836 dev_err(&pdev->dev, "failed to get fck\n");
837 return PTR_ERR(gfclk);
838 }
839
840 parent_clk = clk_get(NULL, parent_name);
841 if (IS_ERR(parent_clk)) {
842 dev_err(&pdev->dev, "failed to get parent clock\n");
843 ret = PTR_ERR(parent_clk);
844 goto err1;
845 }
846
847 ret = clk_set_parent(gfclk, parent_clk);
848 if (ret) {
849 dev_err(&pdev->dev, "failed to reparent fck\n");
850 goto err2;
851 }
852
853err2:
854 clk_put(parent_clk);
855err1:
856 clk_put(gfclk);
857 return ret;
858}
859
3e3b8c34
HG		 860static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
861 struct platform_device *pdev)
862{
863 struct device_node *np = pdev->dev.of_node;
864 struct snd_platform_data *pdata = NULL;
865 const struct of_device_id *match =
ea421eb1 866 of_match_device(mcasp_dt_ids, &pdev->dev);
4023fe6f 867 struct of_phandle_args dma_spec;
3e3b8c34
HG		 868
869 const u32 *of_serial_dir32;
3e3b8c34
HG		 870 u32 val;
871 int i, ret = 0;
872
873 if (pdev->dev.platform_data) {
874 pdata = pdev->dev.platform_data;
875 return pdata;
876 } else if (match) {
256ba181 877 pdata = (struct snd_platform_data *) match->data;
3e3b8c34
HG		 878 } else {
879 /* control shouldn't reach here. something is wrong */
880 ret = -EINVAL;
881 goto nodata;
882 }
883
3e3b8c34
HG		 884 ret = of_property_read_u32(np, "op-mode", &val);
885 if (ret >= 0)
886 pdata->op_mode = val;
887
888 ret = of_property_read_u32(np, "tdm-slots", &val);
2952b27e
MB		 889 if (ret >= 0) {
890 if (val < 2 || val > 32) {
891 dev_err(&pdev->dev,
892 "tdm-slots must be in rage [2-32]\n");
893 ret = -EINVAL;
894 goto nodata;
895 }
896
3e3b8c34 897 pdata->tdm_slots = val;
2952b27e 898 }
3e3b8c34 899
3e3b8c34
HG		 900 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
901 val /= sizeof(u32);
3e3b8c34 902 if (of_serial_dir32) {
1427e660
PU		 903 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
904 (sizeof(*of_serial_dir) * val),
905 GFP_KERNEL);
3e3b8c34
HG		 906 if (!of_serial_dir) {
907 ret = -ENOMEM;
908 goto nodata;
909 }
910
1427e660 911 for (i = 0; i < val; i++)
3e3b8c34
HG		 912 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
913
1427e660 914 pdata->num_serializer = val;
3e3b8c34
HG		 915 pdata->serial_dir = of_serial_dir;
916 }
917
4023fe6f
JS		 918 ret = of_property_match_string(np, "dma-names", "tx");
919 if (ret < 0)
920 goto nodata;
921
922 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
923 &dma_spec);
924 if (ret < 0)
925 goto nodata;
926
927 pdata->tx_dma_channel = dma_spec.args[0];
928
929 ret = of_property_match_string(np, "dma-names", "rx");
930 if (ret < 0)
931 goto nodata;
932
933 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
934 &dma_spec);
935 if (ret < 0)
936 goto nodata;
937
938 pdata->rx_dma_channel = dma_spec.args[0];
939
3e3b8c34
HG		 940 ret = of_property_read_u32(np, "tx-num-evt", &val);
941 if (ret >= 0)
942 pdata->txnumevt = val;
943
944 ret = of_property_read_u32(np, "rx-num-evt", &val);
945 if (ret >= 0)
946 pdata->rxnumevt = val;
947
948 ret = of_property_read_u32(np, "sram-size-playback", &val);
949 if (ret >= 0)
950 pdata->sram_size_playback = val;
951
952 ret = of_property_read_u32(np, "sram-size-capture", &val);
953 if (ret >= 0)
954 pdata->sram_size_capture = val;
955
956 return pdata;
957
958nodata:
959 if (ret < 0) {
960 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
961 ret);
962 pdata = NULL;
963 }
964 return pdata;
965}
966
b67f4487
C		 967static int davinci_mcasp_probe(struct platform_device *pdev)
968{
969 struct davinci_pcm_dma_params *dma_data;
256ba181 970 struct resource *mem, *ioarea, *res, *dat;
b67f4487 971 struct snd_platform_data *pdata;
70091a3e 972 struct davinci_mcasp *mcasp;
96d31e2b 973 int ret;
b67f4487 974
3e3b8c34
HG		 975 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
976 dev_err(&pdev->dev, "No platform data supplied\n");
977 return -EINVAL;
978 }
979
70091a3e 980 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
96d31e2b 981 GFP_KERNEL);
70091a3e 982 if (!mcasp)
b67f4487
C		 983 return -ENOMEM;
984
3e3b8c34
HG		 985 pdata = davinci_mcasp_set_pdata_from_of(pdev);
986 if (!pdata) {
987 dev_err(&pdev->dev, "no platform data\n");
988 return -EINVAL;
989 }
990
256ba181 991 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
b67f4487 992 if (!mem) {
70091a3e 993 dev_warn(mcasp->dev,
256ba181
JS		 994 "\"mpu\" mem resource not found, using index 0\n");
995 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
996 if (!mem) {
997 dev_err(&pdev->dev, "no mem resource?\n");
998 return -ENODEV;
999 }
b67f4487
C		 1000 }
1001
96d31e2b 1002 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
d852f446 1003 resource_size(mem), pdev->name);
b67f4487
C		 1004 if (!ioarea) {
1005 dev_err(&pdev->dev, "Audio region already claimed\n");
96d31e2b 1006 return -EBUSY;
b67f4487
C		 1007 }
1008
10884347 1009 pm_runtime_enable(&pdev->dev);
b67f4487 1010
10884347
HG		 1011 ret = pm_runtime_get_sync(&pdev->dev);
1012 if (IS_ERR_VALUE(ret)) {
1013 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1014 return ret;
1015 }
b67f4487 1016
70091a3e
PU		 1017 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1018 if (!mcasp->base) {
4f82f028
VB		 1019 dev_err(&pdev->dev, "ioremap failed\n");
1020 ret = -ENOMEM;
1021 goto err_release_clk;
1022 }
1023
70091a3e
PU		 1024 mcasp->op_mode = pdata->op_mode;
1025 mcasp->tdm_slots = pdata->tdm_slots;
1026 mcasp->num_serializer = pdata->num_serializer;
1027 mcasp->serial_dir = pdata->serial_dir;
1028 mcasp->version = pdata->version;
1029 mcasp->txnumevt = pdata->txnumevt;
1030 mcasp->rxnumevt = pdata->rxnumevt;
487dce88 1031
70091a3e 1032 mcasp->dev = &pdev->dev;
b67f4487 1033
256ba181 1034 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
cbc7956c
PU		 1035 if (dat)
1036 mcasp->dat_port = true;
256ba181 1037
70091a3e 1038 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
48519f0a
SN		 1039 dma_data->asp_chan_q = pdata->asp_chan_q;
1040 dma_data->ram_chan_q = pdata->ram_chan_q;
b8ec56d8 1041 dma_data->sram_pool = pdata->sram_pool;
a0c83263 1042 dma_data->sram_size = pdata->sram_size_playback;
cbc7956c
PU		 1043 if (dat)
1044 dma_data->dma_addr = dat->start;
1045 else
1046 dma_data->dma_addr = mem->start + pdata->tx_dma_offset;
b67f4487 1047
453c4990
PU		 1048 /* Unconditional dmaengine stuff */
1049 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = dma_data->dma_addr;
1050
b67f4487 1051 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
4023fe6f
JS		 1052 if (res)
1053 dma_data->channel = res->start;
1054 else
1055 dma_data->channel = pdata->tx_dma_channel;
92e2a6f6 1056
70091a3e 1057 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
48519f0a
SN		 1058 dma_data->asp_chan_q = pdata->asp_chan_q;
1059 dma_data->ram_chan_q = pdata->ram_chan_q;
b8ec56d8 1060 dma_data->sram_pool = pdata->sram_pool;
a0c83263 1061 dma_data->sram_size = pdata->sram_size_capture;
cbc7956c
PU		 1062 if (dat)
1063 dma_data->dma_addr = dat->start;
1064 else
1065 dma_data->dma_addr = mem->start + pdata->rx_dma_offset;
1066
453c4990
PU		 1067 /* Unconditional dmaengine stuff */
1068 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = dma_data->dma_addr;
1069
cbc7956c
PU		 1070 if (mcasp->version < MCASP_VERSION_3) {
1071 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1072 /* dma_data->dma_addr is pointing to the data port address */
1073 mcasp->dat_port = true;
1074 } else {
1075 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1076 }
b67f4487
C		 1077
1078 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
4023fe6f
JS		 1079 if (res)
1080 dma_data->channel = res->start;
1081 else
1082 dma_data->channel = pdata->rx_dma_channel;
b67f4487 1083
453c4990
PU		 1084 /* Unconditional dmaengine stuff */
1085 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = "tx";
1086 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = "rx";
1087
70091a3e 1088 dev_set_drvdata(&pdev->dev, mcasp);
ae726e93
PU		 1089
1090 mcasp_reparent_fck(pdev);
1091
eeef0eda
KM		 1092 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1093 &davinci_mcasp_dai[pdata->op_mode], 1);
b67f4487
C		 1094
1095 if (ret != 0)
96d31e2b 1096 goto err_release_clk;
f08095a4 1097
453c4990
PU		 1098 if (mcasp->version != MCASP_VERSION_4) {
1099 ret = davinci_soc_platform_register(&pdev->dev);
1100 if (ret) {
1101 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1102 goto err_unregister_component;
1103 }
f08095a4
HG		 1104 }
1105
b67f4487
C		 1106 return 0;
1107
eeef0eda
KM		 1108err_unregister_component:
1109 snd_soc_unregister_component(&pdev->dev);
eef6d7b8 1110err_release_clk:
10884347
HG		 1111 pm_runtime_put_sync(&pdev->dev);
1112 pm_runtime_disable(&pdev->dev);
b67f4487
C		 1113 return ret;
1114}
1115
1116static int davinci_mcasp_remove(struct platform_device *pdev)
1117{
453c4990 1118 struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
b67f4487 1119
eeef0eda 1120 snd_soc_unregister_component(&pdev->dev);
453c4990
PU		 1121 if (mcasp->version != MCASP_VERSION_4)
1122 davinci_soc_platform_unregister(&pdev->dev);
10884347
HG		 1123
1124 pm_runtime_put_sync(&pdev->dev);
1125 pm_runtime_disable(&pdev->dev);
b67f4487 1126
b67f4487
C		 1127 return 0;
1128}
1129
a85e419e
DM		 1130#ifdef CONFIG_PM_SLEEP
1131static int davinci_mcasp_suspend(struct device *dev)
1132{
70091a3e 1133 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
a85e419e 1134
f68205a7
PU		 1135 mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
1136 mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
1137 mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
1138 mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
1139 mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
1140 mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
1141 mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
a85e419e
DM		 1142
1143 return 0;
1144}
1145
1146static int davinci_mcasp_resume(struct device *dev)
1147{
70091a3e 1148 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
f68205a7
PU		 1149
1150 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
1151 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
1152 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
1153 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
1154 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
1155 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
1156 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
a85e419e
DM		 1157
1158 return 0;
1159}
1160#endif
1161
1162SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
1163 davinci_mcasp_suspend,
1164 davinci_mcasp_resume);
1165
b67f4487
C		 1166static struct platform_driver davinci_mcasp_driver = {
1167 .probe = davinci_mcasp_probe,
1168 .remove = davinci_mcasp_remove,
1169 .driver = {
1170 .name = "davinci-mcasp",
1171 .owner = THIS_MODULE,
a85e419e 1172 .pm = &davinci_mcasp_pm_ops,
ea421eb1 1173 .of_match_table = mcasp_dt_ids,
b67f4487
C		 1174 },
1175};
1176
f9b8a514 1177module_platform_driver(davinci_mcasp_driver);
b67f4487
C		 1178
1179MODULE_AUTHOR("Steve Chen");
1180MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1181MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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