[deliverable/linux.git] / sound / soc / dwc / designware_i2s.c

/*
 * ALSA SoC Synopsys I2S Audio Layer
 *
 * sound/soc/dwc/designware_i2s.c
 *
 * Copyright (C) 2010 ST Microelectronics
 * Rajeev Kumar <rajeevkumar.linux@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <sound/designware_i2s.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

/* common register for all channel */
#define IER		0x000
#define IRER		0x004
#define ITER		0x008
#define CER		0x00C
#define CCR		0x010
#define RXFFR		0x014
#define TXFFR		0x018

/* I2STxRxRegisters for all channels */
#define LRBR_LTHR(x)	(0x40 * x + 0x020)
#define RRBR_RTHR(x)	(0x40 * x + 0x024)
#define RER(x)		(0x40 * x + 0x028)
#define TER(x)		(0x40 * x + 0x02C)
#define RCR(x)		(0x40 * x + 0x030)
#define TCR(x)		(0x40 * x + 0x034)
#define ISR(x)		(0x40 * x + 0x038)
#define IMR(x)		(0x40 * x + 0x03C)
#define ROR(x)		(0x40 * x + 0x040)
#define TOR(x)		(0x40 * x + 0x044)
#define RFCR(x)		(0x40 * x + 0x048)
#define TFCR(x)		(0x40 * x + 0x04C)
#define RFF(x)		(0x40 * x + 0x050)
#define TFF(x)		(0x40 * x + 0x054)

/* I2SCOMPRegisters */
#define I2S_COMP_PARAM_2	0x01F0
#define I2S_COMP_PARAM_1	0x01F4
#define I2S_COMP_VERSION	0x01F8
#define I2S_COMP_TYPE		0x01FC

#define MAX_CHANNEL_NUM		8
#define MIN_CHANNEL_NUM		2

struct dw_i2s_dev {
	void __iomem *i2s_base;
	struct clk *clk;
	int active;
	unsigned int capability;
	struct device *dev;

	/* data related to DMA transfers b/w i2s and DMAC */
	struct i2s_dma_data play_dma_data;
	struct i2s_dma_data capture_dma_data;
	struct i2s_clk_config_data config;
	int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
};

static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
{
	writel(val, io_base + reg);
}

static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
{
	return readl(io_base + reg);
}

static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
{
	u32 i = 0;

	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		for (i = 0; i < 4; i++)
			i2s_write_reg(dev->i2s_base, TER(i), 0);
	} else {
		for (i = 0; i < 4; i++)
			i2s_write_reg(dev->i2s_base, RER(i), 0);
	}
}

static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
{
	u32 i = 0;

	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		for (i = 0; i < 4; i++)
			i2s_write_reg(dev->i2s_base, TOR(i), 0);
	} else {
		for (i = 0; i < 4; i++)
			i2s_write_reg(dev->i2s_base, ROR(i), 0);
	}
}

static void i2s_start(struct dw_i2s_dev *dev,
		      struct snd_pcm_substream *substream)
{

	i2s_write_reg(dev->i2s_base, IER, 1);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		i2s_write_reg(dev->i2s_base, ITER, 1);
	else
		i2s_write_reg(dev->i2s_base, IRER, 1);

	i2s_write_reg(dev->i2s_base, CER, 1);
}

static void i2s_stop(struct dw_i2s_dev *dev,
		struct snd_pcm_substream *substream)
{
	u32 i = 0, irq;

	i2s_clear_irqs(dev, substream->stream);
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		i2s_write_reg(dev->i2s_base, ITER, 0);

		for (i = 0; i < 4; i++) {
			irq = i2s_read_reg(dev->i2s_base, IMR(i));
			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
		}
	} else {
		i2s_write_reg(dev->i2s_base, IRER, 0);

		for (i = 0; i < 4; i++) {
			irq = i2s_read_reg(dev->i2s_base, IMR(i));
			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
		}
	}

	if (!dev->active) {
		i2s_write_reg(dev->i2s_base, CER, 0);
		i2s_write_reg(dev->i2s_base, IER, 0);
	}
}

static int dw_i2s_startup(struct snd_pcm_substream *substream,
		struct snd_soc_dai *cpu_dai)
{
	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
	struct i2s_dma_data *dma_data = NULL;

	if (!(dev->capability & DWC_I2S_RECORD) &&
			(substream->stream == SNDRV_PCM_STREAM_CAPTURE))
		return -EINVAL;

	if (!(dev->capability & DWC_I2S_PLAY) &&
			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
		return -EINVAL;

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dma_data = &dev->play_dma_data;
	else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		dma_data = &dev->capture_dma_data;

	snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);

	return 0;
}

static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	struct i2s_clk_config_data *config = &dev->config;
	u32 ccr, xfer_resolution, ch_reg, irq;
	int ret;

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		config->data_width = 16;
		ccr = 0x00;
		xfer_resolution = 0x02;
		break;

	case SNDRV_PCM_FORMAT_S24_LE:
		config->data_width = 24;
		ccr = 0x08;
		xfer_resolution = 0x04;
		break;

	case SNDRV_PCM_FORMAT_S32_LE:
		config->data_width = 32;
		ccr = 0x10;
		xfer_resolution = 0x05;
		break;

	default:
		dev_err(dev->dev, "designware-i2s: unsuppted PCM fmt");
		return -EINVAL;
	}

	config->chan_nr = params_channels(params);

	switch (config->chan_nr) {
	case EIGHT_CHANNEL_SUPPORT:
		ch_reg = 3;
		break;
	case SIX_CHANNEL_SUPPORT:
		ch_reg = 2;
		break;
	case FOUR_CHANNEL_SUPPORT:
		ch_reg = 1;
		break;
	case TWO_CHANNEL_SUPPORT:
		ch_reg = 0;
		break;
	default:
		dev_err(dev->dev, "channel not supported\n");
		return -EINVAL;
	}

	i2s_disable_channels(dev, substream->stream);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution);
		i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
		irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
		i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
		i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
	} else {
		i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution);
		i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
		irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
		i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
		i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
	}

	i2s_write_reg(dev->i2s_base, CCR, ccr);

	config->sample_rate = params_rate(params);

	if (!dev->i2s_clk_cfg)
		return -EINVAL;

	ret = dev->i2s_clk_cfg(config);
	if (ret < 0) {
		dev_err(dev->dev, "runtime audio clk config fail\n");
		return ret;
	}

	return 0;
}

static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
{
	snd_soc_dai_set_dma_data(dai, substream, NULL);
}

static int dw_i2s_prepare(struct snd_pcm_substream *substream,
			  struct snd_soc_dai *dai)
{
	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		i2s_write_reg(dev->i2s_base, TXFFR, 1);
	else
		i2s_write_reg(dev->i2s_base, RXFFR, 1);

	return 0;
}

static int dw_i2s_trigger(struct snd_pcm_substream *substream,
		int cmd, struct snd_soc_dai *dai)
{
	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		dev->active++;
		i2s_start(dev, substream);
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		dev->active--;
		i2s_stop(dev, substream);
		break;
	default:
		ret = -EINVAL;
		break;
	}
	return ret;
}

static struct snd_soc_dai_ops dw_i2s_dai_ops = {
	.startup	= dw_i2s_startup,
	.shutdown	= dw_i2s_shutdown,
	.hw_params	= dw_i2s_hw_params,
	.prepare	= dw_i2s_prepare,
	.trigger	= dw_i2s_trigger,
};

static const struct snd_soc_component_driver dw_i2s_component = {
	.name		= "dw-i2s",
};

#ifdef CONFIG_PM

static int dw_i2s_suspend(struct snd_soc_dai *dai)
{
	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);

	clk_disable(dev->clk);
	return 0;
}

static int dw_i2s_resume(struct snd_soc_dai *dai)
{
	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);

	clk_enable(dev->clk);
	return 0;
}

#else
#define dw_i2s_suspend	NULL
#define dw_i2s_resume	NULL
#endif

static int dw_i2s_probe(struct platform_device *pdev)
{
	const struct i2s_platform_data *pdata = pdev->dev.platform_data;
	struct dw_i2s_dev *dev;
	struct resource *res;
	int ret;
	unsigned int cap;
	struct snd_soc_dai_driver *dw_i2s_dai;

	if (!pdata) {
		dev_err(&pdev->dev, "Invalid platform data\n");
		return -EINVAL;
	}

	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
	if (!dev) {
		dev_warn(&pdev->dev, "kzalloc fail\n");
		return -ENOMEM;
	}

	dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
	if (!dw_i2s_dai) {
		dev_err(&pdev->dev, "mem allocation failed for dai driver\n");
		return -ENOMEM;
	}

	dw_i2s_dai->ops = &dw_i2s_dai_ops;
	dw_i2s_dai->suspend = dw_i2s_suspend;
	dw_i2s_dai->resume = dw_i2s_resume;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "no i2s resource defined\n");
		return -ENODEV;
	}

	dev->i2s_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(dev->i2s_base)) {
		dev_err(&pdev->dev, "ioremap fail for i2s_region\n");
		return PTR_ERR(dev->i2s_base);
	}

	cap = pdata->cap;
	dev->capability = cap;
	dev->i2s_clk_cfg = pdata->i2s_clk_cfg;

	/* Set DMA slaves info */

	dev->play_dma_data.data = pdata->play_dma_data;
	dev->capture_dma_data.data = pdata->capture_dma_data;
	dev->play_dma_data.addr = res->start + I2S_TXDMA;
	dev->capture_dma_data.addr = res->start + I2S_RXDMA;
	dev->play_dma_data.max_burst = 16;
	dev->capture_dma_data.max_burst = 16;
	dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	dev->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	dev->play_dma_data.filter = pdata->filter;
	dev->capture_dma_data.filter = pdata->filter;

	dev->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(dev->clk))
		return  PTR_ERR(dev->clk);

	ret = clk_enable(dev->clk);
	if (ret < 0)
		goto err_clk_put;

	if (cap & DWC_I2S_PLAY) {
		dev_dbg(&pdev->dev, " designware: play supported\n");
		dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
		dw_i2s_dai->playback.channels_max = pdata->channel;
		dw_i2s_dai->playback.formats = pdata->snd_fmts;
		dw_i2s_dai->playback.rates = pdata->snd_rates;
	}

	if (cap & DWC_I2S_RECORD) {
		dev_dbg(&pdev->dev, "designware: record supported\n");
		dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
		dw_i2s_dai->capture.channels_max = pdata->channel;
		dw_i2s_dai->capture.formats = pdata->snd_fmts;
		dw_i2s_dai->capture.rates = pdata->snd_rates;
	}

	dev->dev = &pdev->dev;
	dev_set_drvdata(&pdev->dev, dev);
	ret = snd_soc_register_component(&pdev->dev, &dw_i2s_component,
					 dw_i2s_dai, 1);
	if (ret != 0) {
		dev_err(&pdev->dev, "not able to register dai\n");
		goto err_clk_disable;
	}

	return 0;

err_clk_disable:
	clk_disable(dev->clk);
err_clk_put:
	clk_put(dev->clk);
	return ret;
}

static int dw_i2s_remove(struct platform_device *pdev)
{
	struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);

	snd_soc_unregister_component(&pdev->dev);

	clk_put(dev->clk);

	return 0;
}

static struct platform_driver dw_i2s_driver = {
	.probe		= dw_i2s_probe,
	.remove		= dw_i2s_remove,
	.driver		= {
		.name	= "designware-i2s",
	},
};

module_platform_driver(dw_i2s_driver);

MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:designware_i2s");
Commit	Line	Data
3a9cf8ef RK	1	/*
	2	* ALSA SoC Synopsys I2S Audio Layer
	3	*
22a4adf2	4	* sound/soc/dwc/designware_i2s.c
3a9cf8ef RK	5	*
3a9cf8ef RK	6	* Copyright (C) 2010 ST Microelectronics
9a302c32	7	* Rajeev Kumar <rajeevkumar.linux@gmail.com>
3a9cf8ef RK	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include <linux/clk.h>
	15	#include <linux/device.h>
	16	#include <linux/init.h>
	17	#include <linux/io.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/module.h>
	20	#include <linux/slab.h>
	21	#include <sound/designware_i2s.h>
	22	#include <sound/pcm.h>
	23	#include <sound/pcm_params.h>
	24	#include <sound/soc.h>
	25
	26	/* common register for all channel */
	27	#define IER 0x000
	28	#define IRER 0x004
	29	#define ITER 0x008
	30	#define CER 0x00C
	31	#define CCR 0x010
	32	#define RXFFR 0x014
	33	#define TXFFR 0x018
	34
	35	/* I2STxRxRegisters for all channels */
	36	#define LRBR_LTHR(x) (0x40 * x + 0x020)
	37	#define RRBR_RTHR(x) (0x40 * x + 0x024)
	38	#define RER(x) (0x40 * x + 0x028)
	39	#define TER(x) (0x40 * x + 0x02C)
	40	#define RCR(x) (0x40 * x + 0x030)
	41	#define TCR(x) (0x40 * x + 0x034)
	42	#define ISR(x) (0x40 * x + 0x038)
	43	#define IMR(x) (0x40 * x + 0x03C)
	44	#define ROR(x) (0x40 * x + 0x040)
	45	#define TOR(x) (0x40 * x + 0x044)
	46	#define RFCR(x) (0x40 * x + 0x048)
	47	#define TFCR(x) (0x40 * x + 0x04C)
	48	#define RFF(x) (0x40 * x + 0x050)
	49	#define TFF(x) (0x40 * x + 0x054)
	50
	51	/* I2SCOMPRegisters */
	52	#define I2S_COMP_PARAM_2 0x01F0
	53	#define I2S_COMP_PARAM_1 0x01F4
	54	#define I2S_COMP_VERSION 0x01F8
	55	#define I2S_COMP_TYPE 0x01FC
	56
	57	#define MAX_CHANNEL_NUM 8
	58	#define MIN_CHANNEL_NUM 2
	59
	60	struct dw_i2s_dev {
	61	void __iomem *i2s_base;
	62	struct clk *clk;
	63	int active;
	64	unsigned int capability;
	65	struct device *dev;
	66
	67	/* data related to DMA transfers b/w i2s and DMAC */
	68	struct i2s_dma_data play_dma_data;
	69	struct i2s_dma_data capture_dma_data;
	70	struct i2s_clk_config_data config;
	71	int (i2s_clk_cfg)(struct i2s_clk_config_data config);
72	};
73
6b4a21b6	74	static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
3a9cf8ef RK	75	{
	76	writel(val, io_base + reg);
	77	}
	78
6b4a21b6	79	static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
3a9cf8ef RK	80	{
	81	return readl(io_base + reg);
	82	}
	83
	84	static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
	85	{
	86	u32 i = 0;
	87
	88	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	89	for (i = 0; i < 4; i++)
	90	i2s_write_reg(dev->i2s_base, TER(i), 0);
	91	} else {
	92	for (i = 0; i < 4; i++)
	93	i2s_write_reg(dev->i2s_base, RER(i), 0);
	94	}
	95	}
	96
	97	static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
	98	{
	99	u32 i = 0;
	100
	101	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	102	for (i = 0; i < 4; i++)
	103	i2s_write_reg(dev->i2s_base, TOR(i), 0);
	104	} else {
	105	for (i = 0; i < 4; i++)
	106	i2s_write_reg(dev->i2s_base, ROR(i), 0);
	107	}
	108	}
	109
1520ffd2 MB	110	static void i2s_start(struct dw_i2s_dev *dev,
1520ffd2 MB	111	struct snd_pcm_substream *substream)
3a9cf8ef RK	112	{
	113
	114	i2s_write_reg(dev->i2s_base, IER, 1);
	115
	116	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	117	i2s_write_reg(dev->i2s_base, ITER, 1);
	118	else
	119	i2s_write_reg(dev->i2s_base, IRER, 1);
	120
	121	i2s_write_reg(dev->i2s_base, CER, 1);
	122	}
	123
	124	static void i2s_stop(struct dw_i2s_dev *dev,
	125	struct snd_pcm_substream *substream)
	126	{
	127	u32 i = 0, irq;
	128
	129	i2s_clear_irqs(dev, substream->stream);
	130	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	131	i2s_write_reg(dev->i2s_base, ITER, 0);
	132
	133	for (i = 0; i < 4; i++) {
	134	irq = i2s_read_reg(dev->i2s_base, IMR(i));
	135	i2s_write_reg(dev->i2s_base, IMR(i), irq \| 0x30);
	136	}
	137	} else {
	138	i2s_write_reg(dev->i2s_base, IRER, 0);
	139
	140	for (i = 0; i < 4; i++) {
	141	irq = i2s_read_reg(dev->i2s_base, IMR(i));
	142	i2s_write_reg(dev->i2s_base, IMR(i), irq \| 0x03);
	143	}
	144	}
	145
	146	if (!dev->active) {
	147	i2s_write_reg(dev->i2s_base, CER, 0);
	148	i2s_write_reg(dev->i2s_base, IER, 0);
	149	}
	150	}
	151
	152	static int dw_i2s_startup(struct snd_pcm_substream *substream,
	153	struct snd_soc_dai *cpu_dai)
	154	{
	155	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
	156	struct i2s_dma_data *dma_data = NULL;
	157
	158	if (!(dev->capability & DWC_I2S_RECORD) &&
	159	(substream->stream == SNDRV_PCM_STREAM_CAPTURE))
	160	return -EINVAL;
	161
	162	if (!(dev->capability & DWC_I2S_PLAY) &&
	163	(substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
	164	return -EINVAL;
	165
	166	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	167	dma_data = &dev->play_dma_data;
	168	else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	169	dma_data = &dev->capture_dma_data;
	170
	171	snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
	172
	173	return 0;
	174	}
	175
176	static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
177	struct snd_pcm_hw_params params, struct snd_soc_dai dai)
178	{
179	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
180	struct i2s_clk_config_data *config = &dev->config;
181	u32 ccr, xfer_resolution, ch_reg, irq;
182	int ret;
183
184	switch (params_format(params)) {
185	case SNDRV_PCM_FORMAT_S16_LE:
186	config->data_width = 16;
187	ccr = 0x00;
188	xfer_resolution = 0x02;
189	break;
190
191	case SNDRV_PCM_FORMAT_S24_LE:
192	config->data_width = 24;
193	ccr = 0x08;
194	xfer_resolution = 0x04;
195	break;
196
197	case SNDRV_PCM_FORMAT_S32_LE:
198	config->data_width = 32;
199	ccr = 0x10;
200	xfer_resolution = 0x05;
201	break;
202
203	default:
204	dev_err(dev->dev, "designware-i2s: unsuppted PCM fmt");
205	return -EINVAL;
206	}
207
208	config->chan_nr = params_channels(params);
209
210	switch (config->chan_nr) {
211	case EIGHT_CHANNEL_SUPPORT:
212	ch_reg = 3;
0099d24c	213	break;
3a9cf8ef RK	214	case SIX_CHANNEL_SUPPORT:
3a9cf8ef RK	215	ch_reg = 2;
0099d24c	216	break;
3a9cf8ef RK	217	case FOUR_CHANNEL_SUPPORT:
3a9cf8ef RK	218	ch_reg = 1;
0099d24c	219	break;
3a9cf8ef RK	220	case TWO_CHANNEL_SUPPORT:
	221	ch_reg = 0;
	222	break;
	223	default:
	224	dev_err(dev->dev, "channel not supported\n");
0099d24c	225	return -EINVAL;
3a9cf8ef RK	226	}
	227
	228	i2s_disable_channels(dev, substream->stream);
	229
	230	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	231	i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution);
	232	i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
	233	irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
	234	i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
	235	i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
	236	} else {
	237	i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution);
	238	i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
	239	irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
	240	i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
	241	i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
	242	}
	243
	244	i2s_write_reg(dev->i2s_base, CCR, ccr);
	245
	246	config->sample_rate = params_rate(params);
	247
	248	if (!dev->i2s_clk_cfg)
	249	return -EINVAL;
	250
	251	ret = dev->i2s_clk_cfg(config);
	252	if (ret < 0) {
	253	dev_err(dev->dev, "runtime audio clk config fail\n");
	254	return ret;
	255	}
	256
	257	return 0;
	258	}
	259
	260	static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
	261	struct snd_soc_dai *dai)
	262	{
	263	snd_soc_dai_set_dma_data(dai, substream, NULL);
	264	}
	265
3475c3d0 AJ	266	static int dw_i2s_prepare(struct snd_pcm_substream *substream,
	267	struct snd_soc_dai *dai)
	268	{
	269	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	270
	271	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	272	i2s_write_reg(dev->i2s_base, TXFFR, 1);
	273	else
	274	i2s_write_reg(dev->i2s_base, RXFFR, 1);
	275
	276	return 0;
	277	}
	278
3a9cf8ef RK	279	static int dw_i2s_trigger(struct snd_pcm_substream *substream,
	280	int cmd, struct snd_soc_dai *dai)
	281	{
	282	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	283	int ret = 0;
	284
	285	switch (cmd) {
	286	case SNDRV_PCM_TRIGGER_START:
	287	case SNDRV_PCM_TRIGGER_RESUME:
	288	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	289	dev->active++;
	290	i2s_start(dev, substream);
	291	break;
	292
	293	case SNDRV_PCM_TRIGGER_STOP:
	294	case SNDRV_PCM_TRIGGER_SUSPEND:
	295	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	296	dev->active--;
	297	i2s_stop(dev, substream);
	298	break;
	299	default:
	300	ret = -EINVAL;
	301	break;
	302	}
	303	return ret;
	304	}
	305
	306	static struct snd_soc_dai_ops dw_i2s_dai_ops = {
	307	.startup = dw_i2s_startup,
	308	.shutdown = dw_i2s_shutdown,
	309	.hw_params = dw_i2s_hw_params,
3475c3d0	310	.prepare = dw_i2s_prepare,
3a9cf8ef RK	311	.trigger = dw_i2s_trigger,
	312	};
	313
92eaa328 KM	314	static const struct snd_soc_component_driver dw_i2s_component = {
	315	.name = "dw-i2s",
	316	};
	317
3a9cf8ef RK	318	#ifdef CONFIG_PM
	319
	320	static int dw_i2s_suspend(struct snd_soc_dai *dai)
	321	{
	322	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	323
	324	clk_disable(dev->clk);
	325	return 0;
	326	}
	327
	328	static int dw_i2s_resume(struct snd_soc_dai *dai)
	329	{
	330	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	331
	332	clk_enable(dev->clk);
	333	return 0;
	334	}
	335
	336	#else
	337	#define dw_i2s_suspend NULL
	338	#define dw_i2s_resume NULL
	339	#endif
	340
	341	static int dw_i2s_probe(struct platform_device *pdev)
	342	{
	343	const struct i2s_platform_data *pdata = pdev->dev.platform_data;
	344	struct dw_i2s_dev *dev;
	345	struct resource *res;
	346	int ret;
	347	unsigned int cap;
	348	struct snd_soc_dai_driver *dw_i2s_dai;
	349
	350	if (!pdata) {
	351	dev_err(&pdev->dev, "Invalid platform data\n");
	352	return -EINVAL;
	353	}
	354
3a9cf8ef RK	355	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
	356	if (!dev) {
	357	dev_warn(&pdev->dev, "kzalloc fail\n");
	358	return -ENOMEM;
	359	}
	360
b163be4c AJ	361	dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
	362	if (!dw_i2s_dai) {
	363	dev_err(&pdev->dev, "mem allocation failed for dai driver\n");
3a9cf8ef RK	364	return -ENOMEM;
	365	}
	366
b163be4c AJ	367	dw_i2s_dai->ops = &dw_i2s_dai_ops;
	368	dw_i2s_dai->suspend = dw_i2s_suspend;
	369	dw_i2s_dai->resume = dw_i2s_resume;
	370
	371	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	372	if (!res) {
	373	dev_err(&pdev->dev, "no i2s resource defined\n");
	374	return -ENODEV;
	375	}
	376
	377	dev->i2s_base = devm_ioremap_resource(&pdev->dev, res);
	378	if (IS_ERR(dev->i2s_base)) {
	379	dev_err(&pdev->dev, "ioremap fail for i2s_region\n");
	380	return PTR_ERR(dev->i2s_base);
	381	}
	382
3a9cf8ef RK	383	cap = pdata->cap;
	384	dev->capability = cap;
	385	dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
	386
	387	/* Set DMA slaves info */
	388
	389	dev->play_dma_data.data = pdata->play_dma_data;
	390	dev->capture_dma_data.data = pdata->capture_dma_data;
	391	dev->play_dma_data.addr = res->start + I2S_TXDMA;
	392	dev->capture_dma_data.addr = res->start + I2S_RXDMA;
	393	dev->play_dma_data.max_burst = 16;
	394	dev->capture_dma_data.max_burst = 16;
	395	dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	396	dev->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	397	dev->play_dma_data.filter = pdata->filter;
	398	dev->capture_dma_data.filter = pdata->filter;
	399
	400	dev->clk = clk_get(&pdev->dev, NULL);
	401	if (IS_ERR(dev->clk))
	402	return PTR_ERR(dev->clk);
	403
	404	ret = clk_enable(dev->clk);
	405	if (ret < 0)
	406	goto err_clk_put;
	407
3a9cf8ef	408	if (cap & DWC_I2S_PLAY) {
5e83c160	409	dev_dbg(&pdev->dev, " designware: play supported\n");
3a9cf8ef RK	410	dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
	411	dw_i2s_dai->playback.channels_max = pdata->channel;
	412	dw_i2s_dai->playback.formats = pdata->snd_fmts;
	413	dw_i2s_dai->playback.rates = pdata->snd_rates;
	414	}
	415
	416	if (cap & DWC_I2S_RECORD) {
5e83c160	417	dev_dbg(&pdev->dev, "designware: record supported\n");
3a9cf8ef RK	418	dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
	419	dw_i2s_dai->capture.channels_max = pdata->channel;
	420	dw_i2s_dai->capture.formats = pdata->snd_fmts;
	421	dw_i2s_dai->capture.rates = pdata->snd_rates;
	422	}
	423
3a9cf8ef RK	424	dev->dev = &pdev->dev;
3a9cf8ef RK	425	dev_set_drvdata(&pdev->dev, dev);
92eaa328 KM	426	ret = snd_soc_register_component(&pdev->dev, &dw_i2s_component,
92eaa328 KM	427	dw_i2s_dai, 1);
3a9cf8ef RK	428	if (ret != 0) {
3a9cf8ef RK	429	dev_err(&pdev->dev, "not able to register dai\n");
e925a6b1	430	goto err_clk_disable;
3a9cf8ef RK	431	}
	432
	433	return 0;
	434
3a9cf8ef RK	435	err_clk_disable:
	436	clk_disable(dev->clk);
	437	err_clk_put:
	438	clk_put(dev->clk);
	439	return ret;
	440	}
	441
	442	static int dw_i2s_remove(struct platform_device *pdev)
	443	{
	444	struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
	445
92eaa328	446	snd_soc_unregister_component(&pdev->dev);
3a9cf8ef RK	447
	448	clk_put(dev->clk);
	449
	450	return 0;
	451	}
	452
	453	static struct platform_driver dw_i2s_driver = {
	454	.probe = dw_i2s_probe,
	455	.remove = dw_i2s_remove,
	456	.driver = {
	457	.name = "designware-i2s",
3a9cf8ef RK	458	},
	459	};
	460
	461	module_platform_driver(dw_i2s_driver);
	462
b794dbcd	463	MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
3a9cf8ef RK	464	MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
	465	MODULE_LICENSE("GPL");
	466	MODULE_ALIAS("platform:designware_i2s");