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17467f23 TT |
1 | /* |
2 | * Freescale DMA ALSA SoC PCM driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
6 | * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed | |
7 | * under the terms of the GNU General Public License version 2. This | |
8 | * program is licensed "as is" without any warranty of any kind, whether | |
9 | * express or implied. | |
10 | * | |
11 | * This driver implements ASoC support for the Elo DMA controller, which is | |
12 | * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, | |
13 | * the PCM driver is what handles the DMA buffer. | |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/delay.h> | |
22 | ||
17467f23 TT |
23 | #include <sound/core.h> |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/soc.h> | |
27 | ||
28 | #include <asm/io.h> | |
29 | ||
30 | #include "fsl_dma.h" | |
31 | ||
32 | /* | |
33 | * The formats that the DMA controller supports, which is anything | |
34 | * that is 8, 16, or 32 bits. | |
35 | */ | |
36 | #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ | |
37 | SNDRV_PCM_FMTBIT_U8 | \ | |
38 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
39 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
40 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
41 | SNDRV_PCM_FMTBIT_U16_BE | \ | |
42 | SNDRV_PCM_FMTBIT_S24_LE | \ | |
43 | SNDRV_PCM_FMTBIT_S24_BE | \ | |
44 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
45 | SNDRV_PCM_FMTBIT_U24_BE | \ | |
46 | SNDRV_PCM_FMTBIT_S32_LE | \ | |
47 | SNDRV_PCM_FMTBIT_S32_BE | \ | |
48 | SNDRV_PCM_FMTBIT_U32_LE | \ | |
49 | SNDRV_PCM_FMTBIT_U32_BE) | |
50 | ||
51 | #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ | |
52 | SNDRV_PCM_RATE_CONTINUOUS) | |
53 | ||
54 | /* DMA global data. This structure is used by fsl_dma_open() to determine | |
55 | * which DMA channels to assign to a substream. Unfortunately, ASoC V1 does | |
56 | * not allow the machine driver to provide this information to the PCM | |
57 | * driver in advance, and there's no way to differentiate between the two | |
58 | * DMA controllers. So for now, this driver only supports one SSI device | |
59 | * using two DMA channels. We cannot support multiple DMA devices. | |
60 | * | |
61 | * ssi_stx_phys: bus address of SSI STX register | |
62 | * ssi_srx_phys: bus address of SSI SRX register | |
63 | * dma_channel: pointer to the DMA channel's registers | |
64 | * irq: IRQ for this DMA channel | |
65 | * assigned: set to 1 if that DMA channel is assigned to a substream | |
66 | */ | |
67 | static struct { | |
68 | dma_addr_t ssi_stx_phys; | |
69 | dma_addr_t ssi_srx_phys; | |
70 | struct ccsr_dma_channel __iomem *dma_channel[2]; | |
71 | unsigned int irq[2]; | |
72 | unsigned int assigned[2]; | |
73 | } dma_global_data; | |
74 | ||
75 | /* | |
76 | * The number of DMA links to use. Two is the bare minimum, but if you | |
77 | * have really small links you might need more. | |
78 | */ | |
79 | #define NUM_DMA_LINKS 2 | |
80 | ||
81 | /** fsl_dma_private: p-substream DMA data | |
82 | * | |
83 | * Each substream has a 1-to-1 association with a DMA channel. | |
84 | * | |
85 | * The link[] array is first because it needs to be aligned on a 32-byte | |
86 | * boundary, so putting it first will ensure alignment without padding the | |
87 | * structure. | |
88 | * | |
89 | * @link[]: array of link descriptors | |
90 | * @controller_id: which DMA controller (0, 1, ...) | |
91 | * @channel_id: which DMA channel on the controller (0, 1, 2, ...) | |
92 | * @dma_channel: pointer to the DMA channel's registers | |
93 | * @irq: IRQ for this DMA channel | |
94 | * @substream: pointer to the substream object, needed by the ISR | |
95 | * @ssi_sxx_phys: bus address of the STX or SRX register to use | |
96 | * @ld_buf_phys: physical address of the LD buffer | |
97 | * @current_link: index into link[] of the link currently being processed | |
98 | * @dma_buf_phys: physical address of the DMA buffer | |
99 | * @dma_buf_next: physical address of the next period to process | |
100 | * @dma_buf_end: physical address of the byte after the end of the DMA | |
101 | * @buffer period_size: the size of a single period | |
102 | * @num_periods: the number of periods in the DMA buffer | |
103 | */ | |
104 | struct fsl_dma_private { | |
105 | struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; | |
106 | unsigned int controller_id; | |
107 | unsigned int channel_id; | |
108 | struct ccsr_dma_channel __iomem *dma_channel; | |
109 | unsigned int irq; | |
110 | struct snd_pcm_substream *substream; | |
111 | dma_addr_t ssi_sxx_phys; | |
112 | dma_addr_t ld_buf_phys; | |
113 | unsigned int current_link; | |
114 | dma_addr_t dma_buf_phys; | |
115 | dma_addr_t dma_buf_next; | |
116 | dma_addr_t dma_buf_end; | |
117 | size_t period_size; | |
118 | unsigned int num_periods; | |
119 | }; | |
120 | ||
121 | /** | |
122 | * fsl_dma_hardare: define characteristics of the PCM hardware. | |
123 | * | |
124 | * The PCM hardware is the Freescale DMA controller. This structure defines | |
125 | * the capabilities of that hardware. | |
126 | * | |
127 | * Since the sampling rate and data format are not controlled by the DMA | |
128 | * controller, we specify no limits for those values. The only exception is | |
129 | * period_bytes_min, which is set to a reasonably low value to prevent the | |
130 | * DMA controller from generating too many interrupts per second. | |
131 | * | |
132 | * Since each link descriptor has a 32-bit byte count field, we set | |
133 | * period_bytes_max to the largest 32-bit number. We also have no maximum | |
134 | * number of periods. | |
be41e941 TT |
135 | * |
136 | * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a | |
137 | * limitation in the SSI driver requires the sample rates for playback and | |
138 | * capture to be the same. | |
17467f23 TT |
139 | */ |
140 | static const struct snd_pcm_hardware fsl_dma_hardware = { | |
141 | ||
4052ce4c TT |
142 | .info = SNDRV_PCM_INFO_INTERLEAVED | |
143 | SNDRV_PCM_INFO_MMAP | | |
be41e941 | 144 | SNDRV_PCM_INFO_MMAP_VALID | |
3a638ff2 TT |
145 | SNDRV_PCM_INFO_JOINT_DUPLEX | |
146 | SNDRV_PCM_INFO_PAUSE, | |
17467f23 TT |
147 | .formats = FSLDMA_PCM_FORMATS, |
148 | .rates = FSLDMA_PCM_RATES, | |
149 | .rate_min = 5512, | |
150 | .rate_max = 192000, | |
151 | .period_bytes_min = 512, /* A reasonable limit */ | |
152 | .period_bytes_max = (u32) -1, | |
153 | .periods_min = NUM_DMA_LINKS, | |
154 | .periods_max = (unsigned int) -1, | |
155 | .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ | |
156 | }; | |
157 | ||
158 | /** | |
159 | * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted | |
160 | * | |
161 | * This function should be called by the ISR whenever the DMA controller | |
162 | * halts data transfer. | |
163 | */ | |
164 | static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) | |
165 | { | |
166 | unsigned long flags; | |
167 | ||
168 | snd_pcm_stream_lock_irqsave(substream, flags); | |
169 | ||
170 | if (snd_pcm_running(substream)) | |
171 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); | |
172 | ||
173 | snd_pcm_stream_unlock_irqrestore(substream, flags); | |
174 | } | |
175 | ||
176 | /** | |
177 | * fsl_dma_update_pointers - update LD pointers to point to the next period | |
178 | * | |
179 | * As each period is completed, this function changes the the link | |
180 | * descriptor pointers for that period to point to the next period. | |
181 | */ | |
182 | static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) | |
183 | { | |
184 | struct fsl_dma_link_descriptor *link = | |
185 | &dma_private->link[dma_private->current_link]; | |
186 | ||
187 | /* Update our link descriptors to point to the next period */ | |
188 | if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
189 | link->source_addr = | |
190 | cpu_to_be32(dma_private->dma_buf_next); | |
191 | else | |
192 | link->dest_addr = | |
193 | cpu_to_be32(dma_private->dma_buf_next); | |
194 | ||
195 | /* Update our variables for next time */ | |
196 | dma_private->dma_buf_next += dma_private->period_size; | |
197 | ||
198 | if (dma_private->dma_buf_next >= dma_private->dma_buf_end) | |
199 | dma_private->dma_buf_next = dma_private->dma_buf_phys; | |
200 | ||
201 | if (++dma_private->current_link >= NUM_DMA_LINKS) | |
202 | dma_private->current_link = 0; | |
203 | } | |
204 | ||
205 | /** | |
206 | * fsl_dma_isr: interrupt handler for the DMA controller | |
207 | * | |
208 | * @irq: IRQ of the DMA channel | |
209 | * @dev_id: pointer to the dma_private structure for this DMA channel | |
210 | */ | |
211 | static irqreturn_t fsl_dma_isr(int irq, void *dev_id) | |
212 | { | |
213 | struct fsl_dma_private *dma_private = dev_id; | |
214 | struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; | |
215 | irqreturn_t ret = IRQ_NONE; | |
216 | u32 sr, sr2 = 0; | |
217 | ||
218 | /* We got an interrupt, so read the status register to see what we | |
219 | were interrupted for. | |
220 | */ | |
221 | sr = in_be32(&dma_channel->sr); | |
222 | ||
223 | if (sr & CCSR_DMA_SR_TE) { | |
224 | dev_err(dma_private->substream->pcm->card->dev, | |
225 | "DMA transmit error (controller=%u channel=%u irq=%u\n", | |
226 | dma_private->controller_id, | |
227 | dma_private->channel_id, irq); | |
228 | fsl_dma_abort_stream(dma_private->substream); | |
229 | sr2 |= CCSR_DMA_SR_TE; | |
230 | ret = IRQ_HANDLED; | |
231 | } | |
232 | ||
233 | if (sr & CCSR_DMA_SR_CH) | |
234 | ret = IRQ_HANDLED; | |
235 | ||
236 | if (sr & CCSR_DMA_SR_PE) { | |
237 | dev_err(dma_private->substream->pcm->card->dev, | |
238 | "DMA%u programming error (channel=%u irq=%u)\n", | |
239 | dma_private->controller_id, | |
240 | dma_private->channel_id, irq); | |
241 | fsl_dma_abort_stream(dma_private->substream); | |
242 | sr2 |= CCSR_DMA_SR_PE; | |
243 | ret = IRQ_HANDLED; | |
244 | } | |
245 | ||
246 | if (sr & CCSR_DMA_SR_EOLNI) { | |
247 | sr2 |= CCSR_DMA_SR_EOLNI; | |
248 | ret = IRQ_HANDLED; | |
249 | } | |
250 | ||
251 | if (sr & CCSR_DMA_SR_CB) | |
252 | ret = IRQ_HANDLED; | |
253 | ||
254 | if (sr & CCSR_DMA_SR_EOSI) { | |
255 | struct snd_pcm_substream *substream = dma_private->substream; | |
256 | ||
257 | /* Tell ALSA we completed a period. */ | |
258 | snd_pcm_period_elapsed(substream); | |
259 | ||
260 | /* | |
261 | * Update our link descriptors to point to the next period. We | |
262 | * only need to do this if the number of periods is not equal to | |
263 | * the number of links. | |
264 | */ | |
265 | if (dma_private->num_periods != NUM_DMA_LINKS) | |
266 | fsl_dma_update_pointers(dma_private); | |
267 | ||
268 | sr2 |= CCSR_DMA_SR_EOSI; | |
269 | ret = IRQ_HANDLED; | |
270 | } | |
271 | ||
272 | if (sr & CCSR_DMA_SR_EOLSI) { | |
273 | sr2 |= CCSR_DMA_SR_EOLSI; | |
274 | ret = IRQ_HANDLED; | |
275 | } | |
276 | ||
277 | /* Clear the bits that we set */ | |
278 | if (sr2) | |
279 | out_be32(&dma_channel->sr, sr2); | |
280 | ||
281 | return ret; | |
282 | } | |
283 | ||
284 | /** | |
285 | * fsl_dma_new: initialize this PCM driver. | |
286 | * | |
287 | * This function is called when the codec driver calls snd_soc_new_pcms(), | |
87506549 | 288 | * once for each .dai_link in the machine driver's snd_soc_card |
17467f23 TT |
289 | * structure. |
290 | */ | |
8cf7b2b3 | 291 | static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, |
17467f23 TT |
292 | struct snd_pcm *pcm) |
293 | { | |
294 | static u64 fsl_dma_dmamask = DMA_BIT_MASK(32); | |
295 | int ret; | |
296 | ||
297 | if (!card->dev->dma_mask) | |
298 | card->dev->dma_mask = &fsl_dma_dmamask; | |
299 | ||
300 | if (!card->dev->coherent_dma_mask) | |
301 | card->dev->coherent_dma_mask = fsl_dma_dmamask; | |
302 | ||
5c15a686 | 303 | ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, |
17467f23 TT |
304 | fsl_dma_hardware.buffer_bytes_max, |
305 | &pcm->streams[0].substream->dma_buffer); | |
306 | if (ret) { | |
307 | dev_err(card->dev, | |
308 | "Can't allocate playback DMA buffer (size=%u)\n", | |
309 | fsl_dma_hardware.buffer_bytes_max); | |
310 | return -ENOMEM; | |
311 | } | |
312 | ||
5c15a686 | 313 | ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, |
17467f23 TT |
314 | fsl_dma_hardware.buffer_bytes_max, |
315 | &pcm->streams[1].substream->dma_buffer); | |
316 | if (ret) { | |
317 | snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); | |
318 | dev_err(card->dev, | |
319 | "Can't allocate capture DMA buffer (size=%u)\n", | |
320 | fsl_dma_hardware.buffer_bytes_max); | |
321 | return -ENOMEM; | |
322 | } | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | /** | |
328 | * fsl_dma_open: open a new substream. | |
329 | * | |
330 | * Each substream has its own DMA buffer. | |
bf9c8c9d TT |
331 | * |
332 | * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link | |
333 | * descriptors that ping-pong from one period to the next. For example, if | |
334 | * there are six periods and two link descriptors, this is how they look | |
335 | * before playback starts: | |
336 | * | |
337 | * The last link descriptor | |
338 | * ____________ points back to the first | |
339 | * | | | |
340 | * V | | |
341 | * ___ ___ | | |
342 | * | |->| |->| | |
343 | * |___| |___| | |
344 | * | | | |
345 | * | | | |
346 | * V V | |
347 | * _________________________________________ | |
348 | * | | | | | | | The DMA buffer is | |
349 | * | | | | | | | divided into 6 parts | |
350 | * |______|______|______|______|______|______| | |
351 | * | |
352 | * and here's how they look after the first period is finished playing: | |
353 | * | |
354 | * ____________ | |
355 | * | | | |
356 | * V | | |
357 | * ___ ___ | | |
358 | * | |->| |->| | |
359 | * |___| |___| | |
360 | * | | | |
361 | * |______________ | |
362 | * | | | |
363 | * V V | |
364 | * _________________________________________ | |
365 | * | | | | | | | | |
366 | * | | | | | | | | |
367 | * |______|______|______|______|______|______| | |
368 | * | |
369 | * The first link descriptor now points to the third period. The DMA | |
370 | * controller is currently playing the second period. When it finishes, it | |
371 | * will jump back to the first descriptor and play the third period. | |
372 | * | |
373 | * There are four reasons we do this: | |
374 | * | |
375 | * 1. The only way to get the DMA controller to automatically restart the | |
376 | * transfer when it gets to the end of the buffer is to use chaining | |
377 | * mode. Basic direct mode doesn't offer that feature. | |
378 | * 2. We need to receive an interrupt at the end of every period. The DMA | |
379 | * controller can generate an interrupt at the end of every link transfer | |
380 | * (aka segment). Making each period into a DMA segment will give us the | |
381 | * interrupts we need. | |
382 | * 3. By creating only two link descriptors, regardless of the number of | |
383 | * periods, we do not need to reallocate the link descriptors if the | |
384 | * number of periods changes. | |
385 | * 4. All of the audio data is still stored in a single, contiguous DMA | |
386 | * buffer, which is what ALSA expects. We're just dividing it into | |
387 | * contiguous parts, and creating a link descriptor for each one. | |
17467f23 TT |
388 | */ |
389 | static int fsl_dma_open(struct snd_pcm_substream *substream) | |
390 | { | |
391 | struct snd_pcm_runtime *runtime = substream->runtime; | |
392 | struct fsl_dma_private *dma_private; | |
bf9c8c9d | 393 | struct ccsr_dma_channel __iomem *dma_channel; |
17467f23 | 394 | dma_addr_t ld_buf_phys; |
bf9c8c9d TT |
395 | u64 temp_link; /* Pointer to next link descriptor */ |
396 | u32 mr; | |
17467f23 TT |
397 | unsigned int channel; |
398 | int ret = 0; | |
bf9c8c9d | 399 | unsigned int i; |
17467f23 TT |
400 | |
401 | /* | |
402 | * Reject any DMA buffer whose size is not a multiple of the period | |
403 | * size. We need to make sure that the DMA buffer can be evenly divided | |
404 | * into periods. | |
405 | */ | |
406 | ret = snd_pcm_hw_constraint_integer(runtime, | |
407 | SNDRV_PCM_HW_PARAM_PERIODS); | |
408 | if (ret < 0) { | |
409 | dev_err(substream->pcm->card->dev, "invalid buffer size\n"); | |
410 | return ret; | |
411 | } | |
412 | ||
413 | channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; | |
414 | ||
415 | if (dma_global_data.assigned[channel]) { | |
416 | dev_err(substream->pcm->card->dev, | |
417 | "DMA channel already assigned\n"); | |
418 | return -EBUSY; | |
419 | } | |
420 | ||
5c15a686 | 421 | dma_private = dma_alloc_coherent(substream->pcm->card->dev, |
17467f23 TT |
422 | sizeof(struct fsl_dma_private), &ld_buf_phys, GFP_KERNEL); |
423 | if (!dma_private) { | |
424 | dev_err(substream->pcm->card->dev, | |
425 | "can't allocate DMA private data\n"); | |
426 | return -ENOMEM; | |
427 | } | |
428 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
429 | dma_private->ssi_sxx_phys = dma_global_data.ssi_stx_phys; | |
430 | else | |
431 | dma_private->ssi_sxx_phys = dma_global_data.ssi_srx_phys; | |
432 | ||
433 | dma_private->dma_channel = dma_global_data.dma_channel[channel]; | |
434 | dma_private->irq = dma_global_data.irq[channel]; | |
435 | dma_private->substream = substream; | |
436 | dma_private->ld_buf_phys = ld_buf_phys; | |
437 | dma_private->dma_buf_phys = substream->dma_buffer.addr; | |
438 | ||
439 | /* We only support one DMA controller for now */ | |
440 | dma_private->controller_id = 0; | |
441 | dma_private->channel_id = channel; | |
442 | ||
443 | ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private); | |
444 | if (ret) { | |
445 | dev_err(substream->pcm->card->dev, | |
446 | "can't register ISR for IRQ %u (ret=%i)\n", | |
447 | dma_private->irq, ret); | |
5c15a686 | 448 | dma_free_coherent(substream->pcm->card->dev, |
17467f23 TT |
449 | sizeof(struct fsl_dma_private), |
450 | dma_private, dma_private->ld_buf_phys); | |
451 | return ret; | |
452 | } | |
453 | ||
454 | dma_global_data.assigned[channel] = 1; | |
455 | ||
456 | snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); | |
457 | snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); | |
458 | runtime->private_data = dma_private; | |
459 | ||
bf9c8c9d TT |
460 | /* Program the fixed DMA controller parameters */ |
461 | ||
462 | dma_channel = dma_private->dma_channel; | |
463 | ||
464 | temp_link = dma_private->ld_buf_phys + | |
465 | sizeof(struct fsl_dma_link_descriptor); | |
466 | ||
467 | for (i = 0; i < NUM_DMA_LINKS; i++) { | |
85ef2375 | 468 | dma_private->link[i].next = cpu_to_be64(temp_link); |
bf9c8c9d TT |
469 | |
470 | temp_link += sizeof(struct fsl_dma_link_descriptor); | |
471 | } | |
472 | /* The last link descriptor points to the first */ | |
473 | dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); | |
474 | ||
475 | /* Tell the DMA controller where the first link descriptor is */ | |
476 | out_be32(&dma_channel->clndar, | |
477 | CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); | |
478 | out_be32(&dma_channel->eclndar, | |
479 | CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); | |
480 | ||
481 | /* The manual says the BCR must be clear before enabling EMP */ | |
482 | out_be32(&dma_channel->bcr, 0); | |
483 | ||
484 | /* | |
485 | * Program the mode register for interrupts, external master control, | |
486 | * and source/destination hold. Also clear the Channel Abort bit. | |
487 | */ | |
488 | mr = in_be32(&dma_channel->mr) & | |
489 | ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); | |
490 | ||
491 | /* | |
492 | * We want External Master Start and External Master Pause enabled, | |
493 | * because the SSI is controlling the DMA controller. We want the DMA | |
494 | * controller to be set up in advance, and then we signal only the SSI | |
495 | * to start transferring. | |
496 | * | |
497 | * We want End-Of-Segment Interrupts enabled, because this will generate | |
498 | * an interrupt at the end of each segment (each link descriptor | |
499 | * represents one segment). Each DMA segment is the same thing as an | |
500 | * ALSA period, so this is how we get an interrupt at the end of every | |
501 | * period. | |
502 | * | |
503 | * We want Error Interrupt enabled, so that we can get an error if | |
504 | * the DMA controller is mis-programmed somehow. | |
505 | */ | |
506 | mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | | |
507 | CCSR_DMA_MR_EMS_EN; | |
508 | ||
509 | /* For playback, we want the destination address to be held. For | |
510 | capture, set the source address to be held. */ | |
511 | mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? | |
512 | CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; | |
513 | ||
514 | out_be32(&dma_channel->mr, mr); | |
515 | ||
17467f23 TT |
516 | return 0; |
517 | } | |
518 | ||
519 | /** | |
bf9c8c9d | 520 | * fsl_dma_hw_params: continue initializing the DMA links |
17467f23 | 521 | * |
bf9c8c9d TT |
522 | * This function obtains hardware parameters about the opened stream and |
523 | * programs the DMA controller accordingly. | |
17467f23 | 524 | * |
85ef2375 TT |
525 | * One drawback of big-endian is that when copying integers of different |
526 | * sizes to a fixed-sized register, the address to which the integer must be | |
527 | * copied is dependent on the size of the integer. | |
17467f23 TT |
528 | * |
529 | * For example, if P is the address of a 32-bit register, and X is a 32-bit | |
530 | * integer, then X should be copied to address P. However, if X is a 16-bit | |
531 | * integer, then it should be copied to P+2. If X is an 8-bit register, | |
532 | * then it should be copied to P+3. | |
533 | * | |
534 | * So for playback of 8-bit samples, the DMA controller must transfer single | |
535 | * bytes from the DMA buffer to the last byte of the STX0 register, i.e. | |
536 | * offset by 3 bytes. For 16-bit samples, the offset is two bytes. | |
537 | * | |
538 | * For 24-bit samples, the offset is 1 byte. However, the DMA controller | |
539 | * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, | |
540 | * and 8 bytes at a time). So we do not support packed 24-bit samples. | |
541 | * 24-bit data must be padded to 32 bits. | |
542 | */ | |
85ef2375 TT |
543 | static int fsl_dma_hw_params(struct snd_pcm_substream *substream, |
544 | struct snd_pcm_hw_params *hw_params) | |
17467f23 TT |
545 | { |
546 | struct snd_pcm_runtime *runtime = substream->runtime; | |
547 | struct fsl_dma_private *dma_private = runtime->private_data; | |
85ef2375 TT |
548 | |
549 | /* Number of bits per sample */ | |
550 | unsigned int sample_size = | |
551 | snd_pcm_format_physical_width(params_format(hw_params)); | |
552 | ||
553 | /* Number of bytes per frame */ | |
554 | unsigned int frame_size = 2 * (sample_size / 8); | |
555 | ||
556 | /* Bus address of SSI STX register */ | |
557 | dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; | |
558 | ||
559 | /* Size of the DMA buffer, in bytes */ | |
560 | size_t buffer_size = params_buffer_bytes(hw_params); | |
561 | ||
562 | /* Number of bytes per period */ | |
563 | size_t period_size = params_period_bytes(hw_params); | |
564 | ||
565 | /* Pointer to next period */ | |
566 | dma_addr_t temp_addr = substream->dma_buffer.addr; | |
567 | ||
568 | /* Pointer to DMA controller */ | |
17467f23 | 569 | struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; |
85ef2375 TT |
570 | |
571 | u32 mr; /* DMA Mode Register */ | |
572 | ||
17467f23 | 573 | unsigned int i; |
17467f23 | 574 | |
85ef2375 TT |
575 | /* Initialize our DMA tracking variables */ |
576 | dma_private->period_size = period_size; | |
577 | dma_private->num_periods = params_periods(hw_params); | |
578 | dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; | |
579 | dma_private->dma_buf_next = dma_private->dma_buf_phys + | |
580 | (NUM_DMA_LINKS * period_size); | |
581 | ||
582 | if (dma_private->dma_buf_next >= dma_private->dma_buf_end) | |
583 | /* This happens if the number of periods == NUM_DMA_LINKS */ | |
584 | dma_private->dma_buf_next = dma_private->dma_buf_phys; | |
17467f23 TT |
585 | |
586 | mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | | |
587 | CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); | |
588 | ||
85ef2375 TT |
589 | /* Due to a quirk of the SSI's STX register, the target address |
590 | * for the DMA operations depends on the sample size. So we calculate | |
591 | * that offset here. While we're at it, also tell the DMA controller | |
592 | * how much data to transfer per sample. | |
593 | */ | |
594 | switch (sample_size) { | |
17467f23 TT |
595 | case 8: |
596 | mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; | |
597 | ssi_sxx_phys += 3; | |
598 | break; | |
599 | case 16: | |
600 | mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; | |
601 | ssi_sxx_phys += 2; | |
602 | break; | |
603 | case 32: | |
604 | mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; | |
605 | break; | |
606 | default: | |
85ef2375 | 607 | /* We should never get here */ |
17467f23 | 608 | dev_err(substream->pcm->card->dev, |
85ef2375 | 609 | "unsupported sample size %u\n", sample_size); |
17467f23 TT |
610 | return -EINVAL; |
611 | } | |
612 | ||
17467f23 TT |
613 | /* |
614 | * BWC should always be a multiple of the frame size. BWC determines | |
615 | * how many bytes are sent/received before the DMA controller checks the | |
616 | * SSI to see if it needs to stop. For playback, the transmit FIFO can | |
617 | * hold three frames, so we want to send two frames at a time. For | |
618 | * capture, the receive FIFO is triggered when it contains one frame, so | |
619 | * we want to receive one frame at a time. | |
620 | */ | |
17467f23 TT |
621 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
622 | mr |= CCSR_DMA_MR_BWC(2 * frame_size); | |
623 | else | |
624 | mr |= CCSR_DMA_MR_BWC(frame_size); | |
625 | ||
626 | out_be32(&dma_channel->mr, mr); | |
627 | ||
17467f23 TT |
628 | for (i = 0; i < NUM_DMA_LINKS; i++) { |
629 | struct fsl_dma_link_descriptor *link = &dma_private->link[i]; | |
630 | ||
85ef2375 TT |
631 | link->count = cpu_to_be32(period_size); |
632 | ||
633 | /* Even though the DMA controller supports 36-bit addressing, | |
634 | * for simplicity we allow only 32-bit addresses for the audio | |
635 | * buffer itself. This was enforced in fsl_dma_new() with the | |
636 | * DMA mask. | |
637 | * | |
638 | * The snoop bit tells the DMA controller whether it should tell | |
639 | * the ECM to snoop during a read or write to an address. For | |
640 | * audio, we use DMA to transfer data between memory and an I/O | |
641 | * device (the SSI's STX0 or SRX0 register). Snooping is only | |
642 | * needed if there is a cache, so we need to snoop memory | |
643 | * addresses only. For playback, that means we snoop the source | |
644 | * but not the destination. For capture, we snoop the | |
645 | * destination but not the source. | |
646 | * | |
647 | * Note that failing to snoop properly is unlikely to cause | |
648 | * cache incoherency if the period size is larger than the | |
649 | * size of L1 cache. This is because filling in one period will | |
650 | * flush out the data for the previous period. So if you | |
651 | * increased period_bytes_min to a large enough size, you might | |
652 | * get more performance by not snooping, and you'll still be | |
653 | * okay. | |
654 | */ | |
655 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
656 | link->source_addr = cpu_to_be32(temp_addr); | |
657 | link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); | |
658 | ||
17467f23 | 659 | link->dest_addr = cpu_to_be32(ssi_sxx_phys); |
85ef2375 TT |
660 | link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP); |
661 | } else { | |
17467f23 | 662 | link->source_addr = cpu_to_be32(ssi_sxx_phys); |
85ef2375 TT |
663 | link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP); |
664 | ||
665 | link->dest_addr = cpu_to_be32(temp_addr); | |
666 | link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); | |
667 | } | |
668 | ||
669 | temp_addr += period_size; | |
17467f23 TT |
670 | } |
671 | ||
672 | return 0; | |
673 | } | |
674 | ||
675 | /** | |
676 | * fsl_dma_pointer: determine the current position of the DMA transfer | |
677 | * | |
678 | * This function is called by ALSA when ALSA wants to know where in the | |
679 | * stream buffer the hardware currently is. | |
680 | * | |
681 | * For playback, the SAR register contains the physical address of the most | |
682 | * recent DMA transfer. For capture, the value is in the DAR register. | |
683 | * | |
684 | * The base address of the buffer is stored in the source_addr field of the | |
685 | * first link descriptor. | |
686 | */ | |
687 | static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) | |
688 | { | |
689 | struct snd_pcm_runtime *runtime = substream->runtime; | |
690 | struct fsl_dma_private *dma_private = runtime->private_data; | |
691 | struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; | |
692 | dma_addr_t position; | |
693 | snd_pcm_uframes_t frames; | |
694 | ||
695 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
696 | position = in_be32(&dma_channel->sar); | |
697 | else | |
698 | position = in_be32(&dma_channel->dar); | |
699 | ||
a4d11fe5 TT |
700 | /* |
701 | * When capture is started, the SSI immediately starts to fill its FIFO. | |
702 | * This means that the DMA controller is not started until the FIFO is | |
703 | * full. However, ALSA calls this function before that happens, when | |
704 | * MR.DAR is still zero. In this case, just return zero to indicate | |
705 | * that nothing has been received yet. | |
706 | */ | |
707 | if (!position) | |
708 | return 0; | |
709 | ||
710 | if ((position < dma_private->dma_buf_phys) || | |
711 | (position > dma_private->dma_buf_end)) { | |
712 | dev_err(substream->pcm->card->dev, | |
713 | "dma pointer is out of range, halting stream\n"); | |
714 | return SNDRV_PCM_POS_XRUN; | |
715 | } | |
716 | ||
17467f23 TT |
717 | frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); |
718 | ||
719 | /* | |
720 | * If the current address is just past the end of the buffer, wrap it | |
721 | * around. | |
722 | */ | |
723 | if (frames == runtime->buffer_size) | |
724 | frames = 0; | |
725 | ||
726 | return frames; | |
727 | } | |
728 | ||
729 | /** | |
730 | * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() | |
731 | * | |
732 | * Release the resources allocated in fsl_dma_hw_params() and de-program the | |
733 | * registers. | |
734 | * | |
735 | * This function can be called multiple times. | |
736 | */ | |
737 | static int fsl_dma_hw_free(struct snd_pcm_substream *substream) | |
738 | { | |
739 | struct snd_pcm_runtime *runtime = substream->runtime; | |
740 | struct fsl_dma_private *dma_private = runtime->private_data; | |
741 | ||
742 | if (dma_private) { | |
743 | struct ccsr_dma_channel __iomem *dma_channel; | |
744 | ||
745 | dma_channel = dma_private->dma_channel; | |
746 | ||
747 | /* Stop the DMA */ | |
748 | out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); | |
749 | out_be32(&dma_channel->mr, 0); | |
750 | ||
751 | /* Reset all the other registers */ | |
752 | out_be32(&dma_channel->sr, -1); | |
753 | out_be32(&dma_channel->clndar, 0); | |
754 | out_be32(&dma_channel->eclndar, 0); | |
755 | out_be32(&dma_channel->satr, 0); | |
756 | out_be32(&dma_channel->sar, 0); | |
757 | out_be32(&dma_channel->datr, 0); | |
758 | out_be32(&dma_channel->dar, 0); | |
759 | out_be32(&dma_channel->bcr, 0); | |
760 | out_be32(&dma_channel->nlndar, 0); | |
761 | out_be32(&dma_channel->enlndar, 0); | |
762 | } | |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
767 | /** | |
768 | * fsl_dma_close: close the stream. | |
769 | */ | |
770 | static int fsl_dma_close(struct snd_pcm_substream *substream) | |
771 | { | |
772 | struct snd_pcm_runtime *runtime = substream->runtime; | |
773 | struct fsl_dma_private *dma_private = runtime->private_data; | |
774 | int dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; | |
775 | ||
776 | if (dma_private) { | |
777 | if (dma_private->irq) | |
778 | free_irq(dma_private->irq, dma_private); | |
779 | ||
780 | if (dma_private->ld_buf_phys) { | |
5c15a686 | 781 | dma_unmap_single(substream->pcm->card->dev, |
17467f23 TT |
782 | dma_private->ld_buf_phys, |
783 | sizeof(dma_private->link), DMA_TO_DEVICE); | |
784 | } | |
785 | ||
786 | /* Deallocate the fsl_dma_private structure */ | |
5c15a686 | 787 | dma_free_coherent(substream->pcm->card->dev, |
17467f23 TT |
788 | sizeof(struct fsl_dma_private), |
789 | dma_private, dma_private->ld_buf_phys); | |
790 | substream->runtime->private_data = NULL; | |
791 | } | |
792 | ||
793 | dma_global_data.assigned[dir] = 0; | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
798 | /* | |
799 | * Remove this PCM driver. | |
800 | */ | |
801 | static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) | |
802 | { | |
803 | struct snd_pcm_substream *substream; | |
804 | unsigned int i; | |
805 | ||
806 | for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { | |
807 | substream = pcm->streams[i].substream; | |
808 | if (substream) { | |
809 | snd_dma_free_pages(&substream->dma_buffer); | |
810 | substream->dma_buffer.area = NULL; | |
811 | substream->dma_buffer.addr = 0; | |
812 | } | |
813 | } | |
814 | } | |
815 | ||
816 | static struct snd_pcm_ops fsl_dma_ops = { | |
817 | .open = fsl_dma_open, | |
818 | .close = fsl_dma_close, | |
819 | .ioctl = snd_pcm_lib_ioctl, | |
820 | .hw_params = fsl_dma_hw_params, | |
821 | .hw_free = fsl_dma_hw_free, | |
17467f23 TT |
822 | .pointer = fsl_dma_pointer, |
823 | }; | |
824 | ||
825 | struct snd_soc_platform fsl_soc_platform = { | |
826 | .name = "fsl-dma", | |
827 | .pcm_ops = &fsl_dma_ops, | |
828 | .pcm_new = fsl_dma_new, | |
829 | .pcm_free = fsl_dma_free_dma_buffers, | |
830 | }; | |
831 | EXPORT_SYMBOL_GPL(fsl_soc_platform); | |
832 | ||
833 | /** | |
834 | * fsl_dma_configure: store the DMA parameters from the fabric driver. | |
835 | * | |
836 | * This function is called by the ASoC fabric driver to give us the DMA and | |
837 | * SSI channel information. | |
838 | * | |
839 | * Unfortunately, ASoC V1 does make it possible to determine the DMA/SSI | |
840 | * data when a substream is created, so for now we need to store this data | |
841 | * into a global variable. This means that we can only support one DMA | |
842 | * controller, and hence only one SSI. | |
843 | */ | |
844 | int fsl_dma_configure(struct fsl_dma_info *dma_info) | |
845 | { | |
846 | static int initialized; | |
847 | ||
848 | /* We only support one DMA controller for now */ | |
849 | if (initialized) | |
850 | return 0; | |
851 | ||
852 | dma_global_data.ssi_stx_phys = dma_info->ssi_stx_phys; | |
853 | dma_global_data.ssi_srx_phys = dma_info->ssi_srx_phys; | |
854 | dma_global_data.dma_channel[0] = dma_info->dma_channel[0]; | |
855 | dma_global_data.dma_channel[1] = dma_info->dma_channel[1]; | |
856 | dma_global_data.irq[0] = dma_info->dma_irq[0]; | |
857 | dma_global_data.irq[1] = dma_info->dma_irq[1]; | |
858 | dma_global_data.assigned[0] = 0; | |
859 | dma_global_data.assigned[1] = 0; | |
860 | ||
861 | initialized = 1; | |
862 | return 1; | |
863 | } | |
864 | EXPORT_SYMBOL_GPL(fsl_dma_configure); | |
865 | ||
c9b3a40f | 866 | static int __init fsl_soc_platform_init(void) |
958e792c MB |
867 | { |
868 | return snd_soc_register_platform(&fsl_soc_platform); | |
869 | } | |
870 | module_init(fsl_soc_platform_init); | |
871 | ||
872 | static void __exit fsl_soc_platform_exit(void) | |
873 | { | |
874 | snd_soc_unregister_platform(&fsl_soc_platform); | |
875 | } | |
876 | module_exit(fsl_soc_platform_exit); | |
877 | ||
17467f23 TT |
878 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
879 | MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM module"); | |
880 | MODULE_LICENSE("GPL"); |