Commit | Line | Data |
---|---|---|
43550821 XL |
1 | /* |
2 | * Freescale ALSA SoC Digital Audio Interface (SAI) driver. | |
3 | * | |
c3ecef21 | 4 | * Copyright 2012-2015 Freescale Semiconductor, Inc. |
43550821 XL |
5 | * |
6 | * This program is free software, you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation, either version 2 of the License, or(at your | |
9 | * option) any later version. | |
10 | * | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of_address.h> | |
78957fc3 | 18 | #include <linux/regmap.h> |
43550821 | 19 | #include <linux/slab.h> |
512feb4e | 20 | #include <linux/time.h> |
43550821 XL |
21 | #include <sound/core.h> |
22 | #include <sound/dmaengine_pcm.h> | |
23 | #include <sound/pcm_params.h> | |
4d245850 FE |
24 | #include <linux/mfd/syscon.h> |
25 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
43550821 XL |
26 | |
27 | #include "fsl_sai.h" | |
c7540644 | 28 | #include "imx-pcm.h" |
43550821 | 29 | |
e2681a1b NC |
30 | #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ |
31 | FSL_SAI_CSR_FEIE) | |
32 | ||
444c37ae | 33 | static const unsigned int fsl_sai_rates[] = { |
c5f4823b ZW |
34 | 8000, 11025, 12000, 16000, 22050, |
35 | 24000, 32000, 44100, 48000, 64000, | |
36 | 88200, 96000, 176400, 192000 | |
37 | }; | |
38 | ||
444c37ae | 39 | static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { |
c5f4823b ZW |
40 | .count = ARRAY_SIZE(fsl_sai_rates), |
41 | .list = fsl_sai_rates, | |
42 | }; | |
43 | ||
e2681a1b NC |
44 | static irqreturn_t fsl_sai_isr(int irq, void *devid) |
45 | { | |
46 | struct fsl_sai *sai = (struct fsl_sai *)devid; | |
47 | struct device *dev = &sai->pdev->dev; | |
413312aa NC |
48 | u32 flags, xcsr, mask; |
49 | bool irq_none = true; | |
50 | ||
51 | /* | |
52 | * Both IRQ status bits and IRQ mask bits are in the xCSR but | |
53 | * different shifts. And we here create a mask only for those | |
54 | * IRQs that we activated. | |
55 | */ | |
e2681a1b NC |
56 | mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; |
57 | ||
58 | /* Tx IRQ */ | |
59 | regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr); | |
413312aa NC |
60 | flags = xcsr & mask; |
61 | ||
62 | if (flags) | |
63 | irq_none = false; | |
64 | else | |
65 | goto irq_rx; | |
e2681a1b | 66 | |
413312aa | 67 | if (flags & FSL_SAI_CSR_WSF) |
e2681a1b NC |
68 | dev_dbg(dev, "isr: Start of Tx word detected\n"); |
69 | ||
413312aa | 70 | if (flags & FSL_SAI_CSR_SEF) |
e2681a1b NC |
71 | dev_warn(dev, "isr: Tx Frame sync error detected\n"); |
72 | ||
413312aa | 73 | if (flags & FSL_SAI_CSR_FEF) { |
e2681a1b NC |
74 | dev_warn(dev, "isr: Transmit underrun detected\n"); |
75 | /* FIFO reset for safety */ | |
76 | xcsr |= FSL_SAI_CSR_FR; | |
77 | } | |
78 | ||
413312aa | 79 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
80 | dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); |
81 | ||
413312aa | 82 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
83 | dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); |
84 | ||
413312aa NC |
85 | flags &= FSL_SAI_CSR_xF_W_MASK; |
86 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
87 | ||
88 | if (flags) | |
89 | regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr); | |
e2681a1b | 90 | |
413312aa | 91 | irq_rx: |
e2681a1b NC |
92 | /* Rx IRQ */ |
93 | regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr); | |
413312aa | 94 | flags = xcsr & mask; |
e2681a1b | 95 | |
413312aa NC |
96 | if (flags) |
97 | irq_none = false; | |
98 | else | |
99 | goto out; | |
100 | ||
101 | if (flags & FSL_SAI_CSR_WSF) | |
e2681a1b NC |
102 | dev_dbg(dev, "isr: Start of Rx word detected\n"); |
103 | ||
413312aa | 104 | if (flags & FSL_SAI_CSR_SEF) |
e2681a1b NC |
105 | dev_warn(dev, "isr: Rx Frame sync error detected\n"); |
106 | ||
413312aa | 107 | if (flags & FSL_SAI_CSR_FEF) { |
e2681a1b NC |
108 | dev_warn(dev, "isr: Receive overflow detected\n"); |
109 | /* FIFO reset for safety */ | |
110 | xcsr |= FSL_SAI_CSR_FR; | |
111 | } | |
112 | ||
413312aa | 113 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
114 | dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); |
115 | ||
413312aa | 116 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
117 | dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); |
118 | ||
413312aa NC |
119 | flags &= FSL_SAI_CSR_xF_W_MASK; |
120 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
e2681a1b | 121 | |
413312aa | 122 | if (flags) |
4800f88b | 123 | regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr); |
413312aa NC |
124 | |
125 | out: | |
126 | if (irq_none) | |
127 | return IRQ_NONE; | |
128 | else | |
129 | return IRQ_HANDLED; | |
e2681a1b NC |
130 | } |
131 | ||
c1df2964 ZW |
132 | static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, |
133 | u32 rx_mask, int slots, int slot_width) | |
134 | { | |
135 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
136 | ||
137 | sai->slots = slots; | |
138 | sai->slot_width = slot_width; | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
43550821 XL |
143 | static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, |
144 | int clk_id, unsigned int freq, int fsl_dir) | |
145 | { | |
43550821 | 146 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b NC |
147 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
148 | u32 val_cr2 = 0; | |
633ff8f8 | 149 | |
43550821 XL |
150 | switch (clk_id) { |
151 | case FSL_SAI_CLK_BUS: | |
43550821 XL |
152 | val_cr2 |= FSL_SAI_CR2_MSEL_BUS; |
153 | break; | |
154 | case FSL_SAI_CLK_MAST1: | |
43550821 XL |
155 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; |
156 | break; | |
157 | case FSL_SAI_CLK_MAST2: | |
43550821 XL |
158 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; |
159 | break; | |
160 | case FSL_SAI_CLK_MAST3: | |
43550821 XL |
161 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; |
162 | break; | |
163 | default: | |
164 | return -EINVAL; | |
165 | } | |
633ff8f8 | 166 | |
2a266f8b NC |
167 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), |
168 | FSL_SAI_CR2_MSEL_MASK, val_cr2); | |
43550821 XL |
169 | |
170 | return 0; | |
171 | } | |
172 | ||
173 | static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
174 | int clk_id, unsigned int freq, int dir) | |
175 | { | |
4e3a99f5 | 176 | int ret; |
43550821 XL |
177 | |
178 | if (dir == SND_SOC_CLOCK_IN) | |
179 | return 0; | |
180 | ||
43550821 XL |
181 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, |
182 | FSL_FMT_TRANSMITTER); | |
183 | if (ret) { | |
190af12d | 184 | dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); |
78957fc3 | 185 | return ret; |
43550821 XL |
186 | } |
187 | ||
188 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, | |
189 | FSL_FMT_RECEIVER); | |
78957fc3 | 190 | if (ret) |
190af12d | 191 | dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); |
43550821 | 192 | |
1fb2d9d7 | 193 | return ret; |
43550821 XL |
194 | } |
195 | ||
196 | static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, | |
197 | unsigned int fmt, int fsl_dir) | |
198 | { | |
43550821 | 199 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b NC |
200 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
201 | u32 val_cr2 = 0, val_cr4 = 0; | |
43550821 | 202 | |
eadb0019 | 203 | if (!sai->is_lsb_first) |
72aa62be | 204 | val_cr4 |= FSL_SAI_CR4_MF; |
43550821 | 205 | |
13cde090 | 206 | /* DAI mode */ |
43550821 XL |
207 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
208 | case SND_SOC_DAIFMT_I2S: | |
a3f7dcc9 XL |
209 | /* |
210 | * Frame low, 1clk before data, one word length for frame sync, | |
211 | * frame sync starts one serial clock cycle earlier, | |
212 | * that is, together with the last bit of the previous | |
213 | * data word. | |
214 | */ | |
ef33bc32 | 215 | val_cr2 |= FSL_SAI_CR2_BCP; |
13cde090 XL |
216 | val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; |
217 | break; | |
218 | case SND_SOC_DAIFMT_LEFT_J: | |
a3f7dcc9 XL |
219 | /* |
220 | * Frame high, one word length for frame sync, | |
221 | * frame sync asserts with the first bit of the frame. | |
222 | */ | |
ef33bc32 | 223 | val_cr2 |= FSL_SAI_CR2_BCP; |
43550821 | 224 | break; |
a3f7dcc9 XL |
225 | case SND_SOC_DAIFMT_DSP_A: |
226 | /* | |
227 | * Frame high, 1clk before data, one bit for frame sync, | |
228 | * frame sync starts one serial clock cycle earlier, | |
229 | * that is, together with the last bit of the previous | |
230 | * data word. | |
231 | */ | |
ef33bc32 | 232 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
233 | val_cr4 |= FSL_SAI_CR4_FSE; |
234 | sai->is_dsp_mode = true; | |
235 | break; | |
236 | case SND_SOC_DAIFMT_DSP_B: | |
237 | /* | |
238 | * Frame high, one bit for frame sync, | |
239 | * frame sync asserts with the first bit of the frame. | |
240 | */ | |
ef33bc32 | 241 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
242 | sai->is_dsp_mode = true; |
243 | break; | |
13cde090 XL |
244 | case SND_SOC_DAIFMT_RIGHT_J: |
245 | /* To be done */ | |
43550821 XL |
246 | default: |
247 | return -EINVAL; | |
248 | } | |
249 | ||
13cde090 | 250 | /* DAI clock inversion */ |
43550821 XL |
251 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
252 | case SND_SOC_DAIFMT_IB_IF: | |
13cde090 XL |
253 | /* Invert both clocks */ |
254 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
255 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
256 | break; |
257 | case SND_SOC_DAIFMT_IB_NF: | |
13cde090 XL |
258 | /* Invert bit clock */ |
259 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
43550821 XL |
260 | break; |
261 | case SND_SOC_DAIFMT_NB_IF: | |
13cde090 XL |
262 | /* Invert frame clock */ |
263 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
264 | break; |
265 | case SND_SOC_DAIFMT_NB_NF: | |
13cde090 | 266 | /* Nothing to do for both normal cases */ |
43550821 XL |
267 | break; |
268 | default: | |
269 | return -EINVAL; | |
270 | } | |
271 | ||
13cde090 | 272 | /* DAI clock master masks */ |
43550821 XL |
273 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
274 | case SND_SOC_DAIFMT_CBS_CFS: | |
275 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; | |
276 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; | |
277 | break; | |
278 | case SND_SOC_DAIFMT_CBM_CFM: | |
c3ecef21 | 279 | sai->is_slave_mode = true; |
43550821 | 280 | break; |
13cde090 XL |
281 | case SND_SOC_DAIFMT_CBS_CFM: |
282 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; | |
13cde090 XL |
283 | break; |
284 | case SND_SOC_DAIFMT_CBM_CFS: | |
13cde090 | 285 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; |
c3ecef21 | 286 | sai->is_slave_mode = true; |
13cde090 | 287 | break; |
43550821 XL |
288 | default: |
289 | return -EINVAL; | |
290 | } | |
291 | ||
2a266f8b NC |
292 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), |
293 | FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); | |
294 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), | |
295 | FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | | |
296 | FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); | |
43550821 XL |
297 | |
298 | return 0; | |
299 | } | |
300 | ||
301 | static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
302 | { | |
4e3a99f5 | 303 | int ret; |
43550821 | 304 | |
43550821 XL |
305 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER); |
306 | if (ret) { | |
190af12d | 307 | dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); |
78957fc3 | 308 | return ret; |
43550821 XL |
309 | } |
310 | ||
311 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER); | |
78957fc3 | 312 | if (ret) |
190af12d | 313 | dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); |
43550821 | 314 | |
1fb2d9d7 | 315 | return ret; |
43550821 XL |
316 | } |
317 | ||
c3ecef21 ZW |
318 | static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) |
319 | { | |
320 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); | |
321 | unsigned long clk_rate; | |
322 | u32 savediv = 0, ratio, savesub = freq; | |
323 | u32 id; | |
324 | int ret = 0; | |
325 | ||
326 | /* Don't apply to slave mode */ | |
327 | if (sai->is_slave_mode) | |
328 | return 0; | |
329 | ||
330 | for (id = 0; id < FSL_SAI_MCLK_MAX; id++) { | |
331 | clk_rate = clk_get_rate(sai->mclk_clk[id]); | |
332 | if (!clk_rate) | |
333 | continue; | |
334 | ||
335 | ratio = clk_rate / freq; | |
336 | ||
337 | ret = clk_rate - ratio * freq; | |
338 | ||
339 | /* | |
340 | * Drop the source that can not be | |
341 | * divided into the required rate. | |
342 | */ | |
343 | if (ret != 0 && clk_rate / ret < 1000) | |
344 | continue; | |
345 | ||
346 | dev_dbg(dai->dev, | |
347 | "ratio %d for freq %dHz based on clock %ldHz\n", | |
348 | ratio, freq, clk_rate); | |
349 | ||
350 | if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512) | |
351 | ratio /= 2; | |
352 | else | |
353 | continue; | |
354 | ||
355 | if (ret < savesub) { | |
356 | savediv = ratio; | |
357 | sai->mclk_id[tx] = id; | |
358 | savesub = ret; | |
359 | } | |
360 | ||
361 | if (ret == 0) | |
362 | break; | |
363 | } | |
364 | ||
365 | if (savediv == 0) { | |
366 | dev_err(dai->dev, "failed to derive required %cx rate: %d\n", | |
367 | tx ? 'T' : 'R', freq); | |
368 | return -EINVAL; | |
369 | } | |
370 | ||
9cc58712 ZW |
371 | /* |
372 | * 1) For Asynchronous mode, we must set RCR2 register for capture, and | |
373 | * set TCR2 register for playback. | |
374 | * 2) For Tx sync with Rx clock, we must set RCR2 register for playback | |
375 | * and capture. | |
376 | * 3) For Rx sync with Tx clock, we must set TCR2 register for playback | |
377 | * and capture. | |
378 | * 4) For Tx and Rx are both Synchronous with another SAI, we just | |
379 | * ignore it. | |
380 | */ | |
381 | if ((sai->synchronous[TX] && !sai->synchronous[RX]) || | |
382 | (!tx && !sai->synchronous[RX])) { | |
c3ecef21 ZW |
383 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, |
384 | FSL_SAI_CR2_MSEL_MASK, | |
385 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
386 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, | |
387 | FSL_SAI_CR2_DIV_MASK, savediv - 1); | |
9cc58712 ZW |
388 | } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) || |
389 | (tx && !sai->synchronous[TX])) { | |
c3ecef21 ZW |
390 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, |
391 | FSL_SAI_CR2_MSEL_MASK, | |
392 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
393 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, | |
394 | FSL_SAI_CR2_DIV_MASK, savediv - 1); | |
395 | } | |
396 | ||
397 | dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", | |
398 | sai->mclk_id[tx], savediv, savesub); | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
43550821 XL |
403 | static int fsl_sai_hw_params(struct snd_pcm_substream *substream, |
404 | struct snd_pcm_hw_params *params, | |
405 | struct snd_soc_dai *cpu_dai) | |
406 | { | |
4e3a99f5 | 407 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b | 408 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
43550821 | 409 | unsigned int channels = params_channels(params); |
4ca73043 | 410 | u32 word_width = params_width(params); |
2a266f8b | 411 | u32 val_cr4 = 0, val_cr5 = 0; |
c1df2964 ZW |
412 | u32 slots = (channels == 1) ? 2 : channels; |
413 | u32 slot_width = word_width; | |
c3ecef21 ZW |
414 | int ret; |
415 | ||
c1df2964 ZW |
416 | if (sai->slots) |
417 | slots = sai->slots; | |
418 | ||
419 | if (sai->slot_width) | |
420 | slot_width = sai->slot_width; | |
421 | ||
c3ecef21 ZW |
422 | if (!sai->is_slave_mode) { |
423 | ret = fsl_sai_set_bclk(cpu_dai, tx, | |
c1df2964 | 424 | slots * slot_width * params_rate(params)); |
c3ecef21 ZW |
425 | if (ret) |
426 | return ret; | |
427 | ||
428 | /* Do not enable the clock if it is already enabled */ | |
429 | if (!(sai->mclk_streams & BIT(substream->stream))) { | |
430 | ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); | |
431 | if (ret) | |
432 | return ret; | |
433 | ||
434 | sai->mclk_streams |= BIT(substream->stream); | |
435 | } | |
c3ecef21 | 436 | } |
43550821 | 437 | |
a3f7dcc9 | 438 | if (!sai->is_dsp_mode) |
c1df2964 | 439 | val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); |
a3f7dcc9 | 440 | |
c1df2964 ZW |
441 | val_cr5 |= FSL_SAI_CR5_WNW(slot_width); |
442 | val_cr5 |= FSL_SAI_CR5_W0W(slot_width); | |
43550821 | 443 | |
eadb0019 | 444 | if (sai->is_lsb_first) |
43550821 | 445 | val_cr5 |= FSL_SAI_CR5_FBT(0); |
72aa62be XL |
446 | else |
447 | val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); | |
43550821 | 448 | |
c1df2964 | 449 | val_cr4 |= FSL_SAI_CR4_FRSZ(slots); |
43550821 | 450 | |
51659ca0 ZW |
451 | /* |
452 | * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will | |
453 | * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), | |
454 | * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync | |
455 | * error. | |
456 | */ | |
457 | ||
458 | if (!sai->is_slave_mode) { | |
459 | if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { | |
460 | regmap_update_bits(sai->regmap, FSL_SAI_TCR4, | |
461 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
462 | val_cr4); | |
463 | regmap_update_bits(sai->regmap, FSL_SAI_TCR5, | |
464 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
465 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
466 | regmap_write(sai->regmap, FSL_SAI_TMR, | |
467 | ~0UL - ((1 << channels) - 1)); | |
468 | } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { | |
469 | regmap_update_bits(sai->regmap, FSL_SAI_RCR4, | |
470 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
471 | val_cr4); | |
472 | regmap_update_bits(sai->regmap, FSL_SAI_RCR5, | |
473 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
474 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
475 | regmap_write(sai->regmap, FSL_SAI_RMR, | |
476 | ~0UL - ((1 << channels) - 1)); | |
477 | } | |
478 | } | |
43550821 | 479 | |
2a266f8b NC |
480 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), |
481 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
482 | val_cr4); | |
483 | regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx), | |
484 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
485 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
486 | regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1)); | |
43550821 XL |
487 | |
488 | return 0; | |
489 | } | |
490 | ||
c3ecef21 ZW |
491 | static int fsl_sai_hw_free(struct snd_pcm_substream *substream, |
492 | struct snd_soc_dai *cpu_dai) | |
493 | { | |
494 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
495 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
496 | ||
497 | if (!sai->is_slave_mode && | |
498 | sai->mclk_streams & BIT(substream->stream)) { | |
499 | clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); | |
500 | sai->mclk_streams &= ~BIT(substream->stream); | |
501 | } | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | ||
43550821 XL |
507 | static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, |
508 | struct snd_soc_dai *cpu_dai) | |
509 | { | |
510 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
e6b39846 | 511 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
c44b56af | 512 | u32 xcsr, count = 100; |
496a39d9 | 513 | |
a3f7dcc9 | 514 | /* |
08fdf65e NC |
515 | * Asynchronous mode: Clear SYNC for both Tx and Rx. |
516 | * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. | |
517 | * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. | |
a3f7dcc9 | 518 | */ |
3cc7780b SA |
519 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, |
520 | sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); | |
78957fc3 | 521 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC, |
08fdf65e | 522 | sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); |
43550821 | 523 | |
a3f7dcc9 XL |
524 | /* |
525 | * It is recommended that the transmitter is the last enabled | |
526 | * and the first disabled. | |
527 | */ | |
43550821 XL |
528 | switch (cmd) { |
529 | case SNDRV_PCM_TRIGGER_START: | |
530 | case SNDRV_PCM_TRIGGER_RESUME: | |
531 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
a3fdc674 NC |
532 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
533 | FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); | |
534 | ||
f4075a8f NC |
535 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, |
536 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); | |
537 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, | |
538 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); | |
e5d0fa9c | 539 | |
8abba5d6 NC |
540 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
541 | FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); | |
43550821 | 542 | break; |
43550821 XL |
543 | case SNDRV_PCM_TRIGGER_STOP: |
544 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
545 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
e6b39846 NC |
546 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
547 | FSL_SAI_CSR_FRDE, 0); | |
8abba5d6 NC |
548 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
549 | FSL_SAI_CSR_xIE_MASK, 0); | |
e6b39846 | 550 | |
f84526cf | 551 | /* Check if the opposite FRDE is also disabled */ |
f4075a8f NC |
552 | regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr); |
553 | if (!(xcsr & FSL_SAI_CSR_FRDE)) { | |
eff952b7 | 554 | /* Disable both directions and reset their FIFOs */ |
e6b39846 | 555 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, |
c44b56af | 556 | FSL_SAI_CSR_TERE, 0); |
e6b39846 | 557 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, |
c44b56af NC |
558 | FSL_SAI_CSR_TERE, 0); |
559 | ||
560 | /* TERE will remain set till the end of current frame */ | |
561 | do { | |
562 | udelay(10); | |
563 | regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr); | |
564 | } while (--count && xcsr & FSL_SAI_CSR_TERE); | |
565 | ||
566 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, | |
567 | FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); | |
568 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, | |
569 | FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); | |
3e3f8bd5 ZW |
570 | |
571 | /* | |
572 | * For sai master mode, after several open/close sai, | |
573 | * there will be no frame clock, and can't recover | |
574 | * anymore. Add software reset to fix this issue. | |
575 | * This is a hardware bug, and will be fix in the | |
576 | * next sai version. | |
577 | */ | |
578 | if (!sai->is_slave_mode) { | |
579 | /* Software Reset for both Tx and Rx */ | |
580 | regmap_write(sai->regmap, | |
581 | FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
582 | regmap_write(sai->regmap, | |
583 | FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
584 | /* Clear SR bit to finish the reset */ | |
585 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); | |
586 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
587 | } | |
43550821 | 588 | } |
43550821 XL |
589 | break; |
590 | default: | |
591 | return -EINVAL; | |
592 | } | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | static int fsl_sai_startup(struct snd_pcm_substream *substream, | |
598 | struct snd_soc_dai *cpu_dai) | |
599 | { | |
43550821 | 600 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b | 601 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
ca3e35c7 | 602 | struct device *dev = &sai->pdev->dev; |
ca3e35c7 NC |
603 | int ret; |
604 | ||
605 | ret = clk_prepare_enable(sai->bus_clk); | |
606 | if (ret) { | |
607 | dev_err(dev, "failed to enable bus clock: %d\n", ret); | |
608 | return ret; | |
609 | } | |
43550821 | 610 | |
2a266f8b | 611 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, |
78957fc3 XL |
612 | FSL_SAI_CR3_TRCE); |
613 | ||
c5f4823b ZW |
614 | ret = snd_pcm_hw_constraint_list(substream->runtime, 0, |
615 | SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); | |
616 | ||
617 | return ret; | |
43550821 XL |
618 | } |
619 | ||
620 | static void fsl_sai_shutdown(struct snd_pcm_substream *substream, | |
621 | struct snd_soc_dai *cpu_dai) | |
622 | { | |
623 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
2a266f8b | 624 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
43550821 | 625 | |
2a266f8b | 626 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0); |
ca3e35c7 NC |
627 | |
628 | clk_disable_unprepare(sai->bus_clk); | |
43550821 XL |
629 | } |
630 | ||
631 | static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { | |
632 | .set_sysclk = fsl_sai_set_dai_sysclk, | |
633 | .set_fmt = fsl_sai_set_dai_fmt, | |
c1df2964 | 634 | .set_tdm_slot = fsl_sai_set_dai_tdm_slot, |
43550821 | 635 | .hw_params = fsl_sai_hw_params, |
c3ecef21 | 636 | .hw_free = fsl_sai_hw_free, |
43550821 XL |
637 | .trigger = fsl_sai_trigger, |
638 | .startup = fsl_sai_startup, | |
639 | .shutdown = fsl_sai_shutdown, | |
640 | }; | |
641 | ||
642 | static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) | |
643 | { | |
644 | struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); | |
e6dc12d7 | 645 | |
376d1a92 NC |
646 | /* Software Reset for both Tx and Rx */ |
647 | regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
648 | regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
649 | /* Clear SR bit to finish the reset */ | |
650 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); | |
651 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
652 | ||
78957fc3 XL |
653 | regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK, |
654 | FSL_SAI_MAXBURST_TX * 2); | |
655 | regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK, | |
656 | FSL_SAI_MAXBURST_RX - 1); | |
43550821 | 657 | |
dd9f4060 XL |
658 | snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, |
659 | &sai->dma_params_rx); | |
43550821 XL |
660 | |
661 | snd_soc_dai_set_drvdata(cpu_dai, sai); | |
662 | ||
663 | return 0; | |
664 | } | |
665 | ||
43550821 XL |
666 | static struct snd_soc_dai_driver fsl_sai_dai = { |
667 | .probe = fsl_sai_dai_probe, | |
43550821 | 668 | .playback = { |
20d5b76f | 669 | .stream_name = "CPU-Playback", |
43550821 XL |
670 | .channels_min = 1, |
671 | .channels_max = 2, | |
c5f4823b ZW |
672 | .rate_min = 8000, |
673 | .rate_max = 192000, | |
674 | .rates = SNDRV_PCM_RATE_KNOT, | |
43550821 XL |
675 | .formats = FSL_SAI_FORMATS, |
676 | }, | |
677 | .capture = { | |
20d5b76f | 678 | .stream_name = "CPU-Capture", |
43550821 XL |
679 | .channels_min = 1, |
680 | .channels_max = 2, | |
c5f4823b ZW |
681 | .rate_min = 8000, |
682 | .rate_max = 192000, | |
683 | .rates = SNDRV_PCM_RATE_KNOT, | |
43550821 XL |
684 | .formats = FSL_SAI_FORMATS, |
685 | }, | |
686 | .ops = &fsl_sai_pcm_dai_ops, | |
687 | }; | |
688 | ||
689 | static const struct snd_soc_component_driver fsl_component = { | |
690 | .name = "fsl-sai", | |
691 | }; | |
692 | ||
3f6f5b0c ZW |
693 | static struct reg_default fsl_sai_reg_defaults[] = { |
694 | {FSL_SAI_TCR1, 0}, | |
695 | {FSL_SAI_TCR2, 0}, | |
696 | {FSL_SAI_TCR3, 0}, | |
697 | {FSL_SAI_TCR4, 0}, | |
698 | {FSL_SAI_TCR5, 0}, | |
699 | {FSL_SAI_TDR, 0}, | |
700 | {FSL_SAI_TMR, 0}, | |
701 | {FSL_SAI_RCR1, 0}, | |
702 | {FSL_SAI_RCR2, 0}, | |
703 | {FSL_SAI_RCR3, 0}, | |
704 | {FSL_SAI_RCR4, 0}, | |
705 | {FSL_SAI_RCR5, 0}, | |
706 | {FSL_SAI_RMR, 0}, | |
707 | }; | |
708 | ||
78957fc3 XL |
709 | static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) |
710 | { | |
711 | switch (reg) { | |
712 | case FSL_SAI_TCSR: | |
713 | case FSL_SAI_TCR1: | |
714 | case FSL_SAI_TCR2: | |
715 | case FSL_SAI_TCR3: | |
716 | case FSL_SAI_TCR4: | |
717 | case FSL_SAI_TCR5: | |
718 | case FSL_SAI_TFR: | |
719 | case FSL_SAI_TMR: | |
720 | case FSL_SAI_RCSR: | |
721 | case FSL_SAI_RCR1: | |
722 | case FSL_SAI_RCR2: | |
723 | case FSL_SAI_RCR3: | |
724 | case FSL_SAI_RCR4: | |
725 | case FSL_SAI_RCR5: | |
726 | case FSL_SAI_RDR: | |
727 | case FSL_SAI_RFR: | |
728 | case FSL_SAI_RMR: | |
729 | return true; | |
730 | default: | |
731 | return false; | |
732 | } | |
733 | } | |
734 | ||
735 | static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) | |
736 | { | |
737 | switch (reg) { | |
1fde5e83 ZW |
738 | case FSL_SAI_TCSR: |
739 | case FSL_SAI_RCSR: | |
78957fc3 XL |
740 | case FSL_SAI_TFR: |
741 | case FSL_SAI_RFR: | |
78957fc3 XL |
742 | case FSL_SAI_RDR: |
743 | return true; | |
744 | default: | |
745 | return false; | |
746 | } | |
78957fc3 XL |
747 | } |
748 | ||
749 | static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) | |
750 | { | |
751 | switch (reg) { | |
752 | case FSL_SAI_TCSR: | |
753 | case FSL_SAI_TCR1: | |
754 | case FSL_SAI_TCR2: | |
755 | case FSL_SAI_TCR3: | |
756 | case FSL_SAI_TCR4: | |
757 | case FSL_SAI_TCR5: | |
758 | case FSL_SAI_TDR: | |
759 | case FSL_SAI_TMR: | |
760 | case FSL_SAI_RCSR: | |
761 | case FSL_SAI_RCR1: | |
762 | case FSL_SAI_RCR2: | |
763 | case FSL_SAI_RCR3: | |
764 | case FSL_SAI_RCR4: | |
765 | case FSL_SAI_RCR5: | |
766 | case FSL_SAI_RMR: | |
767 | return true; | |
768 | default: | |
769 | return false; | |
770 | } | |
771 | } | |
772 | ||
014fd22e | 773 | static const struct regmap_config fsl_sai_regmap_config = { |
78957fc3 XL |
774 | .reg_bits = 32, |
775 | .reg_stride = 4, | |
776 | .val_bits = 32, | |
777 | ||
778 | .max_register = FSL_SAI_RMR, | |
3f6f5b0c ZW |
779 | .reg_defaults = fsl_sai_reg_defaults, |
780 | .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults), | |
78957fc3 XL |
781 | .readable_reg = fsl_sai_readable_reg, |
782 | .volatile_reg = fsl_sai_volatile_reg, | |
783 | .writeable_reg = fsl_sai_writeable_reg, | |
1fde5e83 | 784 | .cache_type = REGCACHE_FLAT, |
78957fc3 XL |
785 | }; |
786 | ||
43550821 XL |
787 | static int fsl_sai_probe(struct platform_device *pdev) |
788 | { | |
4e3a99f5 | 789 | struct device_node *np = pdev->dev.of_node; |
43550821 | 790 | struct fsl_sai *sai; |
4d245850 | 791 | struct regmap *gpr; |
43550821 | 792 | struct resource *res; |
78957fc3 | 793 | void __iomem *base; |
ca3e35c7 NC |
794 | char tmp[8]; |
795 | int irq, ret, i; | |
4d245850 | 796 | int index; |
43550821 XL |
797 | |
798 | sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); | |
799 | if (!sai) | |
800 | return -ENOMEM; | |
801 | ||
e2681a1b NC |
802 | sai->pdev = pdev; |
803 | ||
1593af62 FE |
804 | if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai") || |
805 | of_device_is_compatible(pdev->dev.of_node, "fsl,imx6ul-sai")) | |
c7540644 NC |
806 | sai->sai_on_imx = true; |
807 | ||
eadb0019 | 808 | sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); |
78957fc3 | 809 | |
43550821 | 810 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
78957fc3 XL |
811 | base = devm_ioremap_resource(&pdev->dev, res); |
812 | if (IS_ERR(base)) | |
813 | return PTR_ERR(base); | |
814 | ||
815 | sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, | |
ca3e35c7 NC |
816 | "bus", base, &fsl_sai_regmap_config); |
817 | ||
818 | /* Compatible with old DTB cases */ | |
819 | if (IS_ERR(sai->regmap)) | |
820 | sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, | |
821 | "sai", base, &fsl_sai_regmap_config); | |
78957fc3 XL |
822 | if (IS_ERR(sai->regmap)) { |
823 | dev_err(&pdev->dev, "regmap init failed\n"); | |
824 | return PTR_ERR(sai->regmap); | |
43550821 XL |
825 | } |
826 | ||
ca3e35c7 NC |
827 | /* No error out for old DTB cases but only mark the clock NULL */ |
828 | sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); | |
829 | if (IS_ERR(sai->bus_clk)) { | |
830 | dev_err(&pdev->dev, "failed to get bus clock: %ld\n", | |
831 | PTR_ERR(sai->bus_clk)); | |
832 | sai->bus_clk = NULL; | |
833 | } | |
834 | ||
c3ecef21 ZW |
835 | sai->mclk_clk[0] = sai->bus_clk; |
836 | for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { | |
837 | sprintf(tmp, "mclk%d", i); | |
ca3e35c7 NC |
838 | sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); |
839 | if (IS_ERR(sai->mclk_clk[i])) { | |
840 | dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", | |
841 | i + 1, PTR_ERR(sai->mclk_clk[i])); | |
842 | sai->mclk_clk[i] = NULL; | |
843 | } | |
844 | } | |
845 | ||
e2681a1b NC |
846 | irq = platform_get_irq(pdev, 0); |
847 | if (irq < 0) { | |
0954237f | 848 | dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); |
e2681a1b NC |
849 | return irq; |
850 | } | |
851 | ||
852 | ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai); | |
853 | if (ret) { | |
854 | dev_err(&pdev->dev, "failed to claim irq %u\n", irq); | |
855 | return ret; | |
856 | } | |
857 | ||
08fdf65e NC |
858 | /* Sync Tx with Rx as default by following old DT binding */ |
859 | sai->synchronous[RX] = true; | |
860 | sai->synchronous[TX] = false; | |
861 | fsl_sai_dai.symmetric_rates = 1; | |
862 | fsl_sai_dai.symmetric_channels = 1; | |
863 | fsl_sai_dai.symmetric_samplebits = 1; | |
864 | ||
ce7344a4 NC |
865 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && |
866 | of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
867 | /* error out if both synchronous and asynchronous are present */ | |
868 | dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); | |
869 | return -EINVAL; | |
870 | } | |
871 | ||
08fdf65e NC |
872 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { |
873 | /* Sync Rx with Tx */ | |
874 | sai->synchronous[RX] = false; | |
875 | sai->synchronous[TX] = true; | |
876 | } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
877 | /* Discard all settings for asynchronous mode */ | |
878 | sai->synchronous[RX] = false; | |
879 | sai->synchronous[TX] = false; | |
880 | fsl_sai_dai.symmetric_rates = 0; | |
881 | fsl_sai_dai.symmetric_channels = 0; | |
882 | fsl_sai_dai.symmetric_samplebits = 0; | |
883 | } | |
884 | ||
4d245850 FE |
885 | if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && |
886 | of_device_is_compatible(pdev->dev.of_node, "fsl,imx6ul-sai")) { | |
887 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); | |
888 | if (IS_ERR(gpr)) { | |
889 | dev_err(&pdev->dev, "cannot find iomuxc registers\n"); | |
890 | return PTR_ERR(gpr); | |
891 | } | |
892 | ||
893 | index = of_alias_get_id(np, "sai"); | |
894 | if (index < 0) | |
895 | return index; | |
896 | ||
897 | regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), | |
898 | MCLK_DIR(index)); | |
899 | } | |
900 | ||
43550821 XL |
901 | sai->dma_params_rx.addr = res->start + FSL_SAI_RDR; |
902 | sai->dma_params_tx.addr = res->start + FSL_SAI_TDR; | |
903 | sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; | |
904 | sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; | |
905 | ||
43550821 XL |
906 | platform_set_drvdata(pdev, sai); |
907 | ||
908 | ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, | |
909 | &fsl_sai_dai, 1); | |
910 | if (ret) | |
911 | return ret; | |
912 | ||
c7540644 | 913 | if (sai->sai_on_imx) |
0d69e0dd | 914 | return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE); |
c7540644 | 915 | else |
acde50a7 | 916 | return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); |
43550821 XL |
917 | } |
918 | ||
919 | static const struct of_device_id fsl_sai_ids[] = { | |
920 | { .compatible = "fsl,vf610-sai", }, | |
c7540644 | 921 | { .compatible = "fsl,imx6sx-sai", }, |
1593af62 | 922 | { .compatible = "fsl,imx6ul-sai", }, |
43550821 XL |
923 | { /* sentinel */ } |
924 | }; | |
c759241f | 925 | MODULE_DEVICE_TABLE(of, fsl_sai_ids); |
43550821 | 926 | |
739146b6 | 927 | #ifdef CONFIG_PM_SLEEP |
1fde5e83 ZW |
928 | static int fsl_sai_suspend(struct device *dev) |
929 | { | |
930 | struct fsl_sai *sai = dev_get_drvdata(dev); | |
931 | ||
932 | regcache_cache_only(sai->regmap, true); | |
933 | regcache_mark_dirty(sai->regmap); | |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
938 | static int fsl_sai_resume(struct device *dev) | |
939 | { | |
940 | struct fsl_sai *sai = dev_get_drvdata(dev); | |
941 | ||
942 | regcache_cache_only(sai->regmap, false); | |
943 | regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
944 | regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
512feb4e | 945 | usleep_range(1000, 2000); |
1fde5e83 ZW |
946 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); |
947 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
948 | return regcache_sync(sai->regmap); | |
949 | } | |
950 | #endif /* CONFIG_PM_SLEEP */ | |
951 | ||
952 | static const struct dev_pm_ops fsl_sai_pm_ops = { | |
953 | SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume) | |
954 | }; | |
955 | ||
43550821 XL |
956 | static struct platform_driver fsl_sai_driver = { |
957 | .probe = fsl_sai_probe, | |
43550821 XL |
958 | .driver = { |
959 | .name = "fsl-sai", | |
1fde5e83 | 960 | .pm = &fsl_sai_pm_ops, |
43550821 XL |
961 | .of_match_table = fsl_sai_ids, |
962 | }, | |
963 | }; | |
964 | module_platform_driver(fsl_sai_driver); | |
965 | ||
966 | MODULE_DESCRIPTION("Freescale Soc SAI Interface"); | |
967 | MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); | |
968 | MODULE_ALIAS("platform:fsl-sai"); | |
969 | MODULE_LICENSE("GPL"); |