projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mason...
[deliverable/linux.git] / sound / soc / fsl / fsl_sai.c
CommitLineData
43550821
XL		 1/*
2 * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
3 *
c3ecef21 4 * Copyright 2012-2015 Freescale Semiconductor, Inc.
43550821
XL		 5 *
6 * This program is free software, you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation, either version 2 of the License, or(at your
9 * option) any later version.
10 *
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dmaengine.h>
16#include <linux/module.h>
17#include <linux/of_address.h>
78957fc3 18#include <linux/regmap.h>
43550821
XL		 19#include <linux/slab.h>
20#include <sound/core.h>
21#include <sound/dmaengine_pcm.h>
22#include <sound/pcm_params.h>
23
24#include "fsl_sai.h"
c7540644 25#include "imx-pcm.h"
43550821 26
e2681a1b
NC		 27#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
28 FSL_SAI_CSR_FEIE)
29
c5f4823b
ZW		 30static u32 fsl_sai_rates[] = {
31 8000, 11025, 12000, 16000, 22050,
32 24000, 32000, 44100, 48000, 64000,
33 88200, 96000, 176400, 192000
34};
35
36static struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
37 .count = ARRAY_SIZE(fsl_sai_rates),
38 .list = fsl_sai_rates,
39};
40
e2681a1b
NC		 41static irqreturn_t fsl_sai_isr(int irq, void *devid)
42{
43 struct fsl_sai *sai = (struct fsl_sai *)devid;
44 struct device *dev = &sai->pdev->dev;
413312aa
NC		 45 u32 flags, xcsr, mask;
46 bool irq_none = true;
47
48 /*
49 * Both IRQ status bits and IRQ mask bits are in the xCSR but
50 * different shifts. And we here create a mask only for those
51 * IRQs that we activated.
52 */
e2681a1b
NC		 53 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
54
55 /* Tx IRQ */
56 regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
413312aa
NC		 57 flags = xcsr & mask;
58
59 if (flags)
60 irq_none = false;
61 else
62 goto irq_rx;
e2681a1b 63
413312aa 64 if (flags & FSL_SAI_CSR_WSF)
e2681a1b
NC		 65 dev_dbg(dev, "isr: Start of Tx word detected\n");
66
413312aa 67 if (flags & FSL_SAI_CSR_SEF)
e2681a1b
NC		 68 dev_warn(dev, "isr: Tx Frame sync error detected\n");
69
413312aa 70 if (flags & FSL_SAI_CSR_FEF) {
e2681a1b
NC		 71 dev_warn(dev, "isr: Transmit underrun detected\n");
72 /* FIFO reset for safety */
73 xcsr |= FSL_SAI_CSR_FR;
74 }
75
413312aa 76 if (flags & FSL_SAI_CSR_FWF)
e2681a1b
NC		 77 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
78
413312aa 79 if (flags & FSL_SAI_CSR_FRF)
e2681a1b
NC		 80 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
81
413312aa
NC		 82 flags &= FSL_SAI_CSR_xF_W_MASK;
83 xcsr &= ~FSL_SAI_CSR_xF_MASK;
84
85 if (flags)
86 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
e2681a1b 87
413312aa 88irq_rx:
e2681a1b
NC		 89 /* Rx IRQ */
90 regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
413312aa 91 flags = xcsr & mask;
e2681a1b 92
413312aa
NC		 93 if (flags)
94 irq_none = false;
95 else
96 goto out;
97
98 if (flags & FSL_SAI_CSR_WSF)
e2681a1b
NC		 99 dev_dbg(dev, "isr: Start of Rx word detected\n");
100
413312aa 101 if (flags & FSL_SAI_CSR_SEF)
e2681a1b
NC		 102 dev_warn(dev, "isr: Rx Frame sync error detected\n");
103
413312aa 104 if (flags & FSL_SAI_CSR_FEF) {
e2681a1b
NC		 105 dev_warn(dev, "isr: Receive overflow detected\n");
106 /* FIFO reset for safety */
107 xcsr |= FSL_SAI_CSR_FR;
108 }
109
413312aa 110 if (flags & FSL_SAI_CSR_FWF)
e2681a1b
NC		 111 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
112
413312aa 113 if (flags & FSL_SAI_CSR_FRF)
e2681a1b
NC		 114 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
115
413312aa
NC		 116 flags &= FSL_SAI_CSR_xF_W_MASK;
117 xcsr &= ~FSL_SAI_CSR_xF_MASK;
e2681a1b 118
413312aa 119 if (flags)
4800f88b 120 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
413312aa
NC		 121
122out:
123 if (irq_none)
124 return IRQ_NONE;
125 else
126 return IRQ_HANDLED;
e2681a1b
NC		 127}
128
43550821
XL		 129static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
130 int clk_id, unsigned int freq, int fsl_dir)
131{
43550821 132 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
2a266f8b
NC		 133 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
134 u32 val_cr2 = 0;
633ff8f8 135
43550821
XL		 136 switch (clk_id) {
137 case FSL_SAI_CLK_BUS:
43550821
XL		 138 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
139 break;
140 case FSL_SAI_CLK_MAST1:
43550821
XL		 141 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
142 break;
143 case FSL_SAI_CLK_MAST2:
43550821
XL		 144 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
145 break;
146 case FSL_SAI_CLK_MAST3:
43550821
XL		 147 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
148 break;
149 default:
150 return -EINVAL;
151 }
633ff8f8 152
2a266f8b
NC		 153 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
154 FSL_SAI_CR2_MSEL_MASK, val_cr2);
43550821
XL		 155
156 return 0;
157}
158
159static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
160 int clk_id, unsigned int freq, int dir)
161{
4e3a99f5 162 int ret;
43550821
XL		 163
164 if (dir == SND_SOC_CLOCK_IN)
165 return 0;
166
43550821
XL		 167 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
168 FSL_FMT_TRANSMITTER);
169 if (ret) {
190af12d 170 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
78957fc3 171 return ret;
43550821
XL		 172 }
173
174 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
175 FSL_FMT_RECEIVER);
78957fc3 176 if (ret)
190af12d 177 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
43550821 178
1fb2d9d7 179 return ret;
43550821
XL		 180}
181
182static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
183 unsigned int fmt, int fsl_dir)
184{
43550821 185 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
2a266f8b
NC		 186 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
187 u32 val_cr2 = 0, val_cr4 = 0;
43550821 188
eadb0019 189 if (!sai->is_lsb_first)
72aa62be 190 val_cr4 |= FSL_SAI_CR4_MF;
43550821 191
13cde090 192 /* DAI mode */
43550821
XL		 193 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
194 case SND_SOC_DAIFMT_I2S:
a3f7dcc9
XL		 195 /*
196 * Frame low, 1clk before data, one word length for frame sync,
197 * frame sync starts one serial clock cycle earlier,
198 * that is, together with the last bit of the previous
199 * data word.
200 */
ef33bc32 201 val_cr2 |= FSL_SAI_CR2_BCP;
13cde090
XL		 202 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
203 break;
204 case SND_SOC_DAIFMT_LEFT_J:
a3f7dcc9
XL		 205 /*
206 * Frame high, one word length for frame sync,
207 * frame sync asserts with the first bit of the frame.
208 */
ef33bc32 209 val_cr2 |= FSL_SAI_CR2_BCP;
43550821 210 break;
a3f7dcc9
XL		 211 case SND_SOC_DAIFMT_DSP_A:
212 /*
213 * Frame high, 1clk before data, one bit for frame sync,
214 * frame sync starts one serial clock cycle earlier,
215 * that is, together with the last bit of the previous
216 * data word.
217 */
ef33bc32 218 val_cr2 |= FSL_SAI_CR2_BCP;
a3f7dcc9
XL		 219 val_cr4 |= FSL_SAI_CR4_FSE;
220 sai->is_dsp_mode = true;
221 break;
222 case SND_SOC_DAIFMT_DSP_B:
223 /*
224 * Frame high, one bit for frame sync,
225 * frame sync asserts with the first bit of the frame.
226 */
ef33bc32 227 val_cr2 |= FSL_SAI_CR2_BCP;
a3f7dcc9
XL		 228 sai->is_dsp_mode = true;
229 break;
13cde090
XL		 230 case SND_SOC_DAIFMT_RIGHT_J:
231 /* To be done */
43550821
XL		 232 default:
233 return -EINVAL;
234 }
235
13cde090 236 /* DAI clock inversion */
43550821
XL		 237 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
238 case SND_SOC_DAIFMT_IB_IF:
13cde090
XL		 239 /* Invert both clocks */
240 val_cr2 ^= FSL_SAI_CR2_BCP;
241 val_cr4 ^= FSL_SAI_CR4_FSP;
43550821
XL		 242 break;
243 case SND_SOC_DAIFMT_IB_NF:
13cde090
XL		 244 /* Invert bit clock */
245 val_cr2 ^= FSL_SAI_CR2_BCP;
43550821
XL		 246 break;
247 case SND_SOC_DAIFMT_NB_IF:
13cde090
XL		 248 /* Invert frame clock */
249 val_cr4 ^= FSL_SAI_CR4_FSP;
43550821
XL		 250 break;
251 case SND_SOC_DAIFMT_NB_NF:
13cde090 252 /* Nothing to do for both normal cases */
43550821
XL		 253 break;
254 default:
255 return -EINVAL;
256 }
257
13cde090 258 /* DAI clock master masks */
43550821
XL		 259 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
260 case SND_SOC_DAIFMT_CBS_CFS:
261 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
262 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
263 break;
264 case SND_SOC_DAIFMT_CBM_CFM:
c3ecef21 265 sai->is_slave_mode = true;
43550821 266 break;
13cde090
XL		 267 case SND_SOC_DAIFMT_CBS_CFM:
268 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
13cde090
XL		 269 break;
270 case SND_SOC_DAIFMT_CBM_CFS:
13cde090 271 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
c3ecef21 272 sai->is_slave_mode = true;
13cde090 273 break;
43550821
XL		 274 default:
275 return -EINVAL;
276 }
277
2a266f8b
NC		 278 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
279 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
280 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
281 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
282 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
43550821
XL		 283
284 return 0;
285}
286
287static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
288{
4e3a99f5 289 int ret;
43550821 290
43550821
XL		 291 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
292 if (ret) {
190af12d 293 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
78957fc3 294 return ret;
43550821
XL		 295 }
296
297 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
78957fc3 298 if (ret)
190af12d 299 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
43550821 300
1fb2d9d7 301 return ret;
43550821
XL		 302}
303
c3ecef21
ZW		 304static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
305{
306 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
307 unsigned long clk_rate;
308 u32 savediv = 0, ratio, savesub = freq;
309 u32 id;
310 int ret = 0;
311
312 /* Don't apply to slave mode */
313 if (sai->is_slave_mode)
314 return 0;
315
316 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
317 clk_rate = clk_get_rate(sai->mclk_clk[id]);
318 if (!clk_rate)
319 continue;
320
321 ratio = clk_rate / freq;
322
323 ret = clk_rate - ratio * freq;
324
325 /*
326 * Drop the source that can not be
327 * divided into the required rate.
328 */
329 if (ret != 0 && clk_rate / ret < 1000)
330 continue;
331
332 dev_dbg(dai->dev,
333 "ratio %d for freq %dHz based on clock %ldHz\n",
334 ratio, freq, clk_rate);
335
336 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
337 ratio /= 2;
338 else
339 continue;
340
341 if (ret < savesub) {
342 savediv = ratio;
343 sai->mclk_id[tx] = id;
344 savesub = ret;
345 }
346
347 if (ret == 0)
348 break;
349 }
350
351 if (savediv == 0) {
352 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
353 tx ? 'T' : 'R', freq);
354 return -EINVAL;
355 }
356
357 if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) {
358 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
359 FSL_SAI_CR2_MSEL_MASK,
360 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
361 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
362 FSL_SAI_CR2_DIV_MASK, savediv - 1);
363 } else {
364 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
365 FSL_SAI_CR2_MSEL_MASK,
366 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
367 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
368 FSL_SAI_CR2_DIV_MASK, savediv - 1);
369 }
370
371 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
372 sai->mclk_id[tx], savediv, savesub);
373
374 return 0;
375}
376
43550821
XL		 377static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
378 struct snd_pcm_hw_params *params,
379 struct snd_soc_dai *cpu_dai)
380{
4e3a99f5 381 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
2a266f8b 382 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
43550821 383 unsigned int channels = params_channels(params);
1d700309 384 u32 word_width = snd_pcm_format_width(params_format(params));
2a266f8b 385 u32 val_cr4 = 0, val_cr5 = 0;
c3ecef21
ZW		 386 int ret;
387
388 if (!sai->is_slave_mode) {
389 ret = fsl_sai_set_bclk(cpu_dai, tx,
390 2 * word_width * params_rate(params));
391 if (ret)
392 return ret;
393
394 /* Do not enable the clock if it is already enabled */
395 if (!(sai->mclk_streams & BIT(substream->stream))) {
396 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
397 if (ret)
398 return ret;
399
400 sai->mclk_streams |= BIT(substream->stream);
401 }
402
403 }
43550821 404
a3f7dcc9
XL		 405 if (!sai->is_dsp_mode)
406 val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
407
43550821
XL		 408 val_cr5 |= FSL_SAI_CR5_WNW(word_width);
409 val_cr5 |= FSL_SAI_CR5_W0W(word_width);
410
eadb0019 411 if (sai->is_lsb_first)
43550821 412 val_cr5 |= FSL_SAI_CR5_FBT(0);
72aa62be
XL		 413 else
414 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
43550821
XL		 415
416 val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
43550821 417
2a266f8b
NC		 418 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
419 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
420 val_cr4);
421 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
422 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
423 FSL_SAI_CR5_FBT_MASK, val_cr5);
424 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
43550821
XL		 425
426 return 0;
427}
428
c3ecef21
ZW		 429static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
430 struct snd_soc_dai *cpu_dai)
431{
432 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
433 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
434
435 if (!sai->is_slave_mode &&
436 sai->mclk_streams & BIT(substream->stream)) {
437 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
438 sai->mclk_streams &= ~BIT(substream->stream);
439 }
440
441 return 0;
442}
443
444
43550821
XL		 445static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
446 struct snd_soc_dai *cpu_dai)
447{
448 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
e6b39846 449 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
c44b56af 450 u32 xcsr, count = 100;
496a39d9 451
a3f7dcc9 452 /*
08fdf65e
NC		 453 * Asynchronous mode: Clear SYNC for both Tx and Rx.
454 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
455 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
a3f7dcc9 456 */
855675f6 457 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, 0);
78957fc3 458 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
08fdf65e 459 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
43550821 460
a3f7dcc9
XL		 461 /*
462 * It is recommended that the transmitter is the last enabled
463 * and the first disabled.
464 */
43550821
XL		 465 switch (cmd) {
466 case SNDRV_PCM_TRIGGER_START:
467 case SNDRV_PCM_TRIGGER_RESUME:
468 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
a3fdc674
NC		 469 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
470 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
471
f4075a8f
NC		 472 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
473 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
474 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
475 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
e5d0fa9c 476
8abba5d6
NC		 477 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
478 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
43550821 479 break;
43550821
XL		 480 case SNDRV_PCM_TRIGGER_STOP:
481 case SNDRV_PCM_TRIGGER_SUSPEND:
482 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
e6b39846
NC		 483 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
484 FSL_SAI_CSR_FRDE, 0);
8abba5d6
NC		 485 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
486 FSL_SAI_CSR_xIE_MASK, 0);
e6b39846 487
f84526cf 488 /* Check if the opposite FRDE is also disabled */
f4075a8f
NC		 489 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
490 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
eff952b7 491 /* Disable both directions and reset their FIFOs */
e6b39846 492 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
c44b56af 493 FSL_SAI_CSR_TERE, 0);
e6b39846 494 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
c44b56af
NC		 495 FSL_SAI_CSR_TERE, 0);
496
497 /* TERE will remain set till the end of current frame */
498 do {
499 udelay(10);
500 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
501 } while (--count && xcsr & FSL_SAI_CSR_TERE);
502
503 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
504 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
505 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
506 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
43550821 507 }
43550821
XL		 508 break;
509 default:
510 return -EINVAL;
511 }
512
513 return 0;
514}
515
516static int fsl_sai_startup(struct snd_pcm_substream *substream,
517 struct snd_soc_dai *cpu_dai)
518{
43550821 519 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
2a266f8b 520 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
ca3e35c7 521 struct device *dev = &sai->pdev->dev;
ca3e35c7
NC		 522 int ret;
523
524 ret = clk_prepare_enable(sai->bus_clk);
525 if (ret) {
526 dev_err(dev, "failed to enable bus clock: %d\n", ret);
527 return ret;
528 }
43550821 529
2a266f8b 530 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
78957fc3
XL		 531 FSL_SAI_CR3_TRCE);
532
c5f4823b
ZW		 533 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
534 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
535
536 return ret;
43550821
XL		 537}
538
539static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
540 struct snd_soc_dai *cpu_dai)
541{
542 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
2a266f8b 543 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
43550821 544
2a266f8b 545 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
ca3e35c7
NC		 546
547 clk_disable_unprepare(sai->bus_clk);
43550821
XL		 548}
549
550static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
551 .set_sysclk = fsl_sai_set_dai_sysclk,
552 .set_fmt = fsl_sai_set_dai_fmt,
553 .hw_params = fsl_sai_hw_params,
c3ecef21 554 .hw_free = fsl_sai_hw_free,
43550821
XL		 555 .trigger = fsl_sai_trigger,
556 .startup = fsl_sai_startup,
557 .shutdown = fsl_sai_shutdown,
558};
559
560static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
561{
562 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
e6dc12d7 563
376d1a92
NC		 564 /* Software Reset for both Tx and Rx */
565 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
566 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
567 /* Clear SR bit to finish the reset */
568 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
569 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
570
78957fc3
XL		 571 regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
572 FSL_SAI_MAXBURST_TX * 2);
573 regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
574 FSL_SAI_MAXBURST_RX - 1);
43550821 575
dd9f4060
XL		 576 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
577 &sai->dma_params_rx);
43550821
XL		 578
579 snd_soc_dai_set_drvdata(cpu_dai, sai);
580
581 return 0;
582}
583
43550821
XL		 584static struct snd_soc_dai_driver fsl_sai_dai = {
585 .probe = fsl_sai_dai_probe,
43550821 586 .playback = {
20d5b76f 587 .stream_name = "CPU-Playback",
43550821
XL		 588 .channels_min = 1,
589 .channels_max = 2,
c5f4823b
ZW		 590 .rate_min = 8000,
591 .rate_max = 192000,
592 .rates = SNDRV_PCM_RATE_KNOT,
43550821
XL		 593 .formats = FSL_SAI_FORMATS,
594 },
595 .capture = {
20d5b76f 596 .stream_name = "CPU-Capture",
43550821
XL		 597 .channels_min = 1,
598 .channels_max = 2,
c5f4823b
ZW		 599 .rate_min = 8000,
600 .rate_max = 192000,
601 .rates = SNDRV_PCM_RATE_KNOT,
43550821
XL		 602 .formats = FSL_SAI_FORMATS,
603 },
604 .ops = &fsl_sai_pcm_dai_ops,
605};
606
607static const struct snd_soc_component_driver fsl_component = {
608 .name = "fsl-sai",
609};
610
78957fc3
XL		 611static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
612{
613 switch (reg) {
614 case FSL_SAI_TCSR:
615 case FSL_SAI_TCR1:
616 case FSL_SAI_TCR2:
617 case FSL_SAI_TCR3:
618 case FSL_SAI_TCR4:
619 case FSL_SAI_TCR5:
620 case FSL_SAI_TFR:
621 case FSL_SAI_TMR:
622 case FSL_SAI_RCSR:
623 case FSL_SAI_RCR1:
624 case FSL_SAI_RCR2:
625 case FSL_SAI_RCR3:
626 case FSL_SAI_RCR4:
627 case FSL_SAI_RCR5:
628 case FSL_SAI_RDR:
629 case FSL_SAI_RFR:
630 case FSL_SAI_RMR:
631 return true;
632 default:
633 return false;
634 }
635}
636
637static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
638{
639 switch (reg) {
640 case FSL_SAI_TFR:
641 case FSL_SAI_RFR:
642 case FSL_SAI_TDR:
643 case FSL_SAI_RDR:
644 return true;
645 default:
646 return false;
647 }
648
649}
650
651static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
652{
653 switch (reg) {
654 case FSL_SAI_TCSR:
655 case FSL_SAI_TCR1:
656 case FSL_SAI_TCR2:
657 case FSL_SAI_TCR3:
658 case FSL_SAI_TCR4:
659 case FSL_SAI_TCR5:
660 case FSL_SAI_TDR:
661 case FSL_SAI_TMR:
662 case FSL_SAI_RCSR:
663 case FSL_SAI_RCR1:
664 case FSL_SAI_RCR2:
665 case FSL_SAI_RCR3:
666 case FSL_SAI_RCR4:
667 case FSL_SAI_RCR5:
668 case FSL_SAI_RMR:
669 return true;
670 default:
671 return false;
672 }
673}
674
014fd22e 675static const struct regmap_config fsl_sai_regmap_config = {
78957fc3
XL		 676 .reg_bits = 32,
677 .reg_stride = 4,
678 .val_bits = 32,
679
680 .max_register = FSL_SAI_RMR,
681 .readable_reg = fsl_sai_readable_reg,
682 .volatile_reg = fsl_sai_volatile_reg,
683 .writeable_reg = fsl_sai_writeable_reg,
684};
685
43550821
XL		 686static int fsl_sai_probe(struct platform_device *pdev)
687{
4e3a99f5 688 struct device_node *np = pdev->dev.of_node;
43550821
XL		 689 struct fsl_sai *sai;
690 struct resource *res;
78957fc3 691 void __iomem *base;
ca3e35c7
NC		 692 char tmp[8];
693 int irq, ret, i;
43550821
XL		 694
695 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
696 if (!sai)
697 return -ENOMEM;
698
e2681a1b
NC		 699 sai->pdev = pdev;
700
c7540644
NC		 701 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
702 sai->sai_on_imx = true;
703
eadb0019 704 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
78957fc3 705
43550821 706 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
78957fc3
XL		 707 base = devm_ioremap_resource(&pdev->dev, res);
708 if (IS_ERR(base))
709 return PTR_ERR(base);
710
711 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
ca3e35c7
NC		 712 "bus", base, &fsl_sai_regmap_config);
713
714 /* Compatible with old DTB cases */
715 if (IS_ERR(sai->regmap))
716 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
717 "sai", base, &fsl_sai_regmap_config);
78957fc3
XL		 718 if (IS_ERR(sai->regmap)) {
719 dev_err(&pdev->dev, "regmap init failed\n");
720 return PTR_ERR(sai->regmap);
43550821
XL		 721 }
722
ca3e35c7
NC		 723 /* No error out for old DTB cases but only mark the clock NULL */
724 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
725 if (IS_ERR(sai->bus_clk)) {
726 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
727 PTR_ERR(sai->bus_clk));
728 sai->bus_clk = NULL;
729 }
730
c3ecef21
ZW		 731 sai->mclk_clk[0] = sai->bus_clk;
732 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
733 sprintf(tmp, "mclk%d", i);
ca3e35c7
NC		 734 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
735 if (IS_ERR(sai->mclk_clk[i])) {
736 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
737 i + 1, PTR_ERR(sai->mclk_clk[i]));
738 sai->mclk_clk[i] = NULL;
739 }
740 }
741
e2681a1b
NC		 742 irq = platform_get_irq(pdev, 0);
743 if (irq < 0) {
0954237f 744 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
e2681a1b
NC		 745 return irq;
746 }
747
748 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
749 if (ret) {
750 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
751 return ret;
752 }
753
08fdf65e
NC		 754 /* Sync Tx with Rx as default by following old DT binding */
755 sai->synchronous[RX] = true;
756 sai->synchronous[TX] = false;
757 fsl_sai_dai.symmetric_rates = 1;
758 fsl_sai_dai.symmetric_channels = 1;
759 fsl_sai_dai.symmetric_samplebits = 1;
760
ce7344a4
NC		 761 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
762 of_find_property(np, "fsl,sai-asynchronous", NULL)) {
763 /* error out if both synchronous and asynchronous are present */
764 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
765 return -EINVAL;
766 }
767
08fdf65e
NC		 768 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
769 /* Sync Rx with Tx */
770 sai->synchronous[RX] = false;
771 sai->synchronous[TX] = true;
772 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
773 /* Discard all settings for asynchronous mode */
774 sai->synchronous[RX] = false;
775 sai->synchronous[TX] = false;
776 fsl_sai_dai.symmetric_rates = 0;
777 fsl_sai_dai.symmetric_channels = 0;
778 fsl_sai_dai.symmetric_samplebits = 0;
779 }
780
43550821
XL		 781 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
782 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
783 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
784 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
785
43550821
XL		 786 platform_set_drvdata(pdev, sai);
787
788 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
789 &fsl_sai_dai, 1);
790 if (ret)
791 return ret;
792
c7540644
NC		 793 if (sai->sai_on_imx)
794 return imx_pcm_dma_init(pdev);
795 else
acde50a7 796 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
43550821
XL		 797}
798
799static const struct of_device_id fsl_sai_ids[] = {
800 { .compatible = "fsl,vf610-sai", },
c7540644 801 { .compatible = "fsl,imx6sx-sai", },
43550821
XL		 802 { /* sentinel */ }
803};
804
805static struct platform_driver fsl_sai_driver = {
806 .probe = fsl_sai_probe,
43550821
XL		 807 .driver = {
808 .name = "fsl-sai",
43550821
XL		 809 .of_match_table = fsl_sai_ids,
810 },
811};
812module_platform_driver(fsl_sai_driver);
813
814MODULE_DESCRIPTION("Freescale Soc SAI Interface");
815MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
816MODULE_ALIAS("platform:fsl-sai");
817MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.208885 seconds and 5 git commands to generate.