[deliverable/linux.git] / sound / soc / fsl / fsl_sai.c

/*
 * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
 *
 * Copyright 2012-2013 Freescale Semiconductor, Inc.
 *
 * This program is free software, you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation, either version 2 of the License, or(at your
 * option) any later version.
 *
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>

#include "fsl_sai.h"

static inline u32 sai_readl(struct fsl_sai *sai,
		const void __iomem *addr)
{
	u32 val;

	val = __raw_readl(addr);

	if (likely(sai->big_endian_regs))
		val = be32_to_cpu(val);
	else
		val = le32_to_cpu(val);
	rmb();

	return val;
}

static inline void sai_writel(struct fsl_sai *sai,
		u32 val, void __iomem *addr)
{
	wmb();
	if (likely(sai->big_endian_regs))
		val = cpu_to_be32(val);
	else
		val = cpu_to_le32(val);

	__raw_writel(val, addr);
}

static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
		int clk_id, unsigned int freq, int fsl_dir)
{
	u32 val_cr2, reg_cr2;
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);

	if (fsl_dir == FSL_FMT_TRANSMITTER)
		reg_cr2 = FSL_SAI_TCR2;
	else
		reg_cr2 = FSL_SAI_RCR2;

	val_cr2 = sai_readl(sai, sai->base + reg_cr2);
	switch (clk_id) {
	case FSL_SAI_CLK_BUS:
		val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
		val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
		break;
	case FSL_SAI_CLK_MAST1:
		val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
		break;
	case FSL_SAI_CLK_MAST2:
		val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
		break;
	case FSL_SAI_CLK_MAST3:
		val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
		break;
	default:
		return -EINVAL;
	}
	sai_writel(sai, val_cr2, sai->base + reg_cr2);

	return 0;
}

static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
		int clk_id, unsigned int freq, int dir)
{
	int ret;
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);

	if (dir == SND_SOC_CLOCK_IN)
		return 0;

	ret = clk_prepare_enable(sai->clk);
	if (ret)
		return ret;

	sai_writel(sai, 0x0, sai->base + FSL_SAI_RCSR);
	sai_writel(sai, 0x0, sai->base + FSL_SAI_TCSR);
	sai_writel(sai, FSL_SAI_MAXBURST_TX * 2, sai->base + FSL_SAI_TCR1);
	sai_writel(sai, FSL_SAI_MAXBURST_RX - 1, sai->base + FSL_SAI_RCR1);

	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
					FSL_FMT_TRANSMITTER);
	if (ret) {
		dev_err(cpu_dai->dev,
				"Cannot set SAI's transmitter sysclk: %d\n",
				ret);
		goto err_clk;
	}

	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
					FSL_FMT_RECEIVER);
	if (ret) {
		dev_err(cpu_dai->dev,
				"Cannot set SAI's receiver sysclk: %d\n",
				ret);
		goto err_clk;
	}

err_clk:
	clk_disable_unprepare(sai->clk);

	return ret;
}

static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
				unsigned int fmt, int fsl_dir)
{
	u32 val_cr2, val_cr3, val_cr4, reg_cr2, reg_cr3, reg_cr4;
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);

	if (fsl_dir == FSL_FMT_TRANSMITTER) {
		reg_cr2 = FSL_SAI_TCR2;
		reg_cr3 = FSL_SAI_TCR3;
		reg_cr4 = FSL_SAI_TCR4;
	} else {
		reg_cr2 = FSL_SAI_RCR2;
		reg_cr3 = FSL_SAI_RCR3;
		reg_cr4 = FSL_SAI_RCR4;
	}

	val_cr2 = sai_readl(sai, sai->base + reg_cr2);
	val_cr3 = sai_readl(sai, sai->base + reg_cr3);
	val_cr4 = sai_readl(sai, sai->base + reg_cr4);

	if (sai->big_endian_data)
		val_cr4 |= FSL_SAI_CR4_MF;
	else
		val_cr4 &= ~FSL_SAI_CR4_MF;

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		val_cr4 |= FSL_SAI_CR4_FSE;
		val_cr4 |= FSL_SAI_CR4_FSP;
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_IF:
		val_cr4 |= FSL_SAI_CR4_FSP;
		val_cr2 &= ~FSL_SAI_CR2_BCP;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		val_cr4 &= ~FSL_SAI_CR4_FSP;
		val_cr2 &= ~FSL_SAI_CR2_BCP;
		break;
	case SND_SOC_DAIFMT_NB_IF:
		val_cr4 |= FSL_SAI_CR4_FSP;
		val_cr2 |= FSL_SAI_CR2_BCP;
		break;
	case SND_SOC_DAIFMT_NB_NF:
		val_cr4 &= ~FSL_SAI_CR4_FSP;
		val_cr2 |= FSL_SAI_CR2_BCP;
		break;
	default:
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
		val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR;
		val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR;
		break;
	default:
		return -EINVAL;
	}

	val_cr3 |= FSL_SAI_CR3_TRCE;

	if (fsl_dir == FSL_FMT_RECEIVER)
		val_cr2 |= FSL_SAI_CR2_SYNC;

	sai_writel(sai, val_cr2, sai->base + reg_cr2);
	sai_writel(sai, val_cr3, sai->base + reg_cr3);
	sai_writel(sai, val_cr4, sai->base + reg_cr4);

	return 0;
}

static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
	int ret;
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);

	ret = clk_prepare_enable(sai->clk);
	if (ret)
		return ret;

	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
	if (ret) {
		dev_err(cpu_dai->dev,
				"Cannot set SAI's transmitter format: %d\n",
				ret);
		goto err_clk;
	}

	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
	if (ret) {
		dev_err(cpu_dai->dev,
				"Cannot set SAI's receiver format: %d\n",
				ret);
		goto err_clk;
	}

err_clk:
	clk_disable_unprepare(sai->clk);

	return ret;
}

static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
		struct snd_pcm_hw_params *params,
		struct snd_soc_dai *cpu_dai)
{
	u32 val_cr4, val_cr5, val_mr, reg_cr4, reg_cr5, reg_mr, word_width;
	unsigned int channels = params_channels(params);
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		reg_cr4 = FSL_SAI_TCR4;
		reg_cr5 = FSL_SAI_TCR5;
		reg_mr = FSL_SAI_TMR;
	} else {
		reg_cr4 = FSL_SAI_RCR4;
		reg_cr5 = FSL_SAI_RCR5;
		reg_mr = FSL_SAI_RMR;
	}

	val_cr4 = sai_readl(sai, sai->base + reg_cr4);
	val_cr4 &= ~FSL_SAI_CR4_SYWD_MASK;
	val_cr4 &= ~FSL_SAI_CR4_FRSZ_MASK;

	val_cr5 = sai_readl(sai, sai->base + reg_cr5);
	val_cr5 &= ~FSL_SAI_CR5_WNW_MASK;
	val_cr5 &= ~FSL_SAI_CR5_W0W_MASK;
	val_cr5 &= ~FSL_SAI_CR5_FBT_MASK;

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		word_width = 16;
		break;
	case SNDRV_PCM_FORMAT_S20_3LE:
		word_width = 20;
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		word_width = 24;
		break;
	default:
		return -EINVAL;
	}

	val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
	val_cr5 |= FSL_SAI_CR5_WNW(word_width);
	val_cr5 |= FSL_SAI_CR5_W0W(word_width);

	if (sai->big_endian_data)
		val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
	else
		val_cr5 |= FSL_SAI_CR5_FBT(0);

	val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
	if (channels == 2 || channels == 1)
		val_mr = ~0UL - ((1 << channels) - 1);
	else
		return -EINVAL;

	sai_writel(sai, val_cr4, sai->base + reg_cr4);
	sai_writel(sai, val_cr5, sai->base + reg_cr5);
	sai_writel(sai, val_mr, sai->base + reg_mr);

	return 0;
}

static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
		struct snd_soc_dai *cpu_dai)
{
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
	unsigned int tcsr, rcsr;

	tcsr = sai_readl(sai, sai->base + FSL_SAI_TCSR);
	rcsr = sai_readl(sai, sai->base + FSL_SAI_RCSR);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		tcsr |= FSL_SAI_CSR_FRDE;
		rcsr &= ~FSL_SAI_CSR_FRDE;
	} else {
		rcsr |= FSL_SAI_CSR_FRDE;
		tcsr &= ~FSL_SAI_CSR_FRDE;
	}

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		tcsr |= FSL_SAI_CSR_TERE;
		rcsr |= FSL_SAI_CSR_TERE;
		sai_writel(sai, rcsr, sai->base + FSL_SAI_RCSR);
		sai_writel(sai, tcsr, sai->base + FSL_SAI_TCSR);
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (!(cpu_dai->playback_active || cpu_dai->capture_active)) {
			tcsr &= ~FSL_SAI_CSR_TERE;
			rcsr &= ~FSL_SAI_CSR_TERE;
		}
		sai_writel(sai, tcsr, sai->base + FSL_SAI_TCSR);
		sai_writel(sai, rcsr, sai->base + FSL_SAI_RCSR);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int fsl_sai_startup(struct snd_pcm_substream *substream,
		struct snd_soc_dai *cpu_dai)
{
	int ret;
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);

	ret = clk_prepare_enable(sai->clk);

	return ret;
}

static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
		struct snd_soc_dai *cpu_dai)
{
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);

	clk_disable_unprepare(sai->clk);
}

static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
	.set_sysclk	= fsl_sai_set_dai_sysclk,
	.set_fmt	= fsl_sai_set_dai_fmt,
	.hw_params	= fsl_sai_hw_params,
	.trigger	= fsl_sai_trigger,
	.startup	= fsl_sai_startup,
	.shutdown	= fsl_sai_shutdown,
};

static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
{
	struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);

	snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
				&sai->dma_params_rx);

	snd_soc_dai_set_drvdata(cpu_dai, sai);

	return 0;
}

static struct snd_soc_dai_driver fsl_sai_dai = {
	.probe = fsl_sai_dai_probe,
	.playback = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = FSL_SAI_FORMATS,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = FSL_SAI_FORMATS,
	},
	.ops = &fsl_sai_pcm_dai_ops,
};

static const struct snd_soc_component_driver fsl_component = {
	.name           = "fsl-sai",
};

static int fsl_sai_probe(struct platform_device *pdev)
{
	int ret;
	struct fsl_sai *sai;
	struct resource *res;
	struct device_node *np = pdev->dev.of_node;

	sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
	if (!sai)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sai->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(sai->base))
		return PTR_ERR(sai->base);

	sai->clk = devm_clk_get(&pdev->dev, "sai");
	if (IS_ERR(sai->clk)) {
		dev_err(&pdev->dev, "Cannot get SAI's clock\n");
		return PTR_ERR(sai->clk);
	}

	sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
	sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
	sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
	sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;

	sai->big_endian_regs = of_property_read_bool(np, "big-endian-regs");
	sai->big_endian_data = of_property_read_bool(np, "big-endian-data");

	platform_set_drvdata(pdev, sai);

	ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
			&fsl_sai_dai, 1);
	if (ret)
		return ret;

	return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
			SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
}

static const struct of_device_id fsl_sai_ids[] = {
	{ .compatible = "fsl,vf610-sai", },
	{ /* sentinel */ }
};

static struct platform_driver fsl_sai_driver = {
	.probe = fsl_sai_probe,
	.driver = {
		.name = "fsl-sai",
		.owner = THIS_MODULE,
		.of_match_table = fsl_sai_ids,
	},
};
module_platform_driver(fsl_sai_driver);

MODULE_DESCRIPTION("Freescale Soc SAI Interface");
MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
MODULE_ALIAS("platform:fsl-sai");
MODULE_LICENSE("GPL");
Commit	Line	Data
43550821 XL	1	/*
	2	* Freescale ALSA SoC Digital Audio Interface (SAI) driver.
	3	*
	4	* Copyright 2012-2013 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software, you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation, either version 2 of the License, or(at your
	9	* option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/delay.h>
	15	#include <linux/dmaengine.h>
	16	#include <linux/module.h>
	17	#include <linux/of_address.h>
	18	#include <linux/slab.h>
	19	#include <sound/core.h>
	20	#include <sound/dmaengine_pcm.h>
	21	#include <sound/pcm_params.h>
	22
	23	#include "fsl_sai.h"
	24
	25	static inline u32 sai_readl(struct fsl_sai *sai,
	26	const void __iomem *addr)
	27	{
	28	u32 val;
	29
	30	val = __raw_readl(addr);
	31
	32	if (likely(sai->big_endian_regs))
	33	val = be32_to_cpu(val);
	34	else
	35	val = le32_to_cpu(val);
	36	rmb();
	37
	38	return val;
	39	}
	40
	41	static inline void sai_writel(struct fsl_sai *sai,
	42	u32 val, void __iomem *addr)
	43	{
	44	wmb();
	45	if (likely(sai->big_endian_regs))
	46	val = cpu_to_be32(val);
	47	else
	48	val = cpu_to_le32(val);
	49
	50	__raw_writel(val, addr);
	51	}
	52
	53	static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
	54	int clk_id, unsigned int freq, int fsl_dir)
	55	{
	56	u32 val_cr2, reg_cr2;
	57	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
	58
	59	if (fsl_dir == FSL_FMT_TRANSMITTER)
	60	reg_cr2 = FSL_SAI_TCR2;
	61	else
	62	reg_cr2 = FSL_SAI_RCR2;
	63
	64	val_cr2 = sai_readl(sai, sai->base + reg_cr2);
65	switch (clk_id) {
66	case FSL_SAI_CLK_BUS:
67	val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
68	val_cr2 \|= FSL_SAI_CR2_MSEL_BUS;
69	break;
70	case FSL_SAI_CLK_MAST1:
71	val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
72	val_cr2 \|= FSL_SAI_CR2_MSEL_MCLK1;
73	break;
74	case FSL_SAI_CLK_MAST2:
75	val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
76	val_cr2 \|= FSL_SAI_CR2_MSEL_MCLK2;
77	break;
78	case FSL_SAI_CLK_MAST3:
79	val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
80	val_cr2 \|= FSL_SAI_CR2_MSEL_MCLK3;
81	break;
82	default:
83	return -EINVAL;
84	}
85	sai_writel(sai, val_cr2, sai->base + reg_cr2);
86
87	return 0;
88	}
89
90	static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
91	int clk_id, unsigned int freq, int dir)
92	{
93	int ret;
94	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
95
96	if (dir == SND_SOC_CLOCK_IN)
97	return 0;
98
99	ret = clk_prepare_enable(sai->clk);
100	if (ret)
101	return ret;
102
103	sai_writel(sai, 0x0, sai->base + FSL_SAI_RCSR);
104	sai_writel(sai, 0x0, sai->base + FSL_SAI_TCSR);
105	sai_writel(sai, FSL_SAI_MAXBURST_TX * 2, sai->base + FSL_SAI_TCR1);
106	sai_writel(sai, FSL_SAI_MAXBURST_RX - 1, sai->base + FSL_SAI_RCR1);
107
108	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
109	FSL_FMT_TRANSMITTER);
110	if (ret) {
111	dev_err(cpu_dai->dev,
112	"Cannot set SAI's transmitter sysclk: %d\n",
113	ret);
1fb2d9d7	114	goto err_clk;
43550821 XL	115	}
	116
	117	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
	118	FSL_FMT_RECEIVER);
	119	if (ret) {
	120	dev_err(cpu_dai->dev,
	121	"Cannot set SAI's receiver sysclk: %d\n",
	122	ret);
1fb2d9d7	123	goto err_clk;
43550821 XL	124	}
43550821 XL	125
1fb2d9d7	126	err_clk:
43550821 XL	127	clk_disable_unprepare(sai->clk);
43550821 XL	128
1fb2d9d7	129	return ret;
43550821 XL	130	}
	131
	132	static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
	133	unsigned int fmt, int fsl_dir)
	134	{
	135	u32 val_cr2, val_cr3, val_cr4, reg_cr2, reg_cr3, reg_cr4;
	136	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
	137
	138	if (fsl_dir == FSL_FMT_TRANSMITTER) {
	139	reg_cr2 = FSL_SAI_TCR2;
	140	reg_cr3 = FSL_SAI_TCR3;
	141	reg_cr4 = FSL_SAI_TCR4;
	142	} else {
	143	reg_cr2 = FSL_SAI_RCR2;
	144	reg_cr3 = FSL_SAI_RCR3;
	145	reg_cr4 = FSL_SAI_RCR4;
	146	}
	147
	148	val_cr2 = sai_readl(sai, sai->base + reg_cr2);
	149	val_cr3 = sai_readl(sai, sai->base + reg_cr3);
	150	val_cr4 = sai_readl(sai, sai->base + reg_cr4);
	151
	152	if (sai->big_endian_data)
	153	val_cr4 \|= FSL_SAI_CR4_MF;
	154	else
	155	val_cr4 &= ~FSL_SAI_CR4_MF;
	156
	157	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	158	case SND_SOC_DAIFMT_I2S:
	159	val_cr4 \|= FSL_SAI_CR4_FSE;
	160	val_cr4 \|= FSL_SAI_CR4_FSP;
	161	break;
	162	default:
	163	return -EINVAL;
	164	}
	165
	166	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	167	case SND_SOC_DAIFMT_IB_IF:
	168	val_cr4 \|= FSL_SAI_CR4_FSP;
	169	val_cr2 &= ~FSL_SAI_CR2_BCP;
	170	break;
	171	case SND_SOC_DAIFMT_IB_NF:
	172	val_cr4 &= ~FSL_SAI_CR4_FSP;
	173	val_cr2 &= ~FSL_SAI_CR2_BCP;
	174	break;
	175	case SND_SOC_DAIFMT_NB_IF:
	176	val_cr4 \|= FSL_SAI_CR4_FSP;
	177	val_cr2 \|= FSL_SAI_CR2_BCP;
	178	break;
	179	case SND_SOC_DAIFMT_NB_NF:
	180	val_cr4 &= ~FSL_SAI_CR4_FSP;
	181	val_cr2 \|= FSL_SAI_CR2_BCP;
	182	break;
	183	default:
	184	return -EINVAL;
	185	}
	186
	187	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	188	case SND_SOC_DAIFMT_CBS_CFS:
	189	val_cr2 \|= FSL_SAI_CR2_BCD_MSTR;
	190	val_cr4 \|= FSL_SAI_CR4_FSD_MSTR;
	191	break;
	192	case SND_SOC_DAIFMT_CBM_CFM:
	193	val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR;
194	val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR;
195	break;
196	default:
197	return -EINVAL;
198	}
199
200	val_cr3 \|= FSL_SAI_CR3_TRCE;
201
202	if (fsl_dir == FSL_FMT_RECEIVER)
203	val_cr2 \|= FSL_SAI_CR2_SYNC;
204
205	sai_writel(sai, val_cr2, sai->base + reg_cr2);
206	sai_writel(sai, val_cr3, sai->base + reg_cr3);
207	sai_writel(sai, val_cr4, sai->base + reg_cr4);
208
209	return 0;
210	}
211
212	static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
213	{
214	int ret;
215	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
216
217	ret = clk_prepare_enable(sai->clk);
218	if (ret)
219	return ret;
220
221	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
222	if (ret) {
223	dev_err(cpu_dai->dev,
224	"Cannot set SAI's transmitter format: %d\n",
225	ret);
1fb2d9d7	226	goto err_clk;
43550821 XL	227	}
	228
	229	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
	230	if (ret) {
	231	dev_err(cpu_dai->dev,
	232	"Cannot set SAI's receiver format: %d\n",
	233	ret);
1fb2d9d7	234	goto err_clk;
43550821 XL	235	}
43550821 XL	236
1fb2d9d7	237	err_clk:
43550821 XL	238	clk_disable_unprepare(sai->clk);
43550821 XL	239
1fb2d9d7	240	return ret;
43550821 XL	241	}
	242
	243	static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
	244	struct snd_pcm_hw_params *params,
	245	struct snd_soc_dai *cpu_dai)
	246	{
	247	u32 val_cr4, val_cr5, val_mr, reg_cr4, reg_cr5, reg_mr, word_width;
	248	unsigned int channels = params_channels(params);
	249	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
	250
	251	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	252	reg_cr4 = FSL_SAI_TCR4;
	253	reg_cr5 = FSL_SAI_TCR5;
	254	reg_mr = FSL_SAI_TMR;
	255	} else {
	256	reg_cr4 = FSL_SAI_RCR4;
	257	reg_cr5 = FSL_SAI_RCR5;
	258	reg_mr = FSL_SAI_RMR;
	259	}
	260
	261	val_cr4 = sai_readl(sai, sai->base + reg_cr4);
	262	val_cr4 &= ~FSL_SAI_CR4_SYWD_MASK;
	263	val_cr4 &= ~FSL_SAI_CR4_FRSZ_MASK;
	264
	265	val_cr5 = sai_readl(sai, sai->base + reg_cr5);
	266	val_cr5 &= ~FSL_SAI_CR5_WNW_MASK;
	267	val_cr5 &= ~FSL_SAI_CR5_W0W_MASK;
	268	val_cr5 &= ~FSL_SAI_CR5_FBT_MASK;
	269
	270	switch (params_format(params)) {
	271	case SNDRV_PCM_FORMAT_S16_LE:
	272	word_width = 16;
	273	break;
	274	case SNDRV_PCM_FORMAT_S20_3LE:
	275	word_width = 20;
	276	break;
	277	case SNDRV_PCM_FORMAT_S24_LE:
	278	word_width = 24;
	279	break;
	280	default:
	281	return -EINVAL;
	282	}
	283
	284	val_cr4 \|= FSL_SAI_CR4_SYWD(word_width);
	285	val_cr5 \|= FSL_SAI_CR5_WNW(word_width);
	286	val_cr5 \|= FSL_SAI_CR5_W0W(word_width);
	287
	288	if (sai->big_endian_data)
	289	val_cr5 \|= FSL_SAI_CR5_FBT(word_width - 1);
	290	else
	291	val_cr5 \|= FSL_SAI_CR5_FBT(0);
	292
	293	val_cr4 \|= FSL_SAI_CR4_FRSZ(channels);
	294	if (channels == 2 \|\| channels == 1)
	295	val_mr = ~0UL - ((1 << channels) - 1);
	296	else
	297	return -EINVAL;
	298
	299	sai_writel(sai, val_cr4, sai->base + reg_cr4);
	300	sai_writel(sai, val_cr5, sai->base + reg_cr5);
	301	sai_writel(sai, val_mr, sai->base + reg_mr);
	302
	303	return 0;
	304	}
305
306	static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
307	struct snd_soc_dai *cpu_dai)
308	{
309	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
310	unsigned int tcsr, rcsr;
311
312	tcsr = sai_readl(sai, sai->base + FSL_SAI_TCSR);
313	rcsr = sai_readl(sai, sai->base + FSL_SAI_RCSR);
314
315	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
316	tcsr \|= FSL_SAI_CSR_FRDE;
317	rcsr &= ~FSL_SAI_CSR_FRDE;
318	} else {
319	rcsr \|= FSL_SAI_CSR_FRDE;
320	tcsr &= ~FSL_SAI_CSR_FRDE;
321	}
322
323	switch (cmd) {
324	case SNDRV_PCM_TRIGGER_START:
325	case SNDRV_PCM_TRIGGER_RESUME:
326	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
327	tcsr \|= FSL_SAI_CSR_TERE;
328	rcsr \|= FSL_SAI_CSR_TERE;
329	sai_writel(sai, rcsr, sai->base + FSL_SAI_RCSR);
330	sai_writel(sai, tcsr, sai->base + FSL_SAI_TCSR);
331	break;
332
333	case SNDRV_PCM_TRIGGER_STOP:
334	case SNDRV_PCM_TRIGGER_SUSPEND:
335	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
336	if (!(cpu_dai->playback_active \|\| cpu_dai->capture_active)) {
337	tcsr &= ~FSL_SAI_CSR_TERE;
338	rcsr &= ~FSL_SAI_CSR_TERE;
339	}
340	sai_writel(sai, tcsr, sai->base + FSL_SAI_TCSR);
341	sai_writel(sai, rcsr, sai->base + FSL_SAI_RCSR);
342	break;
343	default:
344	return -EINVAL;
345	}
346
347	return 0;
348	}
349
350	static int fsl_sai_startup(struct snd_pcm_substream *substream,
351	struct snd_soc_dai *cpu_dai)
352	{
353	int ret;
354	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
355
356	ret = clk_prepare_enable(sai->clk);
357
358	return ret;
359	}
360
361	static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
362	struct snd_soc_dai *cpu_dai)
363	{
364	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
365
366	clk_disable_unprepare(sai->clk);
367	}
368
369	static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
370	.set_sysclk = fsl_sai_set_dai_sysclk,
371	.set_fmt = fsl_sai_set_dai_fmt,
372	.hw_params = fsl_sai_hw_params,
373	.trigger = fsl_sai_trigger,
374	.startup = fsl_sai_startup,
375	.shutdown = fsl_sai_shutdown,
376	};
377
378	static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
379	{
380	struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
381
dd9f4060 XL	382	snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
dd9f4060 XL	383	&sai->dma_params_rx);
43550821 XL	384
	385	snd_soc_dai_set_drvdata(cpu_dai, sai);
	386
	387	return 0;
	388	}
	389
43550821 XL	390	static struct snd_soc_dai_driver fsl_sai_dai = {
43550821 XL	391	.probe = fsl_sai_dai_probe,
43550821 XL	392	.playback = {
	393	.channels_min = 1,
	394	.channels_max = 2,
	395	.rates = SNDRV_PCM_RATE_8000_96000,
	396	.formats = FSL_SAI_FORMATS,
	397	},
	398	.capture = {
	399	.channels_min = 1,
	400	.channels_max = 2,
	401	.rates = SNDRV_PCM_RATE_8000_96000,
	402	.formats = FSL_SAI_FORMATS,
	403	},
	404	.ops = &fsl_sai_pcm_dai_ops,
	405	};
	406
	407	static const struct snd_soc_component_driver fsl_component = {
	408	.name = "fsl-sai",
	409	};
	410
	411	static int fsl_sai_probe(struct platform_device *pdev)
	412	{
	413	int ret;
	414	struct fsl_sai *sai;
	415	struct resource *res;
	416	struct device_node *np = pdev->dev.of_node;
	417
	418	sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
	419	if (!sai)
	420	return -ENOMEM;
	421
	422	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	423	sai->base = devm_ioremap_resource(&pdev->dev, res);
	424	if (IS_ERR(sai->base))
	425	return PTR_ERR(sai->base);
	426
	427	sai->clk = devm_clk_get(&pdev->dev, "sai");
	428	if (IS_ERR(sai->clk)) {
	429	dev_err(&pdev->dev, "Cannot get SAI's clock\n");
	430	return PTR_ERR(sai->clk);
	431	}
	432
	433	sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
	434	sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
	435	sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
	436	sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
	437
	438	sai->big_endian_regs = of_property_read_bool(np, "big-endian-regs");
	439	sai->big_endian_data = of_property_read_bool(np, "big-endian-data");
	440
	441	platform_set_drvdata(pdev, sai);
	442
	443	ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
	444	&fsl_sai_dai, 1);
	445	if (ret)
	446	return ret;
	447
e5180df3	448	return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
43550821	449	SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
43550821 XL	450	}
	451
	452	static const struct of_device_id fsl_sai_ids[] = {
	453	{ .compatible = "fsl,vf610-sai", },
	454	{ /* sentinel */ }
	455	};
	456
	457	static struct platform_driver fsl_sai_driver = {
	458	.probe = fsl_sai_probe,
43550821 XL	459	.driver = {
	460	.name = "fsl-sai",
	461	.owner = THIS_MODULE,
	462	.of_match_table = fsl_sai_ids,
	463	},
	464	};
	465	module_platform_driver(fsl_sai_driver);
	466
	467	MODULE_DESCRIPTION("Freescale Soc SAI Interface");
	468	MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
	469	MODULE_ALIAS("platform:fsl-sai");
	470	MODULE_LICENSE("GPL");