Commit | Line | Data |
---|---|---|
43550821 XL |
1 | /* |
2 | * Freescale ALSA SoC Digital Audio Interface (SAI) driver. | |
3 | * | |
c3ecef21 | 4 | * Copyright 2012-2015 Freescale Semiconductor, Inc. |
43550821 XL |
5 | * |
6 | * This program is free software, you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation, either version 2 of the License, or(at your | |
9 | * option) any later version. | |
10 | * | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of_address.h> | |
78957fc3 | 18 | #include <linux/regmap.h> |
43550821 | 19 | #include <linux/slab.h> |
512feb4e | 20 | #include <linux/time.h> |
43550821 XL |
21 | #include <sound/core.h> |
22 | #include <sound/dmaengine_pcm.h> | |
23 | #include <sound/pcm_params.h> | |
24 | ||
25 | #include "fsl_sai.h" | |
c7540644 | 26 | #include "imx-pcm.h" |
43550821 | 27 | |
e2681a1b NC |
28 | #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ |
29 | FSL_SAI_CSR_FEIE) | |
30 | ||
444c37ae | 31 | static const unsigned int fsl_sai_rates[] = { |
c5f4823b ZW |
32 | 8000, 11025, 12000, 16000, 22050, |
33 | 24000, 32000, 44100, 48000, 64000, | |
34 | 88200, 96000, 176400, 192000 | |
35 | }; | |
36 | ||
444c37ae | 37 | static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { |
c5f4823b ZW |
38 | .count = ARRAY_SIZE(fsl_sai_rates), |
39 | .list = fsl_sai_rates, | |
40 | }; | |
41 | ||
e2681a1b NC |
42 | static irqreturn_t fsl_sai_isr(int irq, void *devid) |
43 | { | |
44 | struct fsl_sai *sai = (struct fsl_sai *)devid; | |
45 | struct device *dev = &sai->pdev->dev; | |
413312aa NC |
46 | u32 flags, xcsr, mask; |
47 | bool irq_none = true; | |
48 | ||
49 | /* | |
50 | * Both IRQ status bits and IRQ mask bits are in the xCSR but | |
51 | * different shifts. And we here create a mask only for those | |
52 | * IRQs that we activated. | |
53 | */ | |
e2681a1b NC |
54 | mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; |
55 | ||
56 | /* Tx IRQ */ | |
57 | regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr); | |
413312aa NC |
58 | flags = xcsr & mask; |
59 | ||
60 | if (flags) | |
61 | irq_none = false; | |
62 | else | |
63 | goto irq_rx; | |
e2681a1b | 64 | |
413312aa | 65 | if (flags & FSL_SAI_CSR_WSF) |
e2681a1b NC |
66 | dev_dbg(dev, "isr: Start of Tx word detected\n"); |
67 | ||
413312aa | 68 | if (flags & FSL_SAI_CSR_SEF) |
e2681a1b NC |
69 | dev_warn(dev, "isr: Tx Frame sync error detected\n"); |
70 | ||
413312aa | 71 | if (flags & FSL_SAI_CSR_FEF) { |
e2681a1b NC |
72 | dev_warn(dev, "isr: Transmit underrun detected\n"); |
73 | /* FIFO reset for safety */ | |
74 | xcsr |= FSL_SAI_CSR_FR; | |
75 | } | |
76 | ||
413312aa | 77 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
78 | dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); |
79 | ||
413312aa | 80 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
81 | dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); |
82 | ||
413312aa NC |
83 | flags &= FSL_SAI_CSR_xF_W_MASK; |
84 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
85 | ||
86 | if (flags) | |
87 | regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr); | |
e2681a1b | 88 | |
413312aa | 89 | irq_rx: |
e2681a1b NC |
90 | /* Rx IRQ */ |
91 | regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr); | |
413312aa | 92 | flags = xcsr & mask; |
e2681a1b | 93 | |
413312aa NC |
94 | if (flags) |
95 | irq_none = false; | |
96 | else | |
97 | goto out; | |
98 | ||
99 | if (flags & FSL_SAI_CSR_WSF) | |
e2681a1b NC |
100 | dev_dbg(dev, "isr: Start of Rx word detected\n"); |
101 | ||
413312aa | 102 | if (flags & FSL_SAI_CSR_SEF) |
e2681a1b NC |
103 | dev_warn(dev, "isr: Rx Frame sync error detected\n"); |
104 | ||
413312aa | 105 | if (flags & FSL_SAI_CSR_FEF) { |
e2681a1b NC |
106 | dev_warn(dev, "isr: Receive overflow detected\n"); |
107 | /* FIFO reset for safety */ | |
108 | xcsr |= FSL_SAI_CSR_FR; | |
109 | } | |
110 | ||
413312aa | 111 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
112 | dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); |
113 | ||
413312aa | 114 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
115 | dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); |
116 | ||
413312aa NC |
117 | flags &= FSL_SAI_CSR_xF_W_MASK; |
118 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
e2681a1b | 119 | |
413312aa | 120 | if (flags) |
4800f88b | 121 | regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr); |
413312aa NC |
122 | |
123 | out: | |
124 | if (irq_none) | |
125 | return IRQ_NONE; | |
126 | else | |
127 | return IRQ_HANDLED; | |
e2681a1b NC |
128 | } |
129 | ||
c1df2964 ZW |
130 | static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, |
131 | u32 rx_mask, int slots, int slot_width) | |
132 | { | |
133 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
134 | ||
135 | sai->slots = slots; | |
136 | sai->slot_width = slot_width; | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
43550821 XL |
141 | static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, |
142 | int clk_id, unsigned int freq, int fsl_dir) | |
143 | { | |
43550821 | 144 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b NC |
145 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
146 | u32 val_cr2 = 0; | |
633ff8f8 | 147 | |
43550821 XL |
148 | switch (clk_id) { |
149 | case FSL_SAI_CLK_BUS: | |
43550821 XL |
150 | val_cr2 |= FSL_SAI_CR2_MSEL_BUS; |
151 | break; | |
152 | case FSL_SAI_CLK_MAST1: | |
43550821 XL |
153 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; |
154 | break; | |
155 | case FSL_SAI_CLK_MAST2: | |
43550821 XL |
156 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; |
157 | break; | |
158 | case FSL_SAI_CLK_MAST3: | |
43550821 XL |
159 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; |
160 | break; | |
161 | default: | |
162 | return -EINVAL; | |
163 | } | |
633ff8f8 | 164 | |
2a266f8b NC |
165 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), |
166 | FSL_SAI_CR2_MSEL_MASK, val_cr2); | |
43550821 XL |
167 | |
168 | return 0; | |
169 | } | |
170 | ||
171 | static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
172 | int clk_id, unsigned int freq, int dir) | |
173 | { | |
4e3a99f5 | 174 | int ret; |
43550821 XL |
175 | |
176 | if (dir == SND_SOC_CLOCK_IN) | |
177 | return 0; | |
178 | ||
43550821 XL |
179 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, |
180 | FSL_FMT_TRANSMITTER); | |
181 | if (ret) { | |
190af12d | 182 | dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); |
78957fc3 | 183 | return ret; |
43550821 XL |
184 | } |
185 | ||
186 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, | |
187 | FSL_FMT_RECEIVER); | |
78957fc3 | 188 | if (ret) |
190af12d | 189 | dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); |
43550821 | 190 | |
1fb2d9d7 | 191 | return ret; |
43550821 XL |
192 | } |
193 | ||
194 | static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, | |
195 | unsigned int fmt, int fsl_dir) | |
196 | { | |
43550821 | 197 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b NC |
198 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
199 | u32 val_cr2 = 0, val_cr4 = 0; | |
43550821 | 200 | |
eadb0019 | 201 | if (!sai->is_lsb_first) |
72aa62be | 202 | val_cr4 |= FSL_SAI_CR4_MF; |
43550821 | 203 | |
13cde090 | 204 | /* DAI mode */ |
43550821 XL |
205 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
206 | case SND_SOC_DAIFMT_I2S: | |
a3f7dcc9 XL |
207 | /* |
208 | * Frame low, 1clk before data, one word length for frame sync, | |
209 | * frame sync starts one serial clock cycle earlier, | |
210 | * that is, together with the last bit of the previous | |
211 | * data word. | |
212 | */ | |
ef33bc32 | 213 | val_cr2 |= FSL_SAI_CR2_BCP; |
13cde090 XL |
214 | val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; |
215 | break; | |
216 | case SND_SOC_DAIFMT_LEFT_J: | |
a3f7dcc9 XL |
217 | /* |
218 | * Frame high, one word length for frame sync, | |
219 | * frame sync asserts with the first bit of the frame. | |
220 | */ | |
ef33bc32 | 221 | val_cr2 |= FSL_SAI_CR2_BCP; |
43550821 | 222 | break; |
a3f7dcc9 XL |
223 | case SND_SOC_DAIFMT_DSP_A: |
224 | /* | |
225 | * Frame high, 1clk before data, one bit for frame sync, | |
226 | * frame sync starts one serial clock cycle earlier, | |
227 | * that is, together with the last bit of the previous | |
228 | * data word. | |
229 | */ | |
ef33bc32 | 230 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
231 | val_cr4 |= FSL_SAI_CR4_FSE; |
232 | sai->is_dsp_mode = true; | |
233 | break; | |
234 | case SND_SOC_DAIFMT_DSP_B: | |
235 | /* | |
236 | * Frame high, one bit for frame sync, | |
237 | * frame sync asserts with the first bit of the frame. | |
238 | */ | |
ef33bc32 | 239 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
240 | sai->is_dsp_mode = true; |
241 | break; | |
13cde090 XL |
242 | case SND_SOC_DAIFMT_RIGHT_J: |
243 | /* To be done */ | |
43550821 XL |
244 | default: |
245 | return -EINVAL; | |
246 | } | |
247 | ||
13cde090 | 248 | /* DAI clock inversion */ |
43550821 XL |
249 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
250 | case SND_SOC_DAIFMT_IB_IF: | |
13cde090 XL |
251 | /* Invert both clocks */ |
252 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
253 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
254 | break; |
255 | case SND_SOC_DAIFMT_IB_NF: | |
13cde090 XL |
256 | /* Invert bit clock */ |
257 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
43550821 XL |
258 | break; |
259 | case SND_SOC_DAIFMT_NB_IF: | |
13cde090 XL |
260 | /* Invert frame clock */ |
261 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
262 | break; |
263 | case SND_SOC_DAIFMT_NB_NF: | |
13cde090 | 264 | /* Nothing to do for both normal cases */ |
43550821 XL |
265 | break; |
266 | default: | |
267 | return -EINVAL; | |
268 | } | |
269 | ||
13cde090 | 270 | /* DAI clock master masks */ |
43550821 XL |
271 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
272 | case SND_SOC_DAIFMT_CBS_CFS: | |
273 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; | |
274 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; | |
275 | break; | |
276 | case SND_SOC_DAIFMT_CBM_CFM: | |
c3ecef21 | 277 | sai->is_slave_mode = true; |
43550821 | 278 | break; |
13cde090 XL |
279 | case SND_SOC_DAIFMT_CBS_CFM: |
280 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; | |
13cde090 XL |
281 | break; |
282 | case SND_SOC_DAIFMT_CBM_CFS: | |
13cde090 | 283 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; |
c3ecef21 | 284 | sai->is_slave_mode = true; |
13cde090 | 285 | break; |
43550821 XL |
286 | default: |
287 | return -EINVAL; | |
288 | } | |
289 | ||
2a266f8b NC |
290 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), |
291 | FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); | |
292 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), | |
293 | FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | | |
294 | FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); | |
43550821 XL |
295 | |
296 | return 0; | |
297 | } | |
298 | ||
299 | static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
300 | { | |
4e3a99f5 | 301 | int ret; |
43550821 | 302 | |
43550821 XL |
303 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER); |
304 | if (ret) { | |
190af12d | 305 | dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); |
78957fc3 | 306 | return ret; |
43550821 XL |
307 | } |
308 | ||
309 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER); | |
78957fc3 | 310 | if (ret) |
190af12d | 311 | dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); |
43550821 | 312 | |
1fb2d9d7 | 313 | return ret; |
43550821 XL |
314 | } |
315 | ||
c3ecef21 ZW |
316 | static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) |
317 | { | |
318 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); | |
319 | unsigned long clk_rate; | |
320 | u32 savediv = 0, ratio, savesub = freq; | |
321 | u32 id; | |
322 | int ret = 0; | |
323 | ||
324 | /* Don't apply to slave mode */ | |
325 | if (sai->is_slave_mode) | |
326 | return 0; | |
327 | ||
328 | for (id = 0; id < FSL_SAI_MCLK_MAX; id++) { | |
329 | clk_rate = clk_get_rate(sai->mclk_clk[id]); | |
330 | if (!clk_rate) | |
331 | continue; | |
332 | ||
333 | ratio = clk_rate / freq; | |
334 | ||
335 | ret = clk_rate - ratio * freq; | |
336 | ||
337 | /* | |
338 | * Drop the source that can not be | |
339 | * divided into the required rate. | |
340 | */ | |
341 | if (ret != 0 && clk_rate / ret < 1000) | |
342 | continue; | |
343 | ||
344 | dev_dbg(dai->dev, | |
345 | "ratio %d for freq %dHz based on clock %ldHz\n", | |
346 | ratio, freq, clk_rate); | |
347 | ||
348 | if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512) | |
349 | ratio /= 2; | |
350 | else | |
351 | continue; | |
352 | ||
353 | if (ret < savesub) { | |
354 | savediv = ratio; | |
355 | sai->mclk_id[tx] = id; | |
356 | savesub = ret; | |
357 | } | |
358 | ||
359 | if (ret == 0) | |
360 | break; | |
361 | } | |
362 | ||
363 | if (savediv == 0) { | |
364 | dev_err(dai->dev, "failed to derive required %cx rate: %d\n", | |
365 | tx ? 'T' : 'R', freq); | |
366 | return -EINVAL; | |
367 | } | |
368 | ||
9cc58712 ZW |
369 | /* |
370 | * 1) For Asynchronous mode, we must set RCR2 register for capture, and | |
371 | * set TCR2 register for playback. | |
372 | * 2) For Tx sync with Rx clock, we must set RCR2 register for playback | |
373 | * and capture. | |
374 | * 3) For Rx sync with Tx clock, we must set TCR2 register for playback | |
375 | * and capture. | |
376 | * 4) For Tx and Rx are both Synchronous with another SAI, we just | |
377 | * ignore it. | |
378 | */ | |
379 | if ((sai->synchronous[TX] && !sai->synchronous[RX]) || | |
380 | (!tx && !sai->synchronous[RX])) { | |
c3ecef21 ZW |
381 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, |
382 | FSL_SAI_CR2_MSEL_MASK, | |
383 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
384 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, | |
385 | FSL_SAI_CR2_DIV_MASK, savediv - 1); | |
9cc58712 ZW |
386 | } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) || |
387 | (tx && !sai->synchronous[TX])) { | |
c3ecef21 ZW |
388 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, |
389 | FSL_SAI_CR2_MSEL_MASK, | |
390 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
391 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, | |
392 | FSL_SAI_CR2_DIV_MASK, savediv - 1); | |
393 | } | |
394 | ||
395 | dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", | |
396 | sai->mclk_id[tx], savediv, savesub); | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
43550821 XL |
401 | static int fsl_sai_hw_params(struct snd_pcm_substream *substream, |
402 | struct snd_pcm_hw_params *params, | |
403 | struct snd_soc_dai *cpu_dai) | |
404 | { | |
4e3a99f5 | 405 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b | 406 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
43550821 | 407 | unsigned int channels = params_channels(params); |
4ca73043 | 408 | u32 word_width = params_width(params); |
2a266f8b | 409 | u32 val_cr4 = 0, val_cr5 = 0; |
c1df2964 ZW |
410 | u32 slots = (channels == 1) ? 2 : channels; |
411 | u32 slot_width = word_width; | |
c3ecef21 ZW |
412 | int ret; |
413 | ||
c1df2964 ZW |
414 | if (sai->slots) |
415 | slots = sai->slots; | |
416 | ||
417 | if (sai->slot_width) | |
418 | slot_width = sai->slot_width; | |
419 | ||
c3ecef21 ZW |
420 | if (!sai->is_slave_mode) { |
421 | ret = fsl_sai_set_bclk(cpu_dai, tx, | |
c1df2964 | 422 | slots * slot_width * params_rate(params)); |
c3ecef21 ZW |
423 | if (ret) |
424 | return ret; | |
425 | ||
426 | /* Do not enable the clock if it is already enabled */ | |
427 | if (!(sai->mclk_streams & BIT(substream->stream))) { | |
428 | ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); | |
429 | if (ret) | |
430 | return ret; | |
431 | ||
432 | sai->mclk_streams |= BIT(substream->stream); | |
433 | } | |
c3ecef21 | 434 | } |
43550821 | 435 | |
a3f7dcc9 | 436 | if (!sai->is_dsp_mode) |
c1df2964 | 437 | val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); |
a3f7dcc9 | 438 | |
c1df2964 ZW |
439 | val_cr5 |= FSL_SAI_CR5_WNW(slot_width); |
440 | val_cr5 |= FSL_SAI_CR5_W0W(slot_width); | |
43550821 | 441 | |
eadb0019 | 442 | if (sai->is_lsb_first) |
43550821 | 443 | val_cr5 |= FSL_SAI_CR5_FBT(0); |
72aa62be XL |
444 | else |
445 | val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); | |
43550821 | 446 | |
c1df2964 | 447 | val_cr4 |= FSL_SAI_CR4_FRSZ(slots); |
43550821 | 448 | |
51659ca0 ZW |
449 | /* |
450 | * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will | |
451 | * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), | |
452 | * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync | |
453 | * error. | |
454 | */ | |
455 | ||
456 | if (!sai->is_slave_mode) { | |
457 | if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { | |
458 | regmap_update_bits(sai->regmap, FSL_SAI_TCR4, | |
459 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
460 | val_cr4); | |
461 | regmap_update_bits(sai->regmap, FSL_SAI_TCR5, | |
462 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
463 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
464 | regmap_write(sai->regmap, FSL_SAI_TMR, | |
465 | ~0UL - ((1 << channels) - 1)); | |
466 | } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { | |
467 | regmap_update_bits(sai->regmap, FSL_SAI_RCR4, | |
468 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
469 | val_cr4); | |
470 | regmap_update_bits(sai->regmap, FSL_SAI_RCR5, | |
471 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
472 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
473 | regmap_write(sai->regmap, FSL_SAI_RMR, | |
474 | ~0UL - ((1 << channels) - 1)); | |
475 | } | |
476 | } | |
43550821 | 477 | |
2a266f8b NC |
478 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), |
479 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
480 | val_cr4); | |
481 | regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx), | |
482 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
483 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
484 | regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1)); | |
43550821 XL |
485 | |
486 | return 0; | |
487 | } | |
488 | ||
c3ecef21 ZW |
489 | static int fsl_sai_hw_free(struct snd_pcm_substream *substream, |
490 | struct snd_soc_dai *cpu_dai) | |
491 | { | |
492 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
493 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
494 | ||
495 | if (!sai->is_slave_mode && | |
496 | sai->mclk_streams & BIT(substream->stream)) { | |
497 | clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); | |
498 | sai->mclk_streams &= ~BIT(substream->stream); | |
499 | } | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
504 | ||
43550821 XL |
505 | static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, |
506 | struct snd_soc_dai *cpu_dai) | |
507 | { | |
508 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
e6b39846 | 509 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
c44b56af | 510 | u32 xcsr, count = 100; |
496a39d9 | 511 | |
a3f7dcc9 | 512 | /* |
08fdf65e NC |
513 | * Asynchronous mode: Clear SYNC for both Tx and Rx. |
514 | * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. | |
515 | * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. | |
a3f7dcc9 | 516 | */ |
3cc7780b SA |
517 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, |
518 | sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); | |
78957fc3 | 519 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC, |
08fdf65e | 520 | sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); |
43550821 | 521 | |
a3f7dcc9 XL |
522 | /* |
523 | * It is recommended that the transmitter is the last enabled | |
524 | * and the first disabled. | |
525 | */ | |
43550821 XL |
526 | switch (cmd) { |
527 | case SNDRV_PCM_TRIGGER_START: | |
528 | case SNDRV_PCM_TRIGGER_RESUME: | |
529 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
a3fdc674 NC |
530 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
531 | FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); | |
532 | ||
f4075a8f NC |
533 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, |
534 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); | |
535 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, | |
536 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); | |
e5d0fa9c | 537 | |
8abba5d6 NC |
538 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
539 | FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); | |
43550821 | 540 | break; |
43550821 XL |
541 | case SNDRV_PCM_TRIGGER_STOP: |
542 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
543 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
e6b39846 NC |
544 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
545 | FSL_SAI_CSR_FRDE, 0); | |
8abba5d6 NC |
546 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
547 | FSL_SAI_CSR_xIE_MASK, 0); | |
e6b39846 | 548 | |
f84526cf | 549 | /* Check if the opposite FRDE is also disabled */ |
f4075a8f NC |
550 | regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr); |
551 | if (!(xcsr & FSL_SAI_CSR_FRDE)) { | |
eff952b7 | 552 | /* Disable both directions and reset their FIFOs */ |
e6b39846 | 553 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, |
c44b56af | 554 | FSL_SAI_CSR_TERE, 0); |
e6b39846 | 555 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, |
c44b56af NC |
556 | FSL_SAI_CSR_TERE, 0); |
557 | ||
558 | /* TERE will remain set till the end of current frame */ | |
559 | do { | |
560 | udelay(10); | |
561 | regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr); | |
562 | } while (--count && xcsr & FSL_SAI_CSR_TERE); | |
563 | ||
564 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, | |
565 | FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); | |
566 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, | |
567 | FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); | |
3e3f8bd5 ZW |
568 | |
569 | /* | |
570 | * For sai master mode, after several open/close sai, | |
571 | * there will be no frame clock, and can't recover | |
572 | * anymore. Add software reset to fix this issue. | |
573 | * This is a hardware bug, and will be fix in the | |
574 | * next sai version. | |
575 | */ | |
576 | if (!sai->is_slave_mode) { | |
577 | /* Software Reset for both Tx and Rx */ | |
578 | regmap_write(sai->regmap, | |
579 | FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
580 | regmap_write(sai->regmap, | |
581 | FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
582 | /* Clear SR bit to finish the reset */ | |
583 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); | |
584 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
585 | } | |
43550821 | 586 | } |
43550821 XL |
587 | break; |
588 | default: | |
589 | return -EINVAL; | |
590 | } | |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
595 | static int fsl_sai_startup(struct snd_pcm_substream *substream, | |
596 | struct snd_soc_dai *cpu_dai) | |
597 | { | |
43550821 | 598 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b | 599 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
ca3e35c7 | 600 | struct device *dev = &sai->pdev->dev; |
ca3e35c7 NC |
601 | int ret; |
602 | ||
603 | ret = clk_prepare_enable(sai->bus_clk); | |
604 | if (ret) { | |
605 | dev_err(dev, "failed to enable bus clock: %d\n", ret); | |
606 | return ret; | |
607 | } | |
43550821 | 608 | |
2a266f8b | 609 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, |
78957fc3 XL |
610 | FSL_SAI_CR3_TRCE); |
611 | ||
c5f4823b ZW |
612 | ret = snd_pcm_hw_constraint_list(substream->runtime, 0, |
613 | SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); | |
614 | ||
615 | return ret; | |
43550821 XL |
616 | } |
617 | ||
618 | static void fsl_sai_shutdown(struct snd_pcm_substream *substream, | |
619 | struct snd_soc_dai *cpu_dai) | |
620 | { | |
621 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
2a266f8b | 622 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
43550821 | 623 | |
2a266f8b | 624 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0); |
ca3e35c7 NC |
625 | |
626 | clk_disable_unprepare(sai->bus_clk); | |
43550821 XL |
627 | } |
628 | ||
629 | static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { | |
630 | .set_sysclk = fsl_sai_set_dai_sysclk, | |
631 | .set_fmt = fsl_sai_set_dai_fmt, | |
c1df2964 | 632 | .set_tdm_slot = fsl_sai_set_dai_tdm_slot, |
43550821 | 633 | .hw_params = fsl_sai_hw_params, |
c3ecef21 | 634 | .hw_free = fsl_sai_hw_free, |
43550821 XL |
635 | .trigger = fsl_sai_trigger, |
636 | .startup = fsl_sai_startup, | |
637 | .shutdown = fsl_sai_shutdown, | |
638 | }; | |
639 | ||
640 | static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) | |
641 | { | |
642 | struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); | |
e6dc12d7 | 643 | |
376d1a92 NC |
644 | /* Software Reset for both Tx and Rx */ |
645 | regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
646 | regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
647 | /* Clear SR bit to finish the reset */ | |
648 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); | |
649 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
650 | ||
78957fc3 XL |
651 | regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK, |
652 | FSL_SAI_MAXBURST_TX * 2); | |
653 | regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK, | |
654 | FSL_SAI_MAXBURST_RX - 1); | |
43550821 | 655 | |
dd9f4060 XL |
656 | snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, |
657 | &sai->dma_params_rx); | |
43550821 XL |
658 | |
659 | snd_soc_dai_set_drvdata(cpu_dai, sai); | |
660 | ||
661 | return 0; | |
662 | } | |
663 | ||
43550821 XL |
664 | static struct snd_soc_dai_driver fsl_sai_dai = { |
665 | .probe = fsl_sai_dai_probe, | |
43550821 | 666 | .playback = { |
20d5b76f | 667 | .stream_name = "CPU-Playback", |
43550821 XL |
668 | .channels_min = 1, |
669 | .channels_max = 2, | |
c5f4823b ZW |
670 | .rate_min = 8000, |
671 | .rate_max = 192000, | |
672 | .rates = SNDRV_PCM_RATE_KNOT, | |
43550821 XL |
673 | .formats = FSL_SAI_FORMATS, |
674 | }, | |
675 | .capture = { | |
20d5b76f | 676 | .stream_name = "CPU-Capture", |
43550821 XL |
677 | .channels_min = 1, |
678 | .channels_max = 2, | |
c5f4823b ZW |
679 | .rate_min = 8000, |
680 | .rate_max = 192000, | |
681 | .rates = SNDRV_PCM_RATE_KNOT, | |
43550821 XL |
682 | .formats = FSL_SAI_FORMATS, |
683 | }, | |
684 | .ops = &fsl_sai_pcm_dai_ops, | |
685 | }; | |
686 | ||
687 | static const struct snd_soc_component_driver fsl_component = { | |
688 | .name = "fsl-sai", | |
689 | }; | |
690 | ||
3f6f5b0c ZW |
691 | static struct reg_default fsl_sai_reg_defaults[] = { |
692 | {FSL_SAI_TCR1, 0}, | |
693 | {FSL_SAI_TCR2, 0}, | |
694 | {FSL_SAI_TCR3, 0}, | |
695 | {FSL_SAI_TCR4, 0}, | |
696 | {FSL_SAI_TCR5, 0}, | |
697 | {FSL_SAI_TDR, 0}, | |
698 | {FSL_SAI_TMR, 0}, | |
699 | {FSL_SAI_RCR1, 0}, | |
700 | {FSL_SAI_RCR2, 0}, | |
701 | {FSL_SAI_RCR3, 0}, | |
702 | {FSL_SAI_RCR4, 0}, | |
703 | {FSL_SAI_RCR5, 0}, | |
704 | {FSL_SAI_RMR, 0}, | |
705 | }; | |
706 | ||
78957fc3 XL |
707 | static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) |
708 | { | |
709 | switch (reg) { | |
710 | case FSL_SAI_TCSR: | |
711 | case FSL_SAI_TCR1: | |
712 | case FSL_SAI_TCR2: | |
713 | case FSL_SAI_TCR3: | |
714 | case FSL_SAI_TCR4: | |
715 | case FSL_SAI_TCR5: | |
716 | case FSL_SAI_TFR: | |
717 | case FSL_SAI_TMR: | |
718 | case FSL_SAI_RCSR: | |
719 | case FSL_SAI_RCR1: | |
720 | case FSL_SAI_RCR2: | |
721 | case FSL_SAI_RCR3: | |
722 | case FSL_SAI_RCR4: | |
723 | case FSL_SAI_RCR5: | |
724 | case FSL_SAI_RDR: | |
725 | case FSL_SAI_RFR: | |
726 | case FSL_SAI_RMR: | |
727 | return true; | |
728 | default: | |
729 | return false; | |
730 | } | |
731 | } | |
732 | ||
733 | static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) | |
734 | { | |
735 | switch (reg) { | |
1fde5e83 ZW |
736 | case FSL_SAI_TCSR: |
737 | case FSL_SAI_RCSR: | |
78957fc3 XL |
738 | case FSL_SAI_TFR: |
739 | case FSL_SAI_RFR: | |
78957fc3 XL |
740 | case FSL_SAI_RDR: |
741 | return true; | |
742 | default: | |
743 | return false; | |
744 | } | |
78957fc3 XL |
745 | } |
746 | ||
747 | static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) | |
748 | { | |
749 | switch (reg) { | |
750 | case FSL_SAI_TCSR: | |
751 | case FSL_SAI_TCR1: | |
752 | case FSL_SAI_TCR2: | |
753 | case FSL_SAI_TCR3: | |
754 | case FSL_SAI_TCR4: | |
755 | case FSL_SAI_TCR5: | |
756 | case FSL_SAI_TDR: | |
757 | case FSL_SAI_TMR: | |
758 | case FSL_SAI_RCSR: | |
759 | case FSL_SAI_RCR1: | |
760 | case FSL_SAI_RCR2: | |
761 | case FSL_SAI_RCR3: | |
762 | case FSL_SAI_RCR4: | |
763 | case FSL_SAI_RCR5: | |
764 | case FSL_SAI_RMR: | |
765 | return true; | |
766 | default: | |
767 | return false; | |
768 | } | |
769 | } | |
770 | ||
014fd22e | 771 | static const struct regmap_config fsl_sai_regmap_config = { |
78957fc3 XL |
772 | .reg_bits = 32, |
773 | .reg_stride = 4, | |
774 | .val_bits = 32, | |
775 | ||
776 | .max_register = FSL_SAI_RMR, | |
3f6f5b0c ZW |
777 | .reg_defaults = fsl_sai_reg_defaults, |
778 | .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults), | |
78957fc3 XL |
779 | .readable_reg = fsl_sai_readable_reg, |
780 | .volatile_reg = fsl_sai_volatile_reg, | |
781 | .writeable_reg = fsl_sai_writeable_reg, | |
1fde5e83 | 782 | .cache_type = REGCACHE_FLAT, |
78957fc3 XL |
783 | }; |
784 | ||
43550821 XL |
785 | static int fsl_sai_probe(struct platform_device *pdev) |
786 | { | |
4e3a99f5 | 787 | struct device_node *np = pdev->dev.of_node; |
43550821 XL |
788 | struct fsl_sai *sai; |
789 | struct resource *res; | |
78957fc3 | 790 | void __iomem *base; |
ca3e35c7 NC |
791 | char tmp[8]; |
792 | int irq, ret, i; | |
43550821 XL |
793 | |
794 | sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); | |
795 | if (!sai) | |
796 | return -ENOMEM; | |
797 | ||
e2681a1b NC |
798 | sai->pdev = pdev; |
799 | ||
c7540644 NC |
800 | if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai")) |
801 | sai->sai_on_imx = true; | |
802 | ||
eadb0019 | 803 | sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); |
78957fc3 | 804 | |
43550821 | 805 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
78957fc3 XL |
806 | base = devm_ioremap_resource(&pdev->dev, res); |
807 | if (IS_ERR(base)) | |
808 | return PTR_ERR(base); | |
809 | ||
810 | sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, | |
ca3e35c7 NC |
811 | "bus", base, &fsl_sai_regmap_config); |
812 | ||
813 | /* Compatible with old DTB cases */ | |
814 | if (IS_ERR(sai->regmap)) | |
815 | sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, | |
816 | "sai", base, &fsl_sai_regmap_config); | |
78957fc3 XL |
817 | if (IS_ERR(sai->regmap)) { |
818 | dev_err(&pdev->dev, "regmap init failed\n"); | |
819 | return PTR_ERR(sai->regmap); | |
43550821 XL |
820 | } |
821 | ||
ca3e35c7 NC |
822 | /* No error out for old DTB cases but only mark the clock NULL */ |
823 | sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); | |
824 | if (IS_ERR(sai->bus_clk)) { | |
825 | dev_err(&pdev->dev, "failed to get bus clock: %ld\n", | |
826 | PTR_ERR(sai->bus_clk)); | |
827 | sai->bus_clk = NULL; | |
828 | } | |
829 | ||
c3ecef21 ZW |
830 | sai->mclk_clk[0] = sai->bus_clk; |
831 | for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { | |
832 | sprintf(tmp, "mclk%d", i); | |
ca3e35c7 NC |
833 | sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); |
834 | if (IS_ERR(sai->mclk_clk[i])) { | |
835 | dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", | |
836 | i + 1, PTR_ERR(sai->mclk_clk[i])); | |
837 | sai->mclk_clk[i] = NULL; | |
838 | } | |
839 | } | |
840 | ||
e2681a1b NC |
841 | irq = platform_get_irq(pdev, 0); |
842 | if (irq < 0) { | |
0954237f | 843 | dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); |
e2681a1b NC |
844 | return irq; |
845 | } | |
846 | ||
847 | ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai); | |
848 | if (ret) { | |
849 | dev_err(&pdev->dev, "failed to claim irq %u\n", irq); | |
850 | return ret; | |
851 | } | |
852 | ||
08fdf65e NC |
853 | /* Sync Tx with Rx as default by following old DT binding */ |
854 | sai->synchronous[RX] = true; | |
855 | sai->synchronous[TX] = false; | |
856 | fsl_sai_dai.symmetric_rates = 1; | |
857 | fsl_sai_dai.symmetric_channels = 1; | |
858 | fsl_sai_dai.symmetric_samplebits = 1; | |
859 | ||
ce7344a4 NC |
860 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && |
861 | of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
862 | /* error out if both synchronous and asynchronous are present */ | |
863 | dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); | |
864 | return -EINVAL; | |
865 | } | |
866 | ||
08fdf65e NC |
867 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { |
868 | /* Sync Rx with Tx */ | |
869 | sai->synchronous[RX] = false; | |
870 | sai->synchronous[TX] = true; | |
871 | } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
872 | /* Discard all settings for asynchronous mode */ | |
873 | sai->synchronous[RX] = false; | |
874 | sai->synchronous[TX] = false; | |
875 | fsl_sai_dai.symmetric_rates = 0; | |
876 | fsl_sai_dai.symmetric_channels = 0; | |
877 | fsl_sai_dai.symmetric_samplebits = 0; | |
878 | } | |
879 | ||
43550821 XL |
880 | sai->dma_params_rx.addr = res->start + FSL_SAI_RDR; |
881 | sai->dma_params_tx.addr = res->start + FSL_SAI_TDR; | |
882 | sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; | |
883 | sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; | |
884 | ||
43550821 XL |
885 | platform_set_drvdata(pdev, sai); |
886 | ||
887 | ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, | |
888 | &fsl_sai_dai, 1); | |
889 | if (ret) | |
890 | return ret; | |
891 | ||
c7540644 | 892 | if (sai->sai_on_imx) |
0d69e0dd | 893 | return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE); |
c7540644 | 894 | else |
acde50a7 | 895 | return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); |
43550821 XL |
896 | } |
897 | ||
898 | static const struct of_device_id fsl_sai_ids[] = { | |
899 | { .compatible = "fsl,vf610-sai", }, | |
c7540644 | 900 | { .compatible = "fsl,imx6sx-sai", }, |
43550821 XL |
901 | { /* sentinel */ } |
902 | }; | |
c759241f | 903 | MODULE_DEVICE_TABLE(of, fsl_sai_ids); |
43550821 | 904 | |
739146b6 | 905 | #ifdef CONFIG_PM_SLEEP |
1fde5e83 ZW |
906 | static int fsl_sai_suspend(struct device *dev) |
907 | { | |
908 | struct fsl_sai *sai = dev_get_drvdata(dev); | |
909 | ||
910 | regcache_cache_only(sai->regmap, true); | |
911 | regcache_mark_dirty(sai->regmap); | |
912 | ||
913 | return 0; | |
914 | } | |
915 | ||
916 | static int fsl_sai_resume(struct device *dev) | |
917 | { | |
918 | struct fsl_sai *sai = dev_get_drvdata(dev); | |
919 | ||
920 | regcache_cache_only(sai->regmap, false); | |
921 | regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
922 | regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
512feb4e | 923 | usleep_range(1000, 2000); |
1fde5e83 ZW |
924 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); |
925 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
926 | return regcache_sync(sai->regmap); | |
927 | } | |
928 | #endif /* CONFIG_PM_SLEEP */ | |
929 | ||
930 | static const struct dev_pm_ops fsl_sai_pm_ops = { | |
931 | SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume) | |
932 | }; | |
933 | ||
43550821 XL |
934 | static struct platform_driver fsl_sai_driver = { |
935 | .probe = fsl_sai_probe, | |
43550821 XL |
936 | .driver = { |
937 | .name = "fsl-sai", | |
1fde5e83 | 938 | .pm = &fsl_sai_pm_ops, |
43550821 XL |
939 | .of_match_table = fsl_sai_ids, |
940 | }, | |
941 | }; | |
942 | module_platform_driver(fsl_sai_driver); | |
943 | ||
944 | MODULE_DESCRIPTION("Freescale Soc SAI Interface"); | |
945 | MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); | |
946 | MODULE_ALIAS("platform:fsl-sai"); | |
947 | MODULE_LICENSE("GPL"); |