projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 43550821 XL |
1 | /* |
| 2 | * Copyright 2012-2013 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef __FSL_SAI_H | |
| 10 | #define __FSL_SAI_H | |
| 11 | ||
| 12 | #include <sound/dmaengine_pcm.h> | |
| 13 | ||
| 14 | #define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
| 15 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
| 16 | SNDRV_PCM_FMTBIT_S24_LE) | |
| 17 | ||
| 78957fc3 XL |
18 | /* SAI Register Map Register */ |
| 19 | #define FSL_SAI_TCSR 0x00 /* SAI Transmit Control */ | |
| 20 | #define FSL_SAI_TCR1 0x04 /* SAI Transmit Configuration 1 */ | |
| 21 | #define FSL_SAI_TCR2 0x08 /* SAI Transmit Configuration 2 */ | |
| 22 | #define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */ | |
| 23 | #define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */ | |
| 24 | #define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */ | |
| 25 | #define FSL_SAI_TDR 0x20 /* SAI Transmit Data */ | |
| 26 | #define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */ | |
| 27 | #define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */ | |
| 28 | #define FSL_SAI_RCSR 0x80 /* SAI Receive Control */ | |
| 29 | #define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */ | |
| 30 | #define FSL_SAI_RCR2 0x88 /* SAI Receive Configuration 2 */ | |
| 31 | #define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */ | |
| 32 | #define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */ | |
| 33 | #define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */ | |
| 34 | #define FSL_SAI_RDR 0xa0 /* SAI Receive Data */ | |
| 35 | #define FSL_SAI_RFR 0xc0 /* SAI Receive FIFO */ | |
| 36 | #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */ | |
| 37 | ||
| 43550821 | 38 | /* SAI Transmit/Recieve Control Register */ |
| 43550821 XL |
39 | #define FSL_SAI_CSR_TERE BIT(31) |
| 40 | #define FSL_SAI_CSR_FWF BIT(17) | |
| 41 | #define FSL_SAI_CSR_FRIE BIT(8) | |
| 42 | #define FSL_SAI_CSR_FRDE BIT(0) | |
| 43 | ||
| 43550821 | 44 | /* SAI Transmit and Recieve Configuration 1 Register */ |
| 78957fc3 | 45 | #define FSL_SAI_CR1_RFW_MASK 0x1f |
| 43550821 XL |
46 | |
| 47 | /* SAI Transmit and Recieve Configuration 2 Register */ | |
| 43550821 XL |
48 | #define FSL_SAI_CR2_SYNC BIT(30) |
| 49 | #define FSL_SAI_CR2_MSEL_MASK (0xff << 26) | |
| 50 | #define FSL_SAI_CR2_MSEL_BUS 0 | |
| 51 | #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26) | |
| 52 | #define FSL_SAI_CR2_MSEL_MCLK2 BIT(27) | |
| 53 | #define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27)) | |
| 54 | #define FSL_SAI_CR2_BCP BIT(25) | |
| 55 | #define FSL_SAI_CR2_BCD_MSTR BIT(24) | |
| 56 | ||
| 57 | /* SAI Transmit and Recieve Configuration 3 Register */ | |
| 43550821 XL |
58 | #define FSL_SAI_CR3_TRCE BIT(16) |
| 59 | #define FSL_SAI_CR3_WDFL(x) (x) | |
| 60 | #define FSL_SAI_CR3_WDFL_MASK 0x1f | |
| 61 | ||
| 62 | /* SAI Transmit and Recieve Configuration 4 Register */ | |
| 43550821 XL |
63 | #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16) |
| 64 | #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) | |
| 65 | #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) | |
| 66 | #define FSL_SAI_CR4_SYWD_MASK (0x1f << 8) | |
| 67 | #define FSL_SAI_CR4_MF BIT(4) | |
| 68 | #define FSL_SAI_CR4_FSE BIT(3) | |
| 69 | #define FSL_SAI_CR4_FSP BIT(1) | |
| 70 | #define FSL_SAI_CR4_FSD_MSTR BIT(0) | |
| 71 | ||
| 72 | /* SAI Transmit and Recieve Configuration 5 Register */ | |
| 43550821 XL |
73 | #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24) |
| 74 | #define FSL_SAI_CR5_WNW_MASK (0x1f << 24) | |
| 75 | #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16) | |
| 76 | #define FSL_SAI_CR5_W0W_MASK (0x1f << 16) | |
| 77 | #define FSL_SAI_CR5_FBT(x) ((x) << 8) | |
| 78 | #define FSL_SAI_CR5_FBT_MASK (0x1f << 8) | |
| 79 | ||
| 80 | /* SAI type */ | |
| 81 | #define FSL_SAI_DMA BIT(0) | |
| 82 | #define FSL_SAI_USE_AC97 BIT(1) | |
| 83 | #define FSL_SAI_NET BIT(2) | |
| 84 | #define FSL_SAI_TRA_SYN BIT(3) | |
| 85 | #define FSL_SAI_REC_SYN BIT(4) | |
| 86 | #define FSL_SAI_USE_I2S_SLAVE BIT(5) | |
| 87 | ||
| 88 | #define FSL_FMT_TRANSMITTER 0 | |
| 89 | #define FSL_FMT_RECEIVER 1 | |
| 90 | ||
| 91 | /* SAI clock sources */ | |
| 92 | #define FSL_SAI_CLK_BUS 0 | |
| 93 | #define FSL_SAI_CLK_MAST1 1 | |
| 94 | #define FSL_SAI_CLK_MAST2 2 | |
| 95 | #define FSL_SAI_CLK_MAST3 3 | |
| 96 | ||
| 97 | /* SAI data transfer numbers per DMA request */ | |
| 98 | #define FSL_SAI_MAXBURST_TX 6 | |
| 99 | #define FSL_SAI_MAXBURST_RX 6 | |
| 100 | ||
| 101 | struct fsl_sai { | |
| 78957fc3 | 102 | struct regmap *regmap; |
| 43550821 XL |
103 | |
| 104 | bool big_endian_regs; | |
| 105 | bool big_endian_data; | |
| 106 | ||
| 107 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
| 108 | struct snd_dmaengine_dai_dma_data dma_params_tx; | |
| 109 | }; | |
| 110 | ||
| 111 | #endif /* __FSL_SAI_H */ |