Commit | Line | Data |
---|---|---|
17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
17467f23 TT |
11 | */ |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/delay.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
f0fba2ad | 19 | #include <linux/of_platform.h> |
17467f23 | 20 | |
17467f23 TT |
21 | #include <sound/core.h> |
22 | #include <sound/pcm.h> | |
23 | #include <sound/pcm_params.h> | |
24 | #include <sound/initval.h> | |
25 | #include <sound/soc.h> | |
26 | ||
17467f23 TT |
27 | #include "fsl_ssi.h" |
28 | ||
29 | /** | |
30 | * FSLSSI_I2S_RATES: sample rates supported by the I2S | |
31 | * | |
32 | * This driver currently only supports the SSI running in I2S slave mode, | |
33 | * which means the codec determines the sample rate. Therefore, we tell | |
34 | * ALSA that we support all rates and let the codec driver decide what rates | |
35 | * are really supported. | |
36 | */ | |
37 | #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ | |
38 | SNDRV_PCM_RATE_CONTINUOUS) | |
39 | ||
40 | /** | |
41 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
42 | * | |
43 | * This driver currently only supports the SSI running in I2S slave mode. | |
44 | * | |
45 | * The SSI has a limitation in that the samples must be in the same byte | |
46 | * order as the host CPU. This is because when multiple bytes are written | |
47 | * to the STX register, the bytes and bits must be written in the same | |
48 | * order. The STX is a shift register, so all the bits need to be aligned | |
49 | * (bit-endianness must match byte-endianness). Processors typically write | |
50 | * the bits within a byte in the same order that the bytes of a word are | |
51 | * written in. So if the host CPU is big-endian, then only big-endian | |
52 | * samples will be written to STX properly. | |
53 | */ | |
54 | #ifdef __BIG_ENDIAN | |
55 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
56 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
57 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
58 | #else | |
59 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
60 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
61 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
62 | #endif | |
63 | ||
d5a908b2 TT |
64 | /* SIER bitflag of interrupts to enable */ |
65 | #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \ | |
66 | CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \ | |
67 | CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \ | |
68 | CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \ | |
69 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN) | |
70 | ||
17467f23 TT |
71 | /** |
72 | * fsl_ssi_private: per-SSI private data | |
73 | * | |
17467f23 TT |
74 | * @ssi: pointer to the SSI's registers |
75 | * @ssi_phys: physical address of the SSI registers | |
76 | * @irq: IRQ of this SSI | |
be41e941 TT |
77 | * @first_stream: pointer to the stream that was opened first |
78 | * @second_stream: pointer to second stream | |
17467f23 TT |
79 | * @playback: the number of playback streams opened |
80 | * @capture: the number of capture streams opened | |
a454dad1 | 81 | * @asynchronous: 0=synchronous mode, 1=asynchronous mode |
17467f23 TT |
82 | * @cpu_dai: the CPU DAI for this device |
83 | * @dev_attr: the sysfs device attribute structure | |
84 | * @stats: SSI statistics | |
f0fba2ad | 85 | * @name: name for this device |
17467f23 TT |
86 | */ |
87 | struct fsl_ssi_private { | |
17467f23 TT |
88 | struct ccsr_ssi __iomem *ssi; |
89 | dma_addr_t ssi_phys; | |
90 | unsigned int irq; | |
be41e941 TT |
91 | struct snd_pcm_substream *first_stream; |
92 | struct snd_pcm_substream *second_stream; | |
17467f23 TT |
93 | unsigned int playback; |
94 | unsigned int capture; | |
a454dad1 | 95 | int asynchronous; |
8e9d8690 | 96 | unsigned int fifo_depth; |
f0fba2ad | 97 | struct snd_soc_dai_driver cpu_dai_drv; |
17467f23 | 98 | struct device_attribute dev_attr; |
f0fba2ad | 99 | struct platform_device *pdev; |
17467f23 TT |
100 | |
101 | struct { | |
102 | unsigned int rfrc; | |
103 | unsigned int tfrc; | |
104 | unsigned int cmdau; | |
105 | unsigned int cmddu; | |
106 | unsigned int rxt; | |
107 | unsigned int rdr1; | |
108 | unsigned int rdr0; | |
109 | unsigned int tde1; | |
110 | unsigned int tde0; | |
111 | unsigned int roe1; | |
112 | unsigned int roe0; | |
113 | unsigned int tue1; | |
114 | unsigned int tue0; | |
115 | unsigned int tfs; | |
116 | unsigned int rfs; | |
117 | unsigned int tls; | |
118 | unsigned int rls; | |
119 | unsigned int rff1; | |
120 | unsigned int rff0; | |
121 | unsigned int tfe1; | |
122 | unsigned int tfe0; | |
123 | } stats; | |
f0fba2ad LG |
124 | |
125 | char name[1]; | |
17467f23 TT |
126 | }; |
127 | ||
128 | /** | |
129 | * fsl_ssi_isr: SSI interrupt handler | |
130 | * | |
131 | * Although it's possible to use the interrupt handler to send and receive | |
132 | * data to/from the SSI, we use the DMA instead. Programming is more | |
133 | * complicated, but the performance is much better. | |
134 | * | |
135 | * This interrupt handler is used only to gather statistics. | |
136 | * | |
137 | * @irq: IRQ of the SSI device | |
138 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
139 | */ | |
140 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
141 | { | |
142 | struct fsl_ssi_private *ssi_private = dev_id; | |
143 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
144 | irqreturn_t ret = IRQ_NONE; | |
145 | __be32 sisr; | |
146 | __be32 sisr2 = 0; | |
147 | ||
148 | /* We got an interrupt, so read the status register to see what we | |
149 | were interrupted for. We mask it with the Interrupt Enable register | |
150 | so that we only check for events that we're interested in. | |
151 | */ | |
d5a908b2 | 152 | sisr = in_be32(&ssi->sisr) & SIER_FLAGS; |
17467f23 TT |
153 | |
154 | if (sisr & CCSR_SSI_SISR_RFRC) { | |
155 | ssi_private->stats.rfrc++; | |
156 | sisr2 |= CCSR_SSI_SISR_RFRC; | |
157 | ret = IRQ_HANDLED; | |
158 | } | |
159 | ||
160 | if (sisr & CCSR_SSI_SISR_TFRC) { | |
161 | ssi_private->stats.tfrc++; | |
162 | sisr2 |= CCSR_SSI_SISR_TFRC; | |
163 | ret = IRQ_HANDLED; | |
164 | } | |
165 | ||
166 | if (sisr & CCSR_SSI_SISR_CMDAU) { | |
167 | ssi_private->stats.cmdau++; | |
168 | ret = IRQ_HANDLED; | |
169 | } | |
170 | ||
171 | if (sisr & CCSR_SSI_SISR_CMDDU) { | |
172 | ssi_private->stats.cmddu++; | |
173 | ret = IRQ_HANDLED; | |
174 | } | |
175 | ||
176 | if (sisr & CCSR_SSI_SISR_RXT) { | |
177 | ssi_private->stats.rxt++; | |
178 | ret = IRQ_HANDLED; | |
179 | } | |
180 | ||
181 | if (sisr & CCSR_SSI_SISR_RDR1) { | |
182 | ssi_private->stats.rdr1++; | |
183 | ret = IRQ_HANDLED; | |
184 | } | |
185 | ||
186 | if (sisr & CCSR_SSI_SISR_RDR0) { | |
187 | ssi_private->stats.rdr0++; | |
188 | ret = IRQ_HANDLED; | |
189 | } | |
190 | ||
191 | if (sisr & CCSR_SSI_SISR_TDE1) { | |
192 | ssi_private->stats.tde1++; | |
193 | ret = IRQ_HANDLED; | |
194 | } | |
195 | ||
196 | if (sisr & CCSR_SSI_SISR_TDE0) { | |
197 | ssi_private->stats.tde0++; | |
198 | ret = IRQ_HANDLED; | |
199 | } | |
200 | ||
201 | if (sisr & CCSR_SSI_SISR_ROE1) { | |
202 | ssi_private->stats.roe1++; | |
203 | sisr2 |= CCSR_SSI_SISR_ROE1; | |
204 | ret = IRQ_HANDLED; | |
205 | } | |
206 | ||
207 | if (sisr & CCSR_SSI_SISR_ROE0) { | |
208 | ssi_private->stats.roe0++; | |
209 | sisr2 |= CCSR_SSI_SISR_ROE0; | |
210 | ret = IRQ_HANDLED; | |
211 | } | |
212 | ||
213 | if (sisr & CCSR_SSI_SISR_TUE1) { | |
214 | ssi_private->stats.tue1++; | |
215 | sisr2 |= CCSR_SSI_SISR_TUE1; | |
216 | ret = IRQ_HANDLED; | |
217 | } | |
218 | ||
219 | if (sisr & CCSR_SSI_SISR_TUE0) { | |
220 | ssi_private->stats.tue0++; | |
221 | sisr2 |= CCSR_SSI_SISR_TUE0; | |
222 | ret = IRQ_HANDLED; | |
223 | } | |
224 | ||
225 | if (sisr & CCSR_SSI_SISR_TFS) { | |
226 | ssi_private->stats.tfs++; | |
227 | ret = IRQ_HANDLED; | |
228 | } | |
229 | ||
230 | if (sisr & CCSR_SSI_SISR_RFS) { | |
231 | ssi_private->stats.rfs++; | |
232 | ret = IRQ_HANDLED; | |
233 | } | |
234 | ||
235 | if (sisr & CCSR_SSI_SISR_TLS) { | |
236 | ssi_private->stats.tls++; | |
237 | ret = IRQ_HANDLED; | |
238 | } | |
239 | ||
240 | if (sisr & CCSR_SSI_SISR_RLS) { | |
241 | ssi_private->stats.rls++; | |
242 | ret = IRQ_HANDLED; | |
243 | } | |
244 | ||
245 | if (sisr & CCSR_SSI_SISR_RFF1) { | |
246 | ssi_private->stats.rff1++; | |
247 | ret = IRQ_HANDLED; | |
248 | } | |
249 | ||
250 | if (sisr & CCSR_SSI_SISR_RFF0) { | |
251 | ssi_private->stats.rff0++; | |
252 | ret = IRQ_HANDLED; | |
253 | } | |
254 | ||
255 | if (sisr & CCSR_SSI_SISR_TFE1) { | |
256 | ssi_private->stats.tfe1++; | |
257 | ret = IRQ_HANDLED; | |
258 | } | |
259 | ||
260 | if (sisr & CCSR_SSI_SISR_TFE0) { | |
261 | ssi_private->stats.tfe0++; | |
262 | ret = IRQ_HANDLED; | |
263 | } | |
264 | ||
265 | /* Clear the bits that we set */ | |
266 | if (sisr2) | |
267 | out_be32(&ssi->sisr, sisr2); | |
268 | ||
269 | return ret; | |
270 | } | |
271 | ||
272 | /** | |
273 | * fsl_ssi_startup: create a new substream | |
274 | * | |
275 | * This is the first function called when a stream is opened. | |
276 | * | |
277 | * If this is the first stream open, then grab the IRQ and program most of | |
278 | * the SSI registers. | |
279 | */ | |
dee89c4d MB |
280 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
281 | struct snd_soc_dai *dai) | |
17467f23 TT |
282 | { |
283 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 284 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 TT |
285 | |
286 | /* | |
287 | * If this is the first stream opened, then request the IRQ | |
288 | * and initialize the SSI registers. | |
289 | */ | |
290 | if (!ssi_private->playback && !ssi_private->capture) { | |
291 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
292 | int ret; | |
293 | ||
f0fba2ad | 294 | /* The 'name' should not have any slashes in it. */ |
17467f23 TT |
295 | ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, |
296 | ssi_private->name, ssi_private); | |
297 | if (ret < 0) { | |
298 | dev_err(substream->pcm->card->dev, | |
299 | "could not claim irq %u\n", ssi_private->irq); | |
300 | return ret; | |
301 | } | |
302 | ||
303 | /* | |
304 | * Section 16.5 of the MPC8610 reference manual says that the | |
305 | * SSI needs to be disabled before updating the registers we set | |
306 | * here. | |
307 | */ | |
308 | clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); | |
309 | ||
310 | /* | |
311 | * Program the SSI into I2S Slave Non-Network Synchronous mode. | |
312 | * Also enable the transmit and receive FIFO. | |
313 | * | |
314 | * FIXME: Little-endian samples require a different shift dir | |
315 | */ | |
a454dad1 TT |
316 | clrsetbits_be32(&ssi->scr, |
317 | CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN, | |
318 | CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE | |
319 | | (ssi_private->asynchronous ? 0 : CCSR_SSI_SCR_SYN)); | |
17467f23 TT |
320 | |
321 | out_be32(&ssi->stcr, | |
322 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 | | |
323 | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS | | |
324 | CCSR_SSI_STCR_TSCKP); | |
325 | ||
326 | out_be32(&ssi->srcr, | |
327 | CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 | | |
328 | CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS | | |
329 | CCSR_SSI_SRCR_RSCKP); | |
330 | ||
331 | /* | |
332 | * The DC and PM bits are only used if the SSI is the clock | |
333 | * master. | |
334 | */ | |
335 | ||
336 | /* 4. Enable the interrupts and DMA requests */ | |
d5a908b2 | 337 | out_be32(&ssi->sier, SIER_FLAGS); |
17467f23 TT |
338 | |
339 | /* | |
340 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We | |
8e9d8690 TT |
341 | * don't use FIFO 1. We program the transmit water to signal a |
342 | * DMA transfer if there are only two (or fewer) elements left | |
343 | * in the FIFO. Two elements equals one frame (left channel, | |
344 | * right channel). This value, however, depends on the depth of | |
345 | * the transmit buffer. | |
346 | * | |
347 | * We program the receive FIFO to notify us if at least two | |
348 | * elements (one frame) have been written to the FIFO. We could | |
349 | * make this value larger (and maybe we should), but this way | |
350 | * data will be written to memory as soon as it's available. | |
17467f23 TT |
351 | */ |
352 | out_be32(&ssi->sfcsr, | |
8e9d8690 TT |
353 | CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) | |
354 | CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2)); | |
17467f23 TT |
355 | |
356 | /* | |
357 | * We keep the SSI disabled because if we enable it, then the | |
358 | * DMA controller will start. It's not supposed to start until | |
359 | * the SCR.TE (or SCR.RE) bit is set, but it does anyway. The | |
360 | * DMA controller will transfer one "BWC" of data (i.e. the | |
361 | * amount of data that the MR.BWC bits are set to). The reason | |
362 | * this is bad is because at this point, the PCM driver has not | |
363 | * finished initializing the DMA controller. | |
364 | */ | |
365 | } | |
366 | ||
be41e941 TT |
367 | if (!ssi_private->first_stream) |
368 | ssi_private->first_stream = substream; | |
369 | else { | |
370 | /* This is the second stream open, so we need to impose sample | |
371 | * rate and maybe sample size constraints. Note that this can | |
372 | * cause a race condition if the second stream is opened before | |
373 | * the first stream is fully initialized. | |
374 | * | |
375 | * We provide some protection by checking to make sure the first | |
376 | * stream is initialized, but it's not perfect. ALSA sometimes | |
377 | * re-initializes the driver with a different sample rate or | |
378 | * size. If the second stream is opened before the first stream | |
379 | * has received its final parameters, then the second stream may | |
380 | * be constrained to the wrong sample rate or size. | |
381 | * | |
382 | * FIXME: This code does not handle opening and closing streams | |
383 | * repeatedly. If you open two streams and then close the first | |
384 | * one, you may not be able to open another stream until you | |
385 | * close the second one as well. | |
386 | */ | |
387 | struct snd_pcm_runtime *first_runtime = | |
388 | ssi_private->first_stream->runtime; | |
389 | ||
08d15f03 | 390 | if (!first_runtime->sample_bits) { |
be41e941 | 391 | dev_err(substream->pcm->card->dev, |
08d15f03 | 392 | "set sample size in %s stream first\n", |
be41e941 TT |
393 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK |
394 | ? "capture" : "playback"); | |
395 | return -EAGAIN; | |
396 | } | |
397 | ||
a454dad1 TT |
398 | /* If we're in synchronous mode, then we need to constrain |
399 | * the sample size as well. We don't support independent sample | |
400 | * rates in asynchronous mode. | |
401 | */ | |
402 | if (!ssi_private->asynchronous) | |
403 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
404 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
405 | first_runtime->sample_bits, | |
406 | first_runtime->sample_bits); | |
be41e941 TT |
407 | |
408 | ssi_private->second_stream = substream; | |
409 | } | |
410 | ||
17467f23 TT |
411 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
412 | ssi_private->playback++; | |
413 | ||
414 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
415 | ssi_private->capture++; | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
420 | /** | |
85ef2375 | 421 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
422 | * |
423 | * Most of the SSI registers have been programmed in the startup function, | |
424 | * but the word length must be programmed here. Unfortunately, programming | |
425 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
426 | * cause a problem with supporting simultaneous playback and capture. If | |
427 | * the SSI is already playing a stream, then that stream may be temporarily | |
428 | * stopped when you start capture. | |
429 | * | |
430 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
431 | * clock master. | |
432 | */ | |
85ef2375 TT |
433 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
434 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 435 | { |
f0fba2ad | 436 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
17467f23 | 437 | |
be41e941 | 438 | if (substream == ssi_private->first_stream) { |
85ef2375 TT |
439 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
440 | unsigned int sample_size = | |
441 | snd_pcm_format_width(params_format(hw_params)); | |
a454dad1 | 442 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); |
17467f23 | 443 | |
be41e941 | 444 | /* The SSI should always be disabled at this points (SSIEN=0) */ |
17467f23 | 445 | |
be41e941 | 446 | /* In synchronous mode, the SSI uses STCCR for capture */ |
a454dad1 TT |
447 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || |
448 | !ssi_private->asynchronous) | |
449 | clrsetbits_be32(&ssi->stccr, | |
450 | CCSR_SSI_SxCCR_WL_MASK, wl); | |
451 | else | |
452 | clrsetbits_be32(&ssi->srccr, | |
453 | CCSR_SSI_SxCCR_WL_MASK, wl); | |
be41e941 | 454 | } |
17467f23 TT |
455 | |
456 | return 0; | |
457 | } | |
458 | ||
459 | /** | |
460 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
461 | * | |
462 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
463 | * transfer of data. | |
464 | * | |
465 | * The DMA channel is in external master start and pause mode, which | |
466 | * means the SSI completely controls the flow of data. | |
467 | */ | |
dee89c4d MB |
468 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
469 | struct snd_soc_dai *dai) | |
17467f23 TT |
470 | { |
471 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 472 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 TT |
473 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
474 | ||
475 | switch (cmd) { | |
476 | case SNDRV_PCM_TRIGGER_START: | |
3a638ff2 | 477 | clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); |
17467f23 | 478 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 479 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
be41e941 TT |
480 | setbits32(&ssi->scr, |
481 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE); | |
a4d11fe5 | 482 | else |
be41e941 TT |
483 | setbits32(&ssi->scr, |
484 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE); | |
17467f23 TT |
485 | break; |
486 | ||
487 | case SNDRV_PCM_TRIGGER_STOP: | |
17467f23 TT |
488 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
489 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
490 | clrbits32(&ssi->scr, CCSR_SSI_SCR_TE); | |
491 | else | |
492 | clrbits32(&ssi->scr, CCSR_SSI_SCR_RE); | |
493 | break; | |
494 | ||
495 | default: | |
496 | return -EINVAL; | |
497 | } | |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
502 | /** | |
503 | * fsl_ssi_shutdown: shutdown the SSI | |
504 | * | |
505 | * Shutdown the SSI if there are no other substreams open. | |
506 | */ | |
dee89c4d MB |
507 | static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, |
508 | struct snd_soc_dai *dai) | |
17467f23 TT |
509 | { |
510 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 511 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 TT |
512 | |
513 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
514 | ssi_private->playback--; | |
515 | ||
516 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
517 | ssi_private->capture--; | |
518 | ||
be41e941 TT |
519 | if (ssi_private->first_stream == substream) |
520 | ssi_private->first_stream = ssi_private->second_stream; | |
521 | ||
522 | ssi_private->second_stream = NULL; | |
523 | ||
17467f23 TT |
524 | /* |
525 | * If this is the last active substream, disable the SSI and release | |
526 | * the IRQ. | |
527 | */ | |
528 | if (!ssi_private->playback && !ssi_private->capture) { | |
529 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
530 | ||
531 | clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); | |
532 | ||
533 | free_irq(ssi_private->irq, ssi_private); | |
534 | } | |
535 | } | |
536 | ||
6335d055 EM |
537 | static struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
538 | .startup = fsl_ssi_startup, | |
539 | .hw_params = fsl_ssi_hw_params, | |
540 | .shutdown = fsl_ssi_shutdown, | |
541 | .trigger = fsl_ssi_trigger, | |
6335d055 EM |
542 | }; |
543 | ||
f0fba2ad LG |
544 | /* Template for the CPU dai driver structure */ |
545 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
17467f23 TT |
546 | .playback = { |
547 | /* The SSI does not support monaural audio. */ | |
548 | .channels_min = 2, | |
549 | .channels_max = 2, | |
550 | .rates = FSLSSI_I2S_RATES, | |
551 | .formats = FSLSSI_I2S_FORMATS, | |
552 | }, | |
553 | .capture = { | |
554 | .channels_min = 2, | |
555 | .channels_max = 2, | |
556 | .rates = FSLSSI_I2S_RATES, | |
557 | .formats = FSLSSI_I2S_FORMATS, | |
558 | }, | |
6335d055 | 559 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
560 | }; |
561 | ||
d5a908b2 TT |
562 | /* Show the statistics of a flag only if its interrupt is enabled. The |
563 | * compiler will optimze this code to a no-op if the interrupt is not | |
564 | * enabled. | |
565 | */ | |
566 | #define SIER_SHOW(flag, name) \ | |
567 | do { \ | |
568 | if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \ | |
569 | length += sprintf(buf + length, #name "=%u\n", \ | |
570 | ssi_private->stats.name); \ | |
571 | } while (0) | |
572 | ||
573 | ||
17467f23 TT |
574 | /** |
575 | * fsl_sysfs_ssi_show: display SSI statistics | |
576 | * | |
d5a908b2 TT |
577 | * Display the statistics for the current SSI device. To avoid confusion, |
578 | * we only show those counts that are enabled. | |
17467f23 TT |
579 | */ |
580 | static ssize_t fsl_sysfs_ssi_show(struct device *dev, | |
581 | struct device_attribute *attr, char *buf) | |
582 | { | |
583 | struct fsl_ssi_private *ssi_private = | |
d5a908b2 TT |
584 | container_of(attr, struct fsl_ssi_private, dev_attr); |
585 | ssize_t length = 0; | |
586 | ||
587 | SIER_SHOW(RFRC_EN, rfrc); | |
588 | SIER_SHOW(TFRC_EN, tfrc); | |
589 | SIER_SHOW(CMDAU_EN, cmdau); | |
590 | SIER_SHOW(CMDDU_EN, cmddu); | |
591 | SIER_SHOW(RXT_EN, rxt); | |
592 | SIER_SHOW(RDR1_EN, rdr1); | |
593 | SIER_SHOW(RDR0_EN, rdr0); | |
594 | SIER_SHOW(TDE1_EN, tde1); | |
595 | SIER_SHOW(TDE0_EN, tde0); | |
596 | SIER_SHOW(ROE1_EN, roe1); | |
597 | SIER_SHOW(ROE0_EN, roe0); | |
598 | SIER_SHOW(TUE1_EN, tue1); | |
599 | SIER_SHOW(TUE0_EN, tue0); | |
600 | SIER_SHOW(TFS_EN, tfs); | |
601 | SIER_SHOW(RFS_EN, rfs); | |
602 | SIER_SHOW(TLS_EN, tls); | |
603 | SIER_SHOW(RLS_EN, rls); | |
604 | SIER_SHOW(RFF1_EN, rff1); | |
605 | SIER_SHOW(RFF0_EN, rff0); | |
606 | SIER_SHOW(TFE1_EN, tfe1); | |
607 | SIER_SHOW(TFE0_EN, tfe0); | |
17467f23 TT |
608 | |
609 | return length; | |
610 | } | |
611 | ||
612 | /** | |
f0fba2ad | 613 | * Make every character in a string lower-case |
17467f23 | 614 | */ |
f0fba2ad LG |
615 | static void make_lowercase(char *s) |
616 | { | |
617 | char *p = s; | |
618 | char c; | |
619 | ||
620 | while ((c = *p)) { | |
621 | if ((c >= 'A') && (c <= 'Z')) | |
622 | *p = c + ('a' - 'A'); | |
623 | p++; | |
624 | } | |
625 | } | |
626 | ||
f07eb223 | 627 | static int __devinit fsl_ssi_probe(struct platform_device *pdev) |
17467f23 | 628 | { |
17467f23 TT |
629 | struct fsl_ssi_private *ssi_private; |
630 | int ret = 0; | |
87a0632b | 631 | struct device_attribute *dev_attr = NULL; |
38fec727 | 632 | struct device_node *np = pdev->dev.of_node; |
f0fba2ad | 633 | const char *p, *sprop; |
8e9d8690 | 634 | const uint32_t *iprop; |
f0fba2ad LG |
635 | struct resource res; |
636 | char name[64]; | |
17467f23 | 637 | |
ff71334a TT |
638 | /* SSIs that are not connected on the board should have a |
639 | * status = "disabled" | |
640 | * property in their device tree nodes. | |
f0fba2ad | 641 | */ |
ff71334a | 642 | if (!of_device_is_available(np)) |
f0fba2ad LG |
643 | return -ENODEV; |
644 | ||
ff71334a TT |
645 | /* Check for a codec-handle property. */ |
646 | if (!of_get_property(np, "codec-handle", NULL)) { | |
38fec727 | 647 | dev_err(&pdev->dev, "missing codec-handle property\n"); |
ff71334a TT |
648 | return -ENODEV; |
649 | } | |
650 | ||
f0fba2ad LG |
651 | /* We only support the SSI in "I2S Slave" mode */ |
652 | sprop = of_get_property(np, "fsl,mode", NULL); | |
653 | if (!sprop || strcmp(sprop, "i2s-slave")) { | |
38fec727 | 654 | dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop); |
f0fba2ad LG |
655 | return -ENODEV; |
656 | } | |
657 | ||
658 | /* The DAI name is the last part of the full name of the node. */ | |
659 | p = strrchr(np->full_name, '/') + 1; | |
660 | ssi_private = kzalloc(sizeof(struct fsl_ssi_private) + strlen(p), | |
661 | GFP_KERNEL); | |
17467f23 | 662 | if (!ssi_private) { |
38fec727 | 663 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
f0fba2ad | 664 | return -ENOMEM; |
17467f23 | 665 | } |
17467f23 | 666 | |
f0fba2ad | 667 | strcpy(ssi_private->name, p); |
17467f23 | 668 | |
f0fba2ad LG |
669 | /* Initialize this copy of the CPU DAI driver structure */ |
670 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
671 | sizeof(fsl_ssi_dai_template)); | |
672 | ssi_private->cpu_dai_drv.name = ssi_private->name; | |
673 | ||
674 | /* Get the addresses and IRQ */ | |
675 | ret = of_address_to_resource(np, 0, &res); | |
676 | if (ret) { | |
38fec727 | 677 | dev_err(&pdev->dev, "could not determine device resources\n"); |
f0fba2ad LG |
678 | kfree(ssi_private); |
679 | return ret; | |
680 | } | |
681 | ssi_private->ssi = ioremap(res.start, 1 + res.end - res.start); | |
682 | ssi_private->ssi_phys = res.start; | |
683 | ssi_private->irq = irq_of_parse_and_map(np, 0); | |
17467f23 | 684 | |
f0fba2ad LG |
685 | /* Are the RX and the TX clocks locked? */ |
686 | if (of_find_property(np, "fsl,ssi-asynchronous", NULL)) | |
687 | ssi_private->asynchronous = 1; | |
688 | else | |
689 | ssi_private->cpu_dai_drv.symmetric_rates = 1; | |
17467f23 | 690 | |
8e9d8690 TT |
691 | /* Determine the FIFO depth. */ |
692 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
693 | if (iprop) | |
694 | ssi_private->fifo_depth = *iprop; | |
695 | else | |
696 | /* Older 8610 DTs didn't have the fifo-depth property */ | |
697 | ssi_private->fifo_depth = 8; | |
698 | ||
17467f23 | 699 | /* Initialize the the device_attribute structure */ |
f0fba2ad LG |
700 | dev_attr = &ssi_private->dev_attr; |
701 | dev_attr->attr.name = "statistics"; | |
17467f23 TT |
702 | dev_attr->attr.mode = S_IRUGO; |
703 | dev_attr->show = fsl_sysfs_ssi_show; | |
704 | ||
38fec727 | 705 | ret = device_create_file(&pdev->dev, dev_attr); |
17467f23 | 706 | if (ret) { |
38fec727 | 707 | dev_err(&pdev->dev, "could not create sysfs %s file\n", |
17467f23 | 708 | ssi_private->dev_attr.attr.name); |
87a0632b | 709 | goto error; |
17467f23 TT |
710 | } |
711 | ||
f0fba2ad | 712 | /* Register with ASoC */ |
38fec727 | 713 | dev_set_drvdata(&pdev->dev, ssi_private); |
3f4b783c | 714 | |
38fec727 | 715 | ret = snd_soc_register_dai(&pdev->dev, &ssi_private->cpu_dai_drv); |
87a0632b | 716 | if (ret) { |
38fec727 | 717 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); |
87a0632b | 718 | goto error; |
f0fba2ad LG |
719 | } |
720 | ||
721 | /* Trigger the machine driver's probe function. The platform driver | |
722 | * name of the machine driver is taken from the /model property of the | |
723 | * device tree. We also pass the address of the CPU DAI driver | |
724 | * structure. | |
725 | */ | |
726 | sprop = of_get_property(of_find_node_by_path("/"), "model", NULL); | |
727 | /* Sometimes the model name has a "fsl," prefix, so we strip that. */ | |
728 | p = strrchr(sprop, ','); | |
729 | if (p) | |
730 | sprop = p + 1; | |
731 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
732 | make_lowercase(name); | |
733 | ||
734 | ssi_private->pdev = | |
38fec727 | 735 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
f0fba2ad LG |
736 | if (IS_ERR(ssi_private->pdev)) { |
737 | ret = PTR_ERR(ssi_private->pdev); | |
38fec727 | 738 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
87a0632b | 739 | goto error; |
3f4b783c | 740 | } |
17467f23 | 741 | |
f0fba2ad | 742 | return 0; |
87a0632b TT |
743 | |
744 | error: | |
38fec727 TT |
745 | snd_soc_unregister_dai(&pdev->dev); |
746 | dev_set_drvdata(&pdev->dev, NULL); | |
87a0632b | 747 | if (dev_attr) |
38fec727 | 748 | device_remove_file(&pdev->dev, dev_attr); |
87a0632b TT |
749 | irq_dispose_mapping(ssi_private->irq); |
750 | iounmap(ssi_private->ssi); | |
751 | kfree(ssi_private); | |
752 | ||
753 | return ret; | |
17467f23 | 754 | } |
17467f23 | 755 | |
38fec727 | 756 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 757 | { |
38fec727 | 758 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
17467f23 | 759 | |
f0fba2ad | 760 | platform_device_unregister(ssi_private->pdev); |
38fec727 TT |
761 | snd_soc_unregister_dai(&pdev->dev); |
762 | device_remove_file(&pdev->dev, &ssi_private->dev_attr); | |
3f4b783c | 763 | |
17467f23 | 764 | kfree(ssi_private); |
38fec727 | 765 | dev_set_drvdata(&pdev->dev, NULL); |
f0fba2ad LG |
766 | |
767 | return 0; | |
17467f23 | 768 | } |
f0fba2ad LG |
769 | |
770 | static const struct of_device_id fsl_ssi_ids[] = { | |
771 | { .compatible = "fsl,mpc8610-ssi", }, | |
772 | {} | |
773 | }; | |
774 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
775 | ||
f07eb223 | 776 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
777 | .driver = { |
778 | .name = "fsl-ssi-dai", | |
779 | .owner = THIS_MODULE, | |
780 | .of_match_table = fsl_ssi_ids, | |
781 | }, | |
782 | .probe = fsl_ssi_probe, | |
783 | .remove = fsl_ssi_remove, | |
784 | }; | |
17467f23 | 785 | |
a454dad1 TT |
786 | static int __init fsl_ssi_init(void) |
787 | { | |
788 | printk(KERN_INFO "Freescale Synchronous Serial Interface (SSI) ASoC Driver\n"); | |
789 | ||
f07eb223 | 790 | return platform_driver_register(&fsl_ssi_driver); |
f0fba2ad LG |
791 | } |
792 | ||
793 | static void __exit fsl_ssi_exit(void) | |
794 | { | |
f07eb223 | 795 | platform_driver_unregister(&fsl_ssi_driver); |
a454dad1 | 796 | } |
f0fba2ad | 797 | |
a454dad1 | 798 | module_init(fsl_ssi_init); |
f0fba2ad | 799 | module_exit(fsl_ssi_exit); |
a454dad1 | 800 | |
17467f23 TT |
801 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
802 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 803 | MODULE_LICENSE("GPL v2"); |