Commit | Line | Data |
---|---|---|
17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
17467f23 TT |
11 | */ |
12 | ||
13 | #include <linux/init.h> | |
dfa1a107 | 14 | #include <linux/io.h> |
17467f23 TT |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
95cd98f9 | 17 | #include <linux/clk.h> |
17467f23 TT |
18 | #include <linux/device.h> |
19 | #include <linux/delay.h> | |
5a0e3ad6 | 20 | #include <linux/slab.h> |
dfa1a107 SG |
21 | #include <linux/of_address.h> |
22 | #include <linux/of_irq.h> | |
f0fba2ad | 23 | #include <linux/of_platform.h> |
17467f23 | 24 | |
17467f23 TT |
25 | #include <sound/core.h> |
26 | #include <sound/pcm.h> | |
27 | #include <sound/pcm_params.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/soc.h> | |
30 | ||
17467f23 | 31 | #include "fsl_ssi.h" |
09ce1111 | 32 | #include "imx-pcm.h" |
17467f23 | 33 | |
dfa1a107 SG |
34 | #ifdef PPC |
35 | #define read_ssi(addr) in_be32(addr) | |
36 | #define write_ssi(val, addr) out_be32(addr, val) | |
37 | #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set) | |
38 | #elif defined ARM | |
39 | #define read_ssi(addr) readl(addr) | |
40 | #define write_ssi(val, addr) writel(val, addr) | |
41 | /* | |
42 | * FIXME: Proper locking should be added at write_ssi_mask caller level | |
43 | * to ensure this register read/modify/write sequence is race free. | |
44 | */ | |
45 | static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set) | |
46 | { | |
47 | u32 val = readl(addr); | |
48 | val = (val & ~clear) | set; | |
49 | writel(val, addr); | |
50 | } | |
51 | #endif | |
52 | ||
17467f23 TT |
53 | /** |
54 | * FSLSSI_I2S_RATES: sample rates supported by the I2S | |
55 | * | |
56 | * This driver currently only supports the SSI running in I2S slave mode, | |
57 | * which means the codec determines the sample rate. Therefore, we tell | |
58 | * ALSA that we support all rates and let the codec driver decide what rates | |
59 | * are really supported. | |
60 | */ | |
61 | #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ | |
62 | SNDRV_PCM_RATE_CONTINUOUS) | |
63 | ||
64 | /** | |
65 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
66 | * | |
67 | * This driver currently only supports the SSI running in I2S slave mode. | |
68 | * | |
69 | * The SSI has a limitation in that the samples must be in the same byte | |
70 | * order as the host CPU. This is because when multiple bytes are written | |
71 | * to the STX register, the bytes and bits must be written in the same | |
72 | * order. The STX is a shift register, so all the bits need to be aligned | |
73 | * (bit-endianness must match byte-endianness). Processors typically write | |
74 | * the bits within a byte in the same order that the bytes of a word are | |
75 | * written in. So if the host CPU is big-endian, then only big-endian | |
76 | * samples will be written to STX properly. | |
77 | */ | |
78 | #ifdef __BIG_ENDIAN | |
79 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
80 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
81 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
82 | #else | |
83 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
84 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
85 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
86 | #endif | |
87 | ||
d5a908b2 TT |
88 | /* SIER bitflag of interrupts to enable */ |
89 | #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \ | |
90 | CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \ | |
91 | CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \ | |
92 | CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \ | |
93 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN) | |
94 | ||
17467f23 TT |
95 | /** |
96 | * fsl_ssi_private: per-SSI private data | |
97 | * | |
17467f23 TT |
98 | * @ssi: pointer to the SSI's registers |
99 | * @ssi_phys: physical address of the SSI registers | |
100 | * @irq: IRQ of this SSI | |
be41e941 TT |
101 | * @first_stream: pointer to the stream that was opened first |
102 | * @second_stream: pointer to second stream | |
17467f23 TT |
103 | * @playback: the number of playback streams opened |
104 | * @capture: the number of capture streams opened | |
105 | * @cpu_dai: the CPU DAI for this device | |
106 | * @dev_attr: the sysfs device attribute structure | |
107 | * @stats: SSI statistics | |
f0fba2ad | 108 | * @name: name for this device |
17467f23 TT |
109 | */ |
110 | struct fsl_ssi_private { | |
17467f23 TT |
111 | struct ccsr_ssi __iomem *ssi; |
112 | dma_addr_t ssi_phys; | |
113 | unsigned int irq; | |
be41e941 TT |
114 | struct snd_pcm_substream *first_stream; |
115 | struct snd_pcm_substream *second_stream; | |
8e9d8690 | 116 | unsigned int fifo_depth; |
f0fba2ad | 117 | struct snd_soc_dai_driver cpu_dai_drv; |
17467f23 | 118 | struct device_attribute dev_attr; |
f0fba2ad | 119 | struct platform_device *pdev; |
17467f23 | 120 | |
09ce1111 SG |
121 | bool new_binding; |
122 | bool ssi_on_imx; | |
95cd98f9 | 123 | struct clk *clk; |
09ce1111 SG |
124 | struct platform_device *imx_pcm_pdev; |
125 | struct imx_pcm_dma_params dma_params_tx; | |
126 | struct imx_pcm_dma_params dma_params_rx; | |
127 | ||
17467f23 TT |
128 | struct { |
129 | unsigned int rfrc; | |
130 | unsigned int tfrc; | |
131 | unsigned int cmdau; | |
132 | unsigned int cmddu; | |
133 | unsigned int rxt; | |
134 | unsigned int rdr1; | |
135 | unsigned int rdr0; | |
136 | unsigned int tde1; | |
137 | unsigned int tde0; | |
138 | unsigned int roe1; | |
139 | unsigned int roe0; | |
140 | unsigned int tue1; | |
141 | unsigned int tue0; | |
142 | unsigned int tfs; | |
143 | unsigned int rfs; | |
144 | unsigned int tls; | |
145 | unsigned int rls; | |
146 | unsigned int rff1; | |
147 | unsigned int rff0; | |
148 | unsigned int tfe1; | |
149 | unsigned int tfe0; | |
150 | } stats; | |
f0fba2ad LG |
151 | |
152 | char name[1]; | |
17467f23 TT |
153 | }; |
154 | ||
155 | /** | |
156 | * fsl_ssi_isr: SSI interrupt handler | |
157 | * | |
158 | * Although it's possible to use the interrupt handler to send and receive | |
159 | * data to/from the SSI, we use the DMA instead. Programming is more | |
160 | * complicated, but the performance is much better. | |
161 | * | |
162 | * This interrupt handler is used only to gather statistics. | |
163 | * | |
164 | * @irq: IRQ of the SSI device | |
165 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
166 | */ | |
167 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
168 | { | |
169 | struct fsl_ssi_private *ssi_private = dev_id; | |
170 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
171 | irqreturn_t ret = IRQ_NONE; | |
172 | __be32 sisr; | |
173 | __be32 sisr2 = 0; | |
174 | ||
175 | /* We got an interrupt, so read the status register to see what we | |
176 | were interrupted for. We mask it with the Interrupt Enable register | |
177 | so that we only check for events that we're interested in. | |
178 | */ | |
dfa1a107 | 179 | sisr = read_ssi(&ssi->sisr) & SIER_FLAGS; |
17467f23 TT |
180 | |
181 | if (sisr & CCSR_SSI_SISR_RFRC) { | |
182 | ssi_private->stats.rfrc++; | |
183 | sisr2 |= CCSR_SSI_SISR_RFRC; | |
184 | ret = IRQ_HANDLED; | |
185 | } | |
186 | ||
187 | if (sisr & CCSR_SSI_SISR_TFRC) { | |
188 | ssi_private->stats.tfrc++; | |
189 | sisr2 |= CCSR_SSI_SISR_TFRC; | |
190 | ret = IRQ_HANDLED; | |
191 | } | |
192 | ||
193 | if (sisr & CCSR_SSI_SISR_CMDAU) { | |
194 | ssi_private->stats.cmdau++; | |
195 | ret = IRQ_HANDLED; | |
196 | } | |
197 | ||
198 | if (sisr & CCSR_SSI_SISR_CMDDU) { | |
199 | ssi_private->stats.cmddu++; | |
200 | ret = IRQ_HANDLED; | |
201 | } | |
202 | ||
203 | if (sisr & CCSR_SSI_SISR_RXT) { | |
204 | ssi_private->stats.rxt++; | |
205 | ret = IRQ_HANDLED; | |
206 | } | |
207 | ||
208 | if (sisr & CCSR_SSI_SISR_RDR1) { | |
209 | ssi_private->stats.rdr1++; | |
210 | ret = IRQ_HANDLED; | |
211 | } | |
212 | ||
213 | if (sisr & CCSR_SSI_SISR_RDR0) { | |
214 | ssi_private->stats.rdr0++; | |
215 | ret = IRQ_HANDLED; | |
216 | } | |
217 | ||
218 | if (sisr & CCSR_SSI_SISR_TDE1) { | |
219 | ssi_private->stats.tde1++; | |
220 | ret = IRQ_HANDLED; | |
221 | } | |
222 | ||
223 | if (sisr & CCSR_SSI_SISR_TDE0) { | |
224 | ssi_private->stats.tde0++; | |
225 | ret = IRQ_HANDLED; | |
226 | } | |
227 | ||
228 | if (sisr & CCSR_SSI_SISR_ROE1) { | |
229 | ssi_private->stats.roe1++; | |
230 | sisr2 |= CCSR_SSI_SISR_ROE1; | |
231 | ret = IRQ_HANDLED; | |
232 | } | |
233 | ||
234 | if (sisr & CCSR_SSI_SISR_ROE0) { | |
235 | ssi_private->stats.roe0++; | |
236 | sisr2 |= CCSR_SSI_SISR_ROE0; | |
237 | ret = IRQ_HANDLED; | |
238 | } | |
239 | ||
240 | if (sisr & CCSR_SSI_SISR_TUE1) { | |
241 | ssi_private->stats.tue1++; | |
242 | sisr2 |= CCSR_SSI_SISR_TUE1; | |
243 | ret = IRQ_HANDLED; | |
244 | } | |
245 | ||
246 | if (sisr & CCSR_SSI_SISR_TUE0) { | |
247 | ssi_private->stats.tue0++; | |
248 | sisr2 |= CCSR_SSI_SISR_TUE0; | |
249 | ret = IRQ_HANDLED; | |
250 | } | |
251 | ||
252 | if (sisr & CCSR_SSI_SISR_TFS) { | |
253 | ssi_private->stats.tfs++; | |
254 | ret = IRQ_HANDLED; | |
255 | } | |
256 | ||
257 | if (sisr & CCSR_SSI_SISR_RFS) { | |
258 | ssi_private->stats.rfs++; | |
259 | ret = IRQ_HANDLED; | |
260 | } | |
261 | ||
262 | if (sisr & CCSR_SSI_SISR_TLS) { | |
263 | ssi_private->stats.tls++; | |
264 | ret = IRQ_HANDLED; | |
265 | } | |
266 | ||
267 | if (sisr & CCSR_SSI_SISR_RLS) { | |
268 | ssi_private->stats.rls++; | |
269 | ret = IRQ_HANDLED; | |
270 | } | |
271 | ||
272 | if (sisr & CCSR_SSI_SISR_RFF1) { | |
273 | ssi_private->stats.rff1++; | |
274 | ret = IRQ_HANDLED; | |
275 | } | |
276 | ||
277 | if (sisr & CCSR_SSI_SISR_RFF0) { | |
278 | ssi_private->stats.rff0++; | |
279 | ret = IRQ_HANDLED; | |
280 | } | |
281 | ||
282 | if (sisr & CCSR_SSI_SISR_TFE1) { | |
283 | ssi_private->stats.tfe1++; | |
284 | ret = IRQ_HANDLED; | |
285 | } | |
286 | ||
287 | if (sisr & CCSR_SSI_SISR_TFE0) { | |
288 | ssi_private->stats.tfe0++; | |
289 | ret = IRQ_HANDLED; | |
290 | } | |
291 | ||
292 | /* Clear the bits that we set */ | |
293 | if (sisr2) | |
dfa1a107 | 294 | write_ssi(sisr2, &ssi->sisr); |
17467f23 TT |
295 | |
296 | return ret; | |
297 | } | |
298 | ||
299 | /** | |
300 | * fsl_ssi_startup: create a new substream | |
301 | * | |
302 | * This is the first function called when a stream is opened. | |
303 | * | |
304 | * If this is the first stream open, then grab the IRQ and program most of | |
305 | * the SSI registers. | |
306 | */ | |
dee89c4d MB |
307 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
308 | struct snd_soc_dai *dai) | |
17467f23 TT |
309 | { |
310 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5e538eca TT |
311 | struct fsl_ssi_private *ssi_private = |
312 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
313 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates; | |
17467f23 TT |
314 | |
315 | /* | |
316 | * If this is the first stream opened, then request the IRQ | |
317 | * and initialize the SSI registers. | |
318 | */ | |
5e538eca | 319 | if (!ssi_private->first_stream) { |
17467f23 | 320 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
17467f23 | 321 | |
5e538eca TT |
322 | ssi_private->first_stream = substream; |
323 | ||
17467f23 TT |
324 | /* |
325 | * Section 16.5 of the MPC8610 reference manual says that the | |
326 | * SSI needs to be disabled before updating the registers we set | |
327 | * here. | |
328 | */ | |
dfa1a107 | 329 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); |
17467f23 TT |
330 | |
331 | /* | |
332 | * Program the SSI into I2S Slave Non-Network Synchronous mode. | |
333 | * Also enable the transmit and receive FIFO. | |
334 | * | |
335 | * FIXME: Little-endian samples require a different shift dir | |
336 | */ | |
dfa1a107 | 337 | write_ssi_mask(&ssi->scr, |
a454dad1 TT |
338 | CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN, |
339 | CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE | |
5e538eca | 340 | | (synchronous ? CCSR_SSI_SCR_SYN : 0)); |
17467f23 | 341 | |
dfa1a107 | 342 | write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 | |
17467f23 | 343 | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS | |
dfa1a107 | 344 | CCSR_SSI_STCR_TSCKP, &ssi->stcr); |
17467f23 | 345 | |
dfa1a107 | 346 | write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 | |
17467f23 | 347 | CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS | |
dfa1a107 | 348 | CCSR_SSI_SRCR_RSCKP, &ssi->srcr); |
17467f23 TT |
349 | |
350 | /* | |
351 | * The DC and PM bits are only used if the SSI is the clock | |
352 | * master. | |
353 | */ | |
354 | ||
5e538eca | 355 | /* Enable the interrupts and DMA requests */ |
dfa1a107 | 356 | write_ssi(SIER_FLAGS, &ssi->sier); |
17467f23 TT |
357 | |
358 | /* | |
359 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We | |
8e9d8690 TT |
360 | * don't use FIFO 1. We program the transmit water to signal a |
361 | * DMA transfer if there are only two (or fewer) elements left | |
362 | * in the FIFO. Two elements equals one frame (left channel, | |
363 | * right channel). This value, however, depends on the depth of | |
364 | * the transmit buffer. | |
365 | * | |
366 | * We program the receive FIFO to notify us if at least two | |
367 | * elements (one frame) have been written to the FIFO. We could | |
368 | * make this value larger (and maybe we should), but this way | |
369 | * data will be written to memory as soon as it's available. | |
17467f23 | 370 | */ |
dfa1a107 SG |
371 | write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) | |
372 | CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2), | |
373 | &ssi->sfcsr); | |
17467f23 TT |
374 | |
375 | /* | |
376 | * We keep the SSI disabled because if we enable it, then the | |
377 | * DMA controller will start. It's not supposed to start until | |
378 | * the SCR.TE (or SCR.RE) bit is set, but it does anyway. The | |
379 | * DMA controller will transfer one "BWC" of data (i.e. the | |
380 | * amount of data that the MR.BWC bits are set to). The reason | |
381 | * this is bad is because at this point, the PCM driver has not | |
382 | * finished initializing the DMA controller. | |
383 | */ | |
5e538eca TT |
384 | } else { |
385 | if (synchronous) { | |
386 | struct snd_pcm_runtime *first_runtime = | |
387 | ssi_private->first_stream->runtime; | |
388 | /* | |
389 | * This is the second stream open, and we're in | |
390 | * synchronous mode, so we need to impose sample | |
391 | * sample size constraints. This is because STCCR is | |
392 | * used for playback and capture in synchronous mode, | |
393 | * so there's no way to specify different word | |
394 | * lengths. | |
395 | * | |
396 | * Note that this can cause a race condition if the | |
397 | * second stream is opened before the first stream is | |
398 | * fully initialized. We provide some protection by | |
399 | * checking to make sure the first stream is | |
400 | * initialized, but it's not perfect. ALSA sometimes | |
401 | * re-initializes the driver with a different sample | |
402 | * rate or size. If the second stream is opened | |
403 | * before the first stream has received its final | |
404 | * parameters, then the second stream may be | |
405 | * constrained to the wrong sample rate or size. | |
406 | */ | |
407 | if (!first_runtime->sample_bits) { | |
408 | dev_err(substream->pcm->card->dev, | |
409 | "set sample size in %s stream first\n", | |
410 | substream->stream == | |
411 | SNDRV_PCM_STREAM_PLAYBACK | |
412 | ? "capture" : "playback"); | |
413 | return -EAGAIN; | |
414 | } | |
be41e941 | 415 | |
a454dad1 TT |
416 | snd_pcm_hw_constraint_minmax(substream->runtime, |
417 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
418 | first_runtime->sample_bits, | |
419 | first_runtime->sample_bits); | |
5e538eca | 420 | } |
be41e941 TT |
421 | |
422 | ssi_private->second_stream = substream; | |
423 | } | |
424 | ||
09ce1111 SG |
425 | if (ssi_private->ssi_on_imx) |
426 | snd_soc_dai_set_dma_data(dai, substream, | |
427 | (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? | |
428 | &ssi_private->dma_params_tx : | |
429 | &ssi_private->dma_params_rx); | |
430 | ||
17467f23 TT |
431 | return 0; |
432 | } | |
433 | ||
434 | /** | |
85ef2375 | 435 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
436 | * |
437 | * Most of the SSI registers have been programmed in the startup function, | |
438 | * but the word length must be programmed here. Unfortunately, programming | |
439 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
440 | * cause a problem with supporting simultaneous playback and capture. If | |
441 | * the SSI is already playing a stream, then that stream may be temporarily | |
442 | * stopped when you start capture. | |
443 | * | |
444 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
445 | * clock master. | |
446 | */ | |
85ef2375 TT |
447 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
448 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 449 | { |
f0fba2ad | 450 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
5e538eca TT |
451 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
452 | unsigned int sample_size = | |
453 | snd_pcm_format_width(params_format(hw_params)); | |
454 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); | |
dfa1a107 | 455 | int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; |
17467f23 | 456 | |
5e538eca TT |
457 | /* |
458 | * If we're in synchronous mode, and the SSI is already enabled, | |
459 | * then STCCR is already set properly. | |
460 | */ | |
461 | if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) | |
462 | return 0; | |
17467f23 | 463 | |
5e538eca TT |
464 | /* |
465 | * FIXME: The documentation says that SxCCR[WL] should not be | |
466 | * modified while the SSI is enabled. The only time this can | |
467 | * happen is if we're trying to do simultaneous playback and | |
468 | * capture in asynchronous mode. Unfortunately, I have been enable | |
469 | * to get that to work at all on the P1022DS. Therefore, we don't | |
470 | * bother to disable/enable the SSI when setting SxCCR[WL], because | |
471 | * the SSI will stop anyway. Maybe one day, this will get fixed. | |
472 | */ | |
17467f23 | 473 | |
5e538eca TT |
474 | /* In synchronous mode, the SSI uses STCCR for capture */ |
475 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || | |
476 | ssi_private->cpu_dai_drv.symmetric_rates) | |
dfa1a107 | 477 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
5e538eca | 478 | else |
dfa1a107 | 479 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
17467f23 TT |
480 | |
481 | return 0; | |
482 | } | |
483 | ||
484 | /** | |
485 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
486 | * | |
487 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
488 | * transfer of data. | |
489 | * | |
490 | * The DMA channel is in external master start and pause mode, which | |
491 | * means the SSI completely controls the flow of data. | |
492 | */ | |
dee89c4d MB |
493 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
494 | struct snd_soc_dai *dai) | |
17467f23 TT |
495 | { |
496 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 497 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 TT |
498 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
499 | ||
500 | switch (cmd) { | |
501 | case SNDRV_PCM_TRIGGER_START: | |
17467f23 | 502 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 503 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
dfa1a107 | 504 | write_ssi_mask(&ssi->scr, 0, |
be41e941 | 505 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE); |
a4d11fe5 | 506 | else |
dfa1a107 | 507 | write_ssi_mask(&ssi->scr, 0, |
be41e941 | 508 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE); |
17467f23 TT |
509 | break; |
510 | ||
511 | case SNDRV_PCM_TRIGGER_STOP: | |
17467f23 TT |
512 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
513 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
dfa1a107 | 514 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0); |
17467f23 | 515 | else |
dfa1a107 | 516 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0); |
17467f23 TT |
517 | break; |
518 | ||
519 | default: | |
520 | return -EINVAL; | |
521 | } | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
526 | /** | |
527 | * fsl_ssi_shutdown: shutdown the SSI | |
528 | * | |
529 | * Shutdown the SSI if there are no other substreams open. | |
530 | */ | |
dee89c4d MB |
531 | static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, |
532 | struct snd_soc_dai *dai) | |
17467f23 TT |
533 | { |
534 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 535 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 | 536 | |
be41e941 TT |
537 | if (ssi_private->first_stream == substream) |
538 | ssi_private->first_stream = ssi_private->second_stream; | |
539 | ||
540 | ssi_private->second_stream = NULL; | |
541 | ||
17467f23 | 542 | /* |
1fab6caf | 543 | * If this is the last active substream, disable the SSI. |
17467f23 | 544 | */ |
5e538eca | 545 | if (!ssi_private->first_stream) { |
17467f23 TT |
546 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
547 | ||
dfa1a107 | 548 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); |
17467f23 TT |
549 | } |
550 | } | |
551 | ||
85e7652d | 552 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
6335d055 EM |
553 | .startup = fsl_ssi_startup, |
554 | .hw_params = fsl_ssi_hw_params, | |
555 | .shutdown = fsl_ssi_shutdown, | |
556 | .trigger = fsl_ssi_trigger, | |
6335d055 EM |
557 | }; |
558 | ||
f0fba2ad LG |
559 | /* Template for the CPU dai driver structure */ |
560 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
17467f23 TT |
561 | .playback = { |
562 | /* The SSI does not support monaural audio. */ | |
563 | .channels_min = 2, | |
564 | .channels_max = 2, | |
565 | .rates = FSLSSI_I2S_RATES, | |
566 | .formats = FSLSSI_I2S_FORMATS, | |
567 | }, | |
568 | .capture = { | |
569 | .channels_min = 2, | |
570 | .channels_max = 2, | |
571 | .rates = FSLSSI_I2S_RATES, | |
572 | .formats = FSLSSI_I2S_FORMATS, | |
573 | }, | |
6335d055 | 574 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
575 | }; |
576 | ||
d5a908b2 TT |
577 | /* Show the statistics of a flag only if its interrupt is enabled. The |
578 | * compiler will optimze this code to a no-op if the interrupt is not | |
579 | * enabled. | |
580 | */ | |
581 | #define SIER_SHOW(flag, name) \ | |
582 | do { \ | |
583 | if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \ | |
584 | length += sprintf(buf + length, #name "=%u\n", \ | |
585 | ssi_private->stats.name); \ | |
586 | } while (0) | |
587 | ||
588 | ||
17467f23 TT |
589 | /** |
590 | * fsl_sysfs_ssi_show: display SSI statistics | |
591 | * | |
d5a908b2 TT |
592 | * Display the statistics for the current SSI device. To avoid confusion, |
593 | * we only show those counts that are enabled. | |
17467f23 TT |
594 | */ |
595 | static ssize_t fsl_sysfs_ssi_show(struct device *dev, | |
596 | struct device_attribute *attr, char *buf) | |
597 | { | |
598 | struct fsl_ssi_private *ssi_private = | |
d5a908b2 TT |
599 | container_of(attr, struct fsl_ssi_private, dev_attr); |
600 | ssize_t length = 0; | |
601 | ||
602 | SIER_SHOW(RFRC_EN, rfrc); | |
603 | SIER_SHOW(TFRC_EN, tfrc); | |
604 | SIER_SHOW(CMDAU_EN, cmdau); | |
605 | SIER_SHOW(CMDDU_EN, cmddu); | |
606 | SIER_SHOW(RXT_EN, rxt); | |
607 | SIER_SHOW(RDR1_EN, rdr1); | |
608 | SIER_SHOW(RDR0_EN, rdr0); | |
609 | SIER_SHOW(TDE1_EN, tde1); | |
610 | SIER_SHOW(TDE0_EN, tde0); | |
611 | SIER_SHOW(ROE1_EN, roe1); | |
612 | SIER_SHOW(ROE0_EN, roe0); | |
613 | SIER_SHOW(TUE1_EN, tue1); | |
614 | SIER_SHOW(TUE0_EN, tue0); | |
615 | SIER_SHOW(TFS_EN, tfs); | |
616 | SIER_SHOW(RFS_EN, rfs); | |
617 | SIER_SHOW(TLS_EN, tls); | |
618 | SIER_SHOW(RLS_EN, rls); | |
619 | SIER_SHOW(RFF1_EN, rff1); | |
620 | SIER_SHOW(RFF0_EN, rff0); | |
621 | SIER_SHOW(TFE1_EN, tfe1); | |
622 | SIER_SHOW(TFE0_EN, tfe0); | |
17467f23 TT |
623 | |
624 | return length; | |
625 | } | |
626 | ||
627 | /** | |
f0fba2ad | 628 | * Make every character in a string lower-case |
17467f23 | 629 | */ |
f0fba2ad LG |
630 | static void make_lowercase(char *s) |
631 | { | |
632 | char *p = s; | |
633 | char c; | |
634 | ||
635 | while ((c = *p)) { | |
636 | if ((c >= 'A') && (c <= 'Z')) | |
637 | *p = c + ('a' - 'A'); | |
638 | p++; | |
639 | } | |
640 | } | |
641 | ||
a0a3d518 | 642 | static int fsl_ssi_probe(struct platform_device *pdev) |
17467f23 | 643 | { |
17467f23 TT |
644 | struct fsl_ssi_private *ssi_private; |
645 | int ret = 0; | |
87a0632b | 646 | struct device_attribute *dev_attr = NULL; |
38fec727 | 647 | struct device_node *np = pdev->dev.of_node; |
f0fba2ad | 648 | const char *p, *sprop; |
8e9d8690 | 649 | const uint32_t *iprop; |
f0fba2ad LG |
650 | struct resource res; |
651 | char name[64]; | |
312bb4f6 | 652 | bool shared; |
17467f23 | 653 | |
ff71334a TT |
654 | /* SSIs that are not connected on the board should have a |
655 | * status = "disabled" | |
656 | * property in their device tree nodes. | |
f0fba2ad | 657 | */ |
ff71334a | 658 | if (!of_device_is_available(np)) |
f0fba2ad LG |
659 | return -ENODEV; |
660 | ||
661 | /* We only support the SSI in "I2S Slave" mode */ | |
662 | sprop = of_get_property(np, "fsl,mode", NULL); | |
663 | if (!sprop || strcmp(sprop, "i2s-slave")) { | |
38fec727 | 664 | dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop); |
f0fba2ad LG |
665 | return -ENODEV; |
666 | } | |
667 | ||
668 | /* The DAI name is the last part of the full name of the node. */ | |
669 | p = strrchr(np->full_name, '/') + 1; | |
670 | ssi_private = kzalloc(sizeof(struct fsl_ssi_private) + strlen(p), | |
671 | GFP_KERNEL); | |
17467f23 | 672 | if (!ssi_private) { |
38fec727 | 673 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
f0fba2ad | 674 | return -ENOMEM; |
17467f23 | 675 | } |
17467f23 | 676 | |
f0fba2ad | 677 | strcpy(ssi_private->name, p); |
17467f23 | 678 | |
f0fba2ad LG |
679 | /* Initialize this copy of the CPU DAI driver structure */ |
680 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
681 | sizeof(fsl_ssi_dai_template)); | |
682 | ssi_private->cpu_dai_drv.name = ssi_private->name; | |
683 | ||
684 | /* Get the addresses and IRQ */ | |
685 | ret = of_address_to_resource(np, 0, &res); | |
686 | if (ret) { | |
38fec727 | 687 | dev_err(&pdev->dev, "could not determine device resources\n"); |
1fab6caf | 688 | goto error_kmalloc; |
f0fba2ad | 689 | } |
147dfe90 TT |
690 | ssi_private->ssi = of_iomap(np, 0); |
691 | if (!ssi_private->ssi) { | |
692 | dev_err(&pdev->dev, "could not map device resources\n"); | |
1fab6caf TT |
693 | ret = -ENOMEM; |
694 | goto error_kmalloc; | |
147dfe90 | 695 | } |
f0fba2ad | 696 | ssi_private->ssi_phys = res.start; |
1fab6caf | 697 | |
f0fba2ad | 698 | ssi_private->irq = irq_of_parse_and_map(np, 0); |
1fab6caf TT |
699 | if (ssi_private->irq == NO_IRQ) { |
700 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); | |
701 | ret = -ENXIO; | |
702 | goto error_iomap; | |
703 | } | |
704 | ||
705 | /* The 'name' should not have any slashes in it. */ | |
706 | ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, ssi_private->name, | |
707 | ssi_private); | |
708 | if (ret < 0) { | |
709 | dev_err(&pdev->dev, "could not claim irq %u\n", ssi_private->irq); | |
710 | goto error_irqmap; | |
711 | } | |
17467f23 | 712 | |
f0fba2ad | 713 | /* Are the RX and the TX clocks locked? */ |
5e538eca | 714 | if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) |
f0fba2ad | 715 | ssi_private->cpu_dai_drv.symmetric_rates = 1; |
17467f23 | 716 | |
8e9d8690 TT |
717 | /* Determine the FIFO depth. */ |
718 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
719 | if (iprop) | |
147dfe90 | 720 | ssi_private->fifo_depth = be32_to_cpup(iprop); |
8e9d8690 TT |
721 | else |
722 | /* Older 8610 DTs didn't have the fifo-depth property */ | |
723 | ssi_private->fifo_depth = 8; | |
724 | ||
09ce1111 SG |
725 | if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) { |
726 | u32 dma_events[2]; | |
727 | ssi_private->ssi_on_imx = true; | |
95cd98f9 SG |
728 | |
729 | ssi_private->clk = clk_get(&pdev->dev, NULL); | |
730 | if (IS_ERR(ssi_private->clk)) { | |
731 | ret = PTR_ERR(ssi_private->clk); | |
732 | dev_err(&pdev->dev, "could not get clock: %d\n", ret); | |
733 | goto error_irq; | |
734 | } | |
735 | clk_prepare_enable(ssi_private->clk); | |
736 | ||
09ce1111 SG |
737 | /* |
738 | * We have burstsize be "fifo_depth - 2" to match the SSI | |
739 | * watermark setting in fsl_ssi_startup(). | |
740 | */ | |
741 | ssi_private->dma_params_tx.burstsize = | |
742 | ssi_private->fifo_depth - 2; | |
743 | ssi_private->dma_params_rx.burstsize = | |
744 | ssi_private->fifo_depth - 2; | |
745 | ssi_private->dma_params_tx.dma_addr = | |
746 | ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0); | |
747 | ssi_private->dma_params_rx.dma_addr = | |
748 | ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0); | |
749 | /* | |
750 | * TODO: This is a temporary solution and should be changed | |
751 | * to use generic DMA binding later when the helplers get in. | |
752 | */ | |
753 | ret = of_property_read_u32_array(pdev->dev.of_node, | |
754 | "fsl,ssi-dma-events", dma_events, 2); | |
755 | if (ret) { | |
756 | dev_err(&pdev->dev, "could not get dma events\n"); | |
95cd98f9 | 757 | goto error_clk; |
09ce1111 | 758 | } |
312bb4f6 LPC |
759 | |
760 | shared = of_device_is_compatible(of_get_parent(np), | |
761 | "fsl,spba-bus"); | |
762 | ||
763 | imx_pcm_dma_params_init_data(&ssi_private->dma_params_tx, | |
764 | dma_events[0], shared); | |
765 | imx_pcm_dma_params_init_data(&ssi_private->dma_params_rx, | |
766 | dma_events[1], shared); | |
09ce1111 SG |
767 | } |
768 | ||
17467f23 | 769 | /* Initialize the the device_attribute structure */ |
f0fba2ad | 770 | dev_attr = &ssi_private->dev_attr; |
0f768a72 | 771 | sysfs_attr_init(&dev_attr->attr); |
f0fba2ad | 772 | dev_attr->attr.name = "statistics"; |
17467f23 TT |
773 | dev_attr->attr.mode = S_IRUGO; |
774 | dev_attr->show = fsl_sysfs_ssi_show; | |
775 | ||
38fec727 | 776 | ret = device_create_file(&pdev->dev, dev_attr); |
17467f23 | 777 | if (ret) { |
38fec727 | 778 | dev_err(&pdev->dev, "could not create sysfs %s file\n", |
17467f23 | 779 | ssi_private->dev_attr.attr.name); |
1fab6caf | 780 | goto error_irq; |
17467f23 TT |
781 | } |
782 | ||
f0fba2ad | 783 | /* Register with ASoC */ |
38fec727 | 784 | dev_set_drvdata(&pdev->dev, ssi_private); |
3f4b783c | 785 | |
38fec727 | 786 | ret = snd_soc_register_dai(&pdev->dev, &ssi_private->cpu_dai_drv); |
87a0632b | 787 | if (ret) { |
38fec727 | 788 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); |
1fab6caf | 789 | goto error_dev; |
f0fba2ad LG |
790 | } |
791 | ||
09ce1111 SG |
792 | if (ssi_private->ssi_on_imx) { |
793 | ssi_private->imx_pcm_pdev = | |
794 | platform_device_register_simple("imx-pcm-audio", | |
795 | -1, NULL, 0); | |
796 | if (IS_ERR(ssi_private->imx_pcm_pdev)) { | |
797 | ret = PTR_ERR(ssi_private->imx_pcm_pdev); | |
798 | goto error_dev; | |
799 | } | |
800 | } | |
801 | ||
802 | /* | |
803 | * If codec-handle property is missing from SSI node, we assume | |
804 | * that the machine driver uses new binding which does not require | |
805 | * SSI driver to trigger machine driver's probe. | |
806 | */ | |
807 | if (!of_get_property(np, "codec-handle", NULL)) { | |
808 | ssi_private->new_binding = true; | |
809 | goto done; | |
810 | } | |
811 | ||
f0fba2ad | 812 | /* Trigger the machine driver's probe function. The platform driver |
2b81ec69 | 813 | * name of the machine driver is taken from /compatible property of the |
f0fba2ad LG |
814 | * device tree. We also pass the address of the CPU DAI driver |
815 | * structure. | |
816 | */ | |
2b81ec69 SG |
817 | sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); |
818 | /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ | |
f0fba2ad LG |
819 | p = strrchr(sprop, ','); |
820 | if (p) | |
821 | sprop = p + 1; | |
822 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
823 | make_lowercase(name); | |
824 | ||
825 | ssi_private->pdev = | |
38fec727 | 826 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
f0fba2ad LG |
827 | if (IS_ERR(ssi_private->pdev)) { |
828 | ret = PTR_ERR(ssi_private->pdev); | |
38fec727 | 829 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
1fab6caf | 830 | goto error_dai; |
3f4b783c | 831 | } |
17467f23 | 832 | |
09ce1111 | 833 | done: |
f0fba2ad | 834 | return 0; |
87a0632b | 835 | |
1fab6caf | 836 | error_dai: |
09ce1111 SG |
837 | if (ssi_private->ssi_on_imx) |
838 | platform_device_unregister(ssi_private->imx_pcm_pdev); | |
38fec727 | 839 | snd_soc_unregister_dai(&pdev->dev); |
1fab6caf TT |
840 | |
841 | error_dev: | |
38fec727 | 842 | dev_set_drvdata(&pdev->dev, NULL); |
1fab6caf TT |
843 | device_remove_file(&pdev->dev, dev_attr); |
844 | ||
95cd98f9 SG |
845 | error_clk: |
846 | if (ssi_private->ssi_on_imx) { | |
847 | clk_disable_unprepare(ssi_private->clk); | |
848 | clk_put(ssi_private->clk); | |
849 | } | |
850 | ||
1fab6caf TT |
851 | error_irq: |
852 | free_irq(ssi_private->irq, ssi_private); | |
853 | ||
854 | error_irqmap: | |
87a0632b | 855 | irq_dispose_mapping(ssi_private->irq); |
1fab6caf TT |
856 | |
857 | error_iomap: | |
87a0632b | 858 | iounmap(ssi_private->ssi); |
1fab6caf TT |
859 | |
860 | error_kmalloc: | |
87a0632b TT |
861 | kfree(ssi_private); |
862 | ||
863 | return ret; | |
17467f23 | 864 | } |
17467f23 | 865 | |
38fec727 | 866 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 867 | { |
38fec727 | 868 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
17467f23 | 869 | |
09ce1111 SG |
870 | if (!ssi_private->new_binding) |
871 | platform_device_unregister(ssi_private->pdev); | |
95cd98f9 | 872 | if (ssi_private->ssi_on_imx) { |
09ce1111 | 873 | platform_device_unregister(ssi_private->imx_pcm_pdev); |
95cd98f9 SG |
874 | clk_disable_unprepare(ssi_private->clk); |
875 | clk_put(ssi_private->clk); | |
876 | } | |
38fec727 TT |
877 | snd_soc_unregister_dai(&pdev->dev); |
878 | device_remove_file(&pdev->dev, &ssi_private->dev_attr); | |
3f4b783c | 879 | |
1fab6caf TT |
880 | free_irq(ssi_private->irq, ssi_private); |
881 | irq_dispose_mapping(ssi_private->irq); | |
882 | ||
17467f23 | 883 | kfree(ssi_private); |
38fec727 | 884 | dev_set_drvdata(&pdev->dev, NULL); |
f0fba2ad LG |
885 | |
886 | return 0; | |
17467f23 | 887 | } |
f0fba2ad LG |
888 | |
889 | static const struct of_device_id fsl_ssi_ids[] = { | |
890 | { .compatible = "fsl,mpc8610-ssi", }, | |
09ce1111 | 891 | { .compatible = "fsl,imx21-ssi", }, |
f0fba2ad LG |
892 | {} |
893 | }; | |
894 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
895 | ||
f07eb223 | 896 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
897 | .driver = { |
898 | .name = "fsl-ssi-dai", | |
899 | .owner = THIS_MODULE, | |
900 | .of_match_table = fsl_ssi_ids, | |
901 | }, | |
902 | .probe = fsl_ssi_probe, | |
903 | .remove = fsl_ssi_remove, | |
904 | }; | |
17467f23 | 905 | |
ba0a7e02 | 906 | module_platform_driver(fsl_ssi_driver); |
a454dad1 | 907 | |
17467f23 TT |
908 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
909 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 910 | MODULE_LICENSE("GPL v2"); |