Commit | Line | Data |
---|---|---|
17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
17467f23 TT |
11 | */ |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/delay.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
f0fba2ad | 19 | #include <linux/of_platform.h> |
17467f23 | 20 | |
17467f23 TT |
21 | #include <sound/core.h> |
22 | #include <sound/pcm.h> | |
23 | #include <sound/pcm_params.h> | |
24 | #include <sound/initval.h> | |
25 | #include <sound/soc.h> | |
26 | ||
17467f23 TT |
27 | #include "fsl_ssi.h" |
28 | ||
29 | /** | |
30 | * FSLSSI_I2S_RATES: sample rates supported by the I2S | |
31 | * | |
32 | * This driver currently only supports the SSI running in I2S slave mode, | |
33 | * which means the codec determines the sample rate. Therefore, we tell | |
34 | * ALSA that we support all rates and let the codec driver decide what rates | |
35 | * are really supported. | |
36 | */ | |
37 | #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ | |
38 | SNDRV_PCM_RATE_CONTINUOUS) | |
39 | ||
40 | /** | |
41 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
42 | * | |
43 | * This driver currently only supports the SSI running in I2S slave mode. | |
44 | * | |
45 | * The SSI has a limitation in that the samples must be in the same byte | |
46 | * order as the host CPU. This is because when multiple bytes are written | |
47 | * to the STX register, the bytes and bits must be written in the same | |
48 | * order. The STX is a shift register, so all the bits need to be aligned | |
49 | * (bit-endianness must match byte-endianness). Processors typically write | |
50 | * the bits within a byte in the same order that the bytes of a word are | |
51 | * written in. So if the host CPU is big-endian, then only big-endian | |
52 | * samples will be written to STX properly. | |
53 | */ | |
54 | #ifdef __BIG_ENDIAN | |
55 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
56 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
57 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
58 | #else | |
59 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
60 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
61 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
62 | #endif | |
63 | ||
d5a908b2 TT |
64 | /* SIER bitflag of interrupts to enable */ |
65 | #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \ | |
66 | CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \ | |
67 | CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \ | |
68 | CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \ | |
69 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN) | |
70 | ||
17467f23 TT |
71 | /** |
72 | * fsl_ssi_private: per-SSI private data | |
73 | * | |
17467f23 TT |
74 | * @ssi: pointer to the SSI's registers |
75 | * @ssi_phys: physical address of the SSI registers | |
76 | * @irq: IRQ of this SSI | |
be41e941 TT |
77 | * @first_stream: pointer to the stream that was opened first |
78 | * @second_stream: pointer to second stream | |
17467f23 TT |
79 | * @playback: the number of playback streams opened |
80 | * @capture: the number of capture streams opened | |
81 | * @cpu_dai: the CPU DAI for this device | |
82 | * @dev_attr: the sysfs device attribute structure | |
83 | * @stats: SSI statistics | |
f0fba2ad | 84 | * @name: name for this device |
17467f23 TT |
85 | */ |
86 | struct fsl_ssi_private { | |
17467f23 TT |
87 | struct ccsr_ssi __iomem *ssi; |
88 | dma_addr_t ssi_phys; | |
89 | unsigned int irq; | |
be41e941 TT |
90 | struct snd_pcm_substream *first_stream; |
91 | struct snd_pcm_substream *second_stream; | |
8e9d8690 | 92 | unsigned int fifo_depth; |
f0fba2ad | 93 | struct snd_soc_dai_driver cpu_dai_drv; |
17467f23 | 94 | struct device_attribute dev_attr; |
f0fba2ad | 95 | struct platform_device *pdev; |
17467f23 TT |
96 | |
97 | struct { | |
98 | unsigned int rfrc; | |
99 | unsigned int tfrc; | |
100 | unsigned int cmdau; | |
101 | unsigned int cmddu; | |
102 | unsigned int rxt; | |
103 | unsigned int rdr1; | |
104 | unsigned int rdr0; | |
105 | unsigned int tde1; | |
106 | unsigned int tde0; | |
107 | unsigned int roe1; | |
108 | unsigned int roe0; | |
109 | unsigned int tue1; | |
110 | unsigned int tue0; | |
111 | unsigned int tfs; | |
112 | unsigned int rfs; | |
113 | unsigned int tls; | |
114 | unsigned int rls; | |
115 | unsigned int rff1; | |
116 | unsigned int rff0; | |
117 | unsigned int tfe1; | |
118 | unsigned int tfe0; | |
119 | } stats; | |
f0fba2ad LG |
120 | |
121 | char name[1]; | |
17467f23 TT |
122 | }; |
123 | ||
124 | /** | |
125 | * fsl_ssi_isr: SSI interrupt handler | |
126 | * | |
127 | * Although it's possible to use the interrupt handler to send and receive | |
128 | * data to/from the SSI, we use the DMA instead. Programming is more | |
129 | * complicated, but the performance is much better. | |
130 | * | |
131 | * This interrupt handler is used only to gather statistics. | |
132 | * | |
133 | * @irq: IRQ of the SSI device | |
134 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
135 | */ | |
136 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
137 | { | |
138 | struct fsl_ssi_private *ssi_private = dev_id; | |
139 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
140 | irqreturn_t ret = IRQ_NONE; | |
141 | __be32 sisr; | |
142 | __be32 sisr2 = 0; | |
143 | ||
144 | /* We got an interrupt, so read the status register to see what we | |
145 | were interrupted for. We mask it with the Interrupt Enable register | |
146 | so that we only check for events that we're interested in. | |
147 | */ | |
d5a908b2 | 148 | sisr = in_be32(&ssi->sisr) & SIER_FLAGS; |
17467f23 TT |
149 | |
150 | if (sisr & CCSR_SSI_SISR_RFRC) { | |
151 | ssi_private->stats.rfrc++; | |
152 | sisr2 |= CCSR_SSI_SISR_RFRC; | |
153 | ret = IRQ_HANDLED; | |
154 | } | |
155 | ||
156 | if (sisr & CCSR_SSI_SISR_TFRC) { | |
157 | ssi_private->stats.tfrc++; | |
158 | sisr2 |= CCSR_SSI_SISR_TFRC; | |
159 | ret = IRQ_HANDLED; | |
160 | } | |
161 | ||
162 | if (sisr & CCSR_SSI_SISR_CMDAU) { | |
163 | ssi_private->stats.cmdau++; | |
164 | ret = IRQ_HANDLED; | |
165 | } | |
166 | ||
167 | if (sisr & CCSR_SSI_SISR_CMDDU) { | |
168 | ssi_private->stats.cmddu++; | |
169 | ret = IRQ_HANDLED; | |
170 | } | |
171 | ||
172 | if (sisr & CCSR_SSI_SISR_RXT) { | |
173 | ssi_private->stats.rxt++; | |
174 | ret = IRQ_HANDLED; | |
175 | } | |
176 | ||
177 | if (sisr & CCSR_SSI_SISR_RDR1) { | |
178 | ssi_private->stats.rdr1++; | |
179 | ret = IRQ_HANDLED; | |
180 | } | |
181 | ||
182 | if (sisr & CCSR_SSI_SISR_RDR0) { | |
183 | ssi_private->stats.rdr0++; | |
184 | ret = IRQ_HANDLED; | |
185 | } | |
186 | ||
187 | if (sisr & CCSR_SSI_SISR_TDE1) { | |
188 | ssi_private->stats.tde1++; | |
189 | ret = IRQ_HANDLED; | |
190 | } | |
191 | ||
192 | if (sisr & CCSR_SSI_SISR_TDE0) { | |
193 | ssi_private->stats.tde0++; | |
194 | ret = IRQ_HANDLED; | |
195 | } | |
196 | ||
197 | if (sisr & CCSR_SSI_SISR_ROE1) { | |
198 | ssi_private->stats.roe1++; | |
199 | sisr2 |= CCSR_SSI_SISR_ROE1; | |
200 | ret = IRQ_HANDLED; | |
201 | } | |
202 | ||
203 | if (sisr & CCSR_SSI_SISR_ROE0) { | |
204 | ssi_private->stats.roe0++; | |
205 | sisr2 |= CCSR_SSI_SISR_ROE0; | |
206 | ret = IRQ_HANDLED; | |
207 | } | |
208 | ||
209 | if (sisr & CCSR_SSI_SISR_TUE1) { | |
210 | ssi_private->stats.tue1++; | |
211 | sisr2 |= CCSR_SSI_SISR_TUE1; | |
212 | ret = IRQ_HANDLED; | |
213 | } | |
214 | ||
215 | if (sisr & CCSR_SSI_SISR_TUE0) { | |
216 | ssi_private->stats.tue0++; | |
217 | sisr2 |= CCSR_SSI_SISR_TUE0; | |
218 | ret = IRQ_HANDLED; | |
219 | } | |
220 | ||
221 | if (sisr & CCSR_SSI_SISR_TFS) { | |
222 | ssi_private->stats.tfs++; | |
223 | ret = IRQ_HANDLED; | |
224 | } | |
225 | ||
226 | if (sisr & CCSR_SSI_SISR_RFS) { | |
227 | ssi_private->stats.rfs++; | |
228 | ret = IRQ_HANDLED; | |
229 | } | |
230 | ||
231 | if (sisr & CCSR_SSI_SISR_TLS) { | |
232 | ssi_private->stats.tls++; | |
233 | ret = IRQ_HANDLED; | |
234 | } | |
235 | ||
236 | if (sisr & CCSR_SSI_SISR_RLS) { | |
237 | ssi_private->stats.rls++; | |
238 | ret = IRQ_HANDLED; | |
239 | } | |
240 | ||
241 | if (sisr & CCSR_SSI_SISR_RFF1) { | |
242 | ssi_private->stats.rff1++; | |
243 | ret = IRQ_HANDLED; | |
244 | } | |
245 | ||
246 | if (sisr & CCSR_SSI_SISR_RFF0) { | |
247 | ssi_private->stats.rff0++; | |
248 | ret = IRQ_HANDLED; | |
249 | } | |
250 | ||
251 | if (sisr & CCSR_SSI_SISR_TFE1) { | |
252 | ssi_private->stats.tfe1++; | |
253 | ret = IRQ_HANDLED; | |
254 | } | |
255 | ||
256 | if (sisr & CCSR_SSI_SISR_TFE0) { | |
257 | ssi_private->stats.tfe0++; | |
258 | ret = IRQ_HANDLED; | |
259 | } | |
260 | ||
261 | /* Clear the bits that we set */ | |
262 | if (sisr2) | |
263 | out_be32(&ssi->sisr, sisr2); | |
264 | ||
265 | return ret; | |
266 | } | |
267 | ||
268 | /** | |
269 | * fsl_ssi_startup: create a new substream | |
270 | * | |
271 | * This is the first function called when a stream is opened. | |
272 | * | |
273 | * If this is the first stream open, then grab the IRQ and program most of | |
274 | * the SSI registers. | |
275 | */ | |
dee89c4d MB |
276 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
277 | struct snd_soc_dai *dai) | |
17467f23 TT |
278 | { |
279 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5e538eca TT |
280 | struct fsl_ssi_private *ssi_private = |
281 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
282 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates; | |
17467f23 TT |
283 | |
284 | /* | |
285 | * If this is the first stream opened, then request the IRQ | |
286 | * and initialize the SSI registers. | |
287 | */ | |
5e538eca | 288 | if (!ssi_private->first_stream) { |
17467f23 | 289 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
17467f23 | 290 | |
5e538eca TT |
291 | ssi_private->first_stream = substream; |
292 | ||
17467f23 TT |
293 | /* |
294 | * Section 16.5 of the MPC8610 reference manual says that the | |
295 | * SSI needs to be disabled before updating the registers we set | |
296 | * here. | |
297 | */ | |
298 | clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); | |
299 | ||
300 | /* | |
301 | * Program the SSI into I2S Slave Non-Network Synchronous mode. | |
302 | * Also enable the transmit and receive FIFO. | |
303 | * | |
304 | * FIXME: Little-endian samples require a different shift dir | |
305 | */ | |
a454dad1 TT |
306 | clrsetbits_be32(&ssi->scr, |
307 | CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN, | |
308 | CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE | |
5e538eca | 309 | | (synchronous ? CCSR_SSI_SCR_SYN : 0)); |
17467f23 TT |
310 | |
311 | out_be32(&ssi->stcr, | |
312 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 | | |
313 | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS | | |
314 | CCSR_SSI_STCR_TSCKP); | |
315 | ||
316 | out_be32(&ssi->srcr, | |
317 | CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 | | |
318 | CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS | | |
319 | CCSR_SSI_SRCR_RSCKP); | |
320 | ||
321 | /* | |
322 | * The DC and PM bits are only used if the SSI is the clock | |
323 | * master. | |
324 | */ | |
325 | ||
5e538eca | 326 | /* Enable the interrupts and DMA requests */ |
d5a908b2 | 327 | out_be32(&ssi->sier, SIER_FLAGS); |
17467f23 TT |
328 | |
329 | /* | |
330 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We | |
8e9d8690 TT |
331 | * don't use FIFO 1. We program the transmit water to signal a |
332 | * DMA transfer if there are only two (or fewer) elements left | |
333 | * in the FIFO. Two elements equals one frame (left channel, | |
334 | * right channel). This value, however, depends on the depth of | |
335 | * the transmit buffer. | |
336 | * | |
337 | * We program the receive FIFO to notify us if at least two | |
338 | * elements (one frame) have been written to the FIFO. We could | |
339 | * make this value larger (and maybe we should), but this way | |
340 | * data will be written to memory as soon as it's available. | |
17467f23 TT |
341 | */ |
342 | out_be32(&ssi->sfcsr, | |
8e9d8690 TT |
343 | CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) | |
344 | CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2)); | |
17467f23 TT |
345 | |
346 | /* | |
347 | * We keep the SSI disabled because if we enable it, then the | |
348 | * DMA controller will start. It's not supposed to start until | |
349 | * the SCR.TE (or SCR.RE) bit is set, but it does anyway. The | |
350 | * DMA controller will transfer one "BWC" of data (i.e. the | |
351 | * amount of data that the MR.BWC bits are set to). The reason | |
352 | * this is bad is because at this point, the PCM driver has not | |
353 | * finished initializing the DMA controller. | |
354 | */ | |
5e538eca TT |
355 | } else { |
356 | if (synchronous) { | |
357 | struct snd_pcm_runtime *first_runtime = | |
358 | ssi_private->first_stream->runtime; | |
359 | /* | |
360 | * This is the second stream open, and we're in | |
361 | * synchronous mode, so we need to impose sample | |
362 | * sample size constraints. This is because STCCR is | |
363 | * used for playback and capture in synchronous mode, | |
364 | * so there's no way to specify different word | |
365 | * lengths. | |
366 | * | |
367 | * Note that this can cause a race condition if the | |
368 | * second stream is opened before the first stream is | |
369 | * fully initialized. We provide some protection by | |
370 | * checking to make sure the first stream is | |
371 | * initialized, but it's not perfect. ALSA sometimes | |
372 | * re-initializes the driver with a different sample | |
373 | * rate or size. If the second stream is opened | |
374 | * before the first stream has received its final | |
375 | * parameters, then the second stream may be | |
376 | * constrained to the wrong sample rate or size. | |
377 | */ | |
378 | if (!first_runtime->sample_bits) { | |
379 | dev_err(substream->pcm->card->dev, | |
380 | "set sample size in %s stream first\n", | |
381 | substream->stream == | |
382 | SNDRV_PCM_STREAM_PLAYBACK | |
383 | ? "capture" : "playback"); | |
384 | return -EAGAIN; | |
385 | } | |
be41e941 | 386 | |
a454dad1 TT |
387 | snd_pcm_hw_constraint_minmax(substream->runtime, |
388 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
389 | first_runtime->sample_bits, | |
390 | first_runtime->sample_bits); | |
5e538eca | 391 | } |
be41e941 TT |
392 | |
393 | ssi_private->second_stream = substream; | |
394 | } | |
395 | ||
17467f23 TT |
396 | return 0; |
397 | } | |
398 | ||
399 | /** | |
85ef2375 | 400 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
401 | * |
402 | * Most of the SSI registers have been programmed in the startup function, | |
403 | * but the word length must be programmed here. Unfortunately, programming | |
404 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
405 | * cause a problem with supporting simultaneous playback and capture. If | |
406 | * the SSI is already playing a stream, then that stream may be temporarily | |
407 | * stopped when you start capture. | |
408 | * | |
409 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
410 | * clock master. | |
411 | */ | |
85ef2375 TT |
412 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
413 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 414 | { |
f0fba2ad | 415 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
5e538eca TT |
416 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
417 | unsigned int sample_size = | |
418 | snd_pcm_format_width(params_format(hw_params)); | |
419 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); | |
420 | int enabled = in_be32(&ssi->scr) & CCSR_SSI_SCR_SSIEN; | |
17467f23 | 421 | |
5e538eca TT |
422 | /* |
423 | * If we're in synchronous mode, and the SSI is already enabled, | |
424 | * then STCCR is already set properly. | |
425 | */ | |
426 | if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) | |
427 | return 0; | |
17467f23 | 428 | |
5e538eca TT |
429 | /* |
430 | * FIXME: The documentation says that SxCCR[WL] should not be | |
431 | * modified while the SSI is enabled. The only time this can | |
432 | * happen is if we're trying to do simultaneous playback and | |
433 | * capture in asynchronous mode. Unfortunately, I have been enable | |
434 | * to get that to work at all on the P1022DS. Therefore, we don't | |
435 | * bother to disable/enable the SSI when setting SxCCR[WL], because | |
436 | * the SSI will stop anyway. Maybe one day, this will get fixed. | |
437 | */ | |
17467f23 | 438 | |
5e538eca TT |
439 | /* In synchronous mode, the SSI uses STCCR for capture */ |
440 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || | |
441 | ssi_private->cpu_dai_drv.symmetric_rates) | |
442 | clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); | |
443 | else | |
444 | clrsetbits_be32(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); | |
17467f23 TT |
445 | |
446 | return 0; | |
447 | } | |
448 | ||
449 | /** | |
450 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
451 | * | |
452 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
453 | * transfer of data. | |
454 | * | |
455 | * The DMA channel is in external master start and pause mode, which | |
456 | * means the SSI completely controls the flow of data. | |
457 | */ | |
dee89c4d MB |
458 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
459 | struct snd_soc_dai *dai) | |
17467f23 TT |
460 | { |
461 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 462 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 TT |
463 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
464 | ||
465 | switch (cmd) { | |
466 | case SNDRV_PCM_TRIGGER_START: | |
17467f23 | 467 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 468 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
be41e941 TT |
469 | setbits32(&ssi->scr, |
470 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE); | |
a4d11fe5 | 471 | else |
be41e941 TT |
472 | setbits32(&ssi->scr, |
473 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE); | |
17467f23 TT |
474 | break; |
475 | ||
476 | case SNDRV_PCM_TRIGGER_STOP: | |
17467f23 TT |
477 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
478 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
479 | clrbits32(&ssi->scr, CCSR_SSI_SCR_TE); | |
480 | else | |
481 | clrbits32(&ssi->scr, CCSR_SSI_SCR_RE); | |
482 | break; | |
483 | ||
484 | default: | |
485 | return -EINVAL; | |
486 | } | |
487 | ||
488 | return 0; | |
489 | } | |
490 | ||
491 | /** | |
492 | * fsl_ssi_shutdown: shutdown the SSI | |
493 | * | |
494 | * Shutdown the SSI if there are no other substreams open. | |
495 | */ | |
dee89c4d MB |
496 | static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, |
497 | struct snd_soc_dai *dai) | |
17467f23 TT |
498 | { |
499 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 500 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 | 501 | |
be41e941 TT |
502 | if (ssi_private->first_stream == substream) |
503 | ssi_private->first_stream = ssi_private->second_stream; | |
504 | ||
505 | ssi_private->second_stream = NULL; | |
506 | ||
17467f23 | 507 | /* |
1fab6caf | 508 | * If this is the last active substream, disable the SSI. |
17467f23 | 509 | */ |
5e538eca | 510 | if (!ssi_private->first_stream) { |
17467f23 TT |
511 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
512 | ||
513 | clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); | |
17467f23 TT |
514 | } |
515 | } | |
516 | ||
85e7652d | 517 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
6335d055 EM |
518 | .startup = fsl_ssi_startup, |
519 | .hw_params = fsl_ssi_hw_params, | |
520 | .shutdown = fsl_ssi_shutdown, | |
521 | .trigger = fsl_ssi_trigger, | |
6335d055 EM |
522 | }; |
523 | ||
f0fba2ad LG |
524 | /* Template for the CPU dai driver structure */ |
525 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
17467f23 TT |
526 | .playback = { |
527 | /* The SSI does not support monaural audio. */ | |
528 | .channels_min = 2, | |
529 | .channels_max = 2, | |
530 | .rates = FSLSSI_I2S_RATES, | |
531 | .formats = FSLSSI_I2S_FORMATS, | |
532 | }, | |
533 | .capture = { | |
534 | .channels_min = 2, | |
535 | .channels_max = 2, | |
536 | .rates = FSLSSI_I2S_RATES, | |
537 | .formats = FSLSSI_I2S_FORMATS, | |
538 | }, | |
6335d055 | 539 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
540 | }; |
541 | ||
d5a908b2 TT |
542 | /* Show the statistics of a flag only if its interrupt is enabled. The |
543 | * compiler will optimze this code to a no-op if the interrupt is not | |
544 | * enabled. | |
545 | */ | |
546 | #define SIER_SHOW(flag, name) \ | |
547 | do { \ | |
548 | if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \ | |
549 | length += sprintf(buf + length, #name "=%u\n", \ | |
550 | ssi_private->stats.name); \ | |
551 | } while (0) | |
552 | ||
553 | ||
17467f23 TT |
554 | /** |
555 | * fsl_sysfs_ssi_show: display SSI statistics | |
556 | * | |
d5a908b2 TT |
557 | * Display the statistics for the current SSI device. To avoid confusion, |
558 | * we only show those counts that are enabled. | |
17467f23 TT |
559 | */ |
560 | static ssize_t fsl_sysfs_ssi_show(struct device *dev, | |
561 | struct device_attribute *attr, char *buf) | |
562 | { | |
563 | struct fsl_ssi_private *ssi_private = | |
d5a908b2 TT |
564 | container_of(attr, struct fsl_ssi_private, dev_attr); |
565 | ssize_t length = 0; | |
566 | ||
567 | SIER_SHOW(RFRC_EN, rfrc); | |
568 | SIER_SHOW(TFRC_EN, tfrc); | |
569 | SIER_SHOW(CMDAU_EN, cmdau); | |
570 | SIER_SHOW(CMDDU_EN, cmddu); | |
571 | SIER_SHOW(RXT_EN, rxt); | |
572 | SIER_SHOW(RDR1_EN, rdr1); | |
573 | SIER_SHOW(RDR0_EN, rdr0); | |
574 | SIER_SHOW(TDE1_EN, tde1); | |
575 | SIER_SHOW(TDE0_EN, tde0); | |
576 | SIER_SHOW(ROE1_EN, roe1); | |
577 | SIER_SHOW(ROE0_EN, roe0); | |
578 | SIER_SHOW(TUE1_EN, tue1); | |
579 | SIER_SHOW(TUE0_EN, tue0); | |
580 | SIER_SHOW(TFS_EN, tfs); | |
581 | SIER_SHOW(RFS_EN, rfs); | |
582 | SIER_SHOW(TLS_EN, tls); | |
583 | SIER_SHOW(RLS_EN, rls); | |
584 | SIER_SHOW(RFF1_EN, rff1); | |
585 | SIER_SHOW(RFF0_EN, rff0); | |
586 | SIER_SHOW(TFE1_EN, tfe1); | |
587 | SIER_SHOW(TFE0_EN, tfe0); | |
17467f23 TT |
588 | |
589 | return length; | |
590 | } | |
591 | ||
592 | /** | |
f0fba2ad | 593 | * Make every character in a string lower-case |
17467f23 | 594 | */ |
f0fba2ad LG |
595 | static void make_lowercase(char *s) |
596 | { | |
597 | char *p = s; | |
598 | char c; | |
599 | ||
600 | while ((c = *p)) { | |
601 | if ((c >= 'A') && (c <= 'Z')) | |
602 | *p = c + ('a' - 'A'); | |
603 | p++; | |
604 | } | |
605 | } | |
606 | ||
f07eb223 | 607 | static int __devinit fsl_ssi_probe(struct platform_device *pdev) |
17467f23 | 608 | { |
17467f23 TT |
609 | struct fsl_ssi_private *ssi_private; |
610 | int ret = 0; | |
87a0632b | 611 | struct device_attribute *dev_attr = NULL; |
38fec727 | 612 | struct device_node *np = pdev->dev.of_node; |
f0fba2ad | 613 | const char *p, *sprop; |
8e9d8690 | 614 | const uint32_t *iprop; |
f0fba2ad LG |
615 | struct resource res; |
616 | char name[64]; | |
17467f23 | 617 | |
ff71334a TT |
618 | /* SSIs that are not connected on the board should have a |
619 | * status = "disabled" | |
620 | * property in their device tree nodes. | |
f0fba2ad | 621 | */ |
ff71334a | 622 | if (!of_device_is_available(np)) |
f0fba2ad LG |
623 | return -ENODEV; |
624 | ||
ff71334a TT |
625 | /* Check for a codec-handle property. */ |
626 | if (!of_get_property(np, "codec-handle", NULL)) { | |
38fec727 | 627 | dev_err(&pdev->dev, "missing codec-handle property\n"); |
ff71334a TT |
628 | return -ENODEV; |
629 | } | |
630 | ||
f0fba2ad LG |
631 | /* We only support the SSI in "I2S Slave" mode */ |
632 | sprop = of_get_property(np, "fsl,mode", NULL); | |
633 | if (!sprop || strcmp(sprop, "i2s-slave")) { | |
38fec727 | 634 | dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop); |
f0fba2ad LG |
635 | return -ENODEV; |
636 | } | |
637 | ||
638 | /* The DAI name is the last part of the full name of the node. */ | |
639 | p = strrchr(np->full_name, '/') + 1; | |
640 | ssi_private = kzalloc(sizeof(struct fsl_ssi_private) + strlen(p), | |
641 | GFP_KERNEL); | |
17467f23 | 642 | if (!ssi_private) { |
38fec727 | 643 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
f0fba2ad | 644 | return -ENOMEM; |
17467f23 | 645 | } |
17467f23 | 646 | |
f0fba2ad | 647 | strcpy(ssi_private->name, p); |
17467f23 | 648 | |
f0fba2ad LG |
649 | /* Initialize this copy of the CPU DAI driver structure */ |
650 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
651 | sizeof(fsl_ssi_dai_template)); | |
652 | ssi_private->cpu_dai_drv.name = ssi_private->name; | |
653 | ||
654 | /* Get the addresses and IRQ */ | |
655 | ret = of_address_to_resource(np, 0, &res); | |
656 | if (ret) { | |
38fec727 | 657 | dev_err(&pdev->dev, "could not determine device resources\n"); |
1fab6caf | 658 | goto error_kmalloc; |
f0fba2ad | 659 | } |
147dfe90 TT |
660 | ssi_private->ssi = of_iomap(np, 0); |
661 | if (!ssi_private->ssi) { | |
662 | dev_err(&pdev->dev, "could not map device resources\n"); | |
1fab6caf TT |
663 | ret = -ENOMEM; |
664 | goto error_kmalloc; | |
147dfe90 | 665 | } |
f0fba2ad | 666 | ssi_private->ssi_phys = res.start; |
1fab6caf | 667 | |
f0fba2ad | 668 | ssi_private->irq = irq_of_parse_and_map(np, 0); |
1fab6caf TT |
669 | if (ssi_private->irq == NO_IRQ) { |
670 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); | |
671 | ret = -ENXIO; | |
672 | goto error_iomap; | |
673 | } | |
674 | ||
675 | /* The 'name' should not have any slashes in it. */ | |
676 | ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, ssi_private->name, | |
677 | ssi_private); | |
678 | if (ret < 0) { | |
679 | dev_err(&pdev->dev, "could not claim irq %u\n", ssi_private->irq); | |
680 | goto error_irqmap; | |
681 | } | |
17467f23 | 682 | |
f0fba2ad | 683 | /* Are the RX and the TX clocks locked? */ |
5e538eca | 684 | if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) |
f0fba2ad | 685 | ssi_private->cpu_dai_drv.symmetric_rates = 1; |
17467f23 | 686 | |
8e9d8690 TT |
687 | /* Determine the FIFO depth. */ |
688 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
689 | if (iprop) | |
147dfe90 | 690 | ssi_private->fifo_depth = be32_to_cpup(iprop); |
8e9d8690 TT |
691 | else |
692 | /* Older 8610 DTs didn't have the fifo-depth property */ | |
693 | ssi_private->fifo_depth = 8; | |
694 | ||
17467f23 | 695 | /* Initialize the the device_attribute structure */ |
f0fba2ad | 696 | dev_attr = &ssi_private->dev_attr; |
0f768a72 | 697 | sysfs_attr_init(&dev_attr->attr); |
f0fba2ad | 698 | dev_attr->attr.name = "statistics"; |
17467f23 TT |
699 | dev_attr->attr.mode = S_IRUGO; |
700 | dev_attr->show = fsl_sysfs_ssi_show; | |
701 | ||
38fec727 | 702 | ret = device_create_file(&pdev->dev, dev_attr); |
17467f23 | 703 | if (ret) { |
38fec727 | 704 | dev_err(&pdev->dev, "could not create sysfs %s file\n", |
17467f23 | 705 | ssi_private->dev_attr.attr.name); |
1fab6caf | 706 | goto error_irq; |
17467f23 TT |
707 | } |
708 | ||
f0fba2ad | 709 | /* Register with ASoC */ |
38fec727 | 710 | dev_set_drvdata(&pdev->dev, ssi_private); |
3f4b783c | 711 | |
38fec727 | 712 | ret = snd_soc_register_dai(&pdev->dev, &ssi_private->cpu_dai_drv); |
87a0632b | 713 | if (ret) { |
38fec727 | 714 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); |
1fab6caf | 715 | goto error_dev; |
f0fba2ad LG |
716 | } |
717 | ||
718 | /* Trigger the machine driver's probe function. The platform driver | |
719 | * name of the machine driver is taken from the /model property of the | |
720 | * device tree. We also pass the address of the CPU DAI driver | |
721 | * structure. | |
722 | */ | |
723 | sprop = of_get_property(of_find_node_by_path("/"), "model", NULL); | |
724 | /* Sometimes the model name has a "fsl," prefix, so we strip that. */ | |
725 | p = strrchr(sprop, ','); | |
726 | if (p) | |
727 | sprop = p + 1; | |
728 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
729 | make_lowercase(name); | |
730 | ||
731 | ssi_private->pdev = | |
38fec727 | 732 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
f0fba2ad LG |
733 | if (IS_ERR(ssi_private->pdev)) { |
734 | ret = PTR_ERR(ssi_private->pdev); | |
38fec727 | 735 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
1fab6caf | 736 | goto error_dai; |
3f4b783c | 737 | } |
17467f23 | 738 | |
f0fba2ad | 739 | return 0; |
87a0632b | 740 | |
1fab6caf | 741 | error_dai: |
38fec727 | 742 | snd_soc_unregister_dai(&pdev->dev); |
1fab6caf TT |
743 | |
744 | error_dev: | |
38fec727 | 745 | dev_set_drvdata(&pdev->dev, NULL); |
1fab6caf TT |
746 | device_remove_file(&pdev->dev, dev_attr); |
747 | ||
748 | error_irq: | |
749 | free_irq(ssi_private->irq, ssi_private); | |
750 | ||
751 | error_irqmap: | |
87a0632b | 752 | irq_dispose_mapping(ssi_private->irq); |
1fab6caf TT |
753 | |
754 | error_iomap: | |
87a0632b | 755 | iounmap(ssi_private->ssi); |
1fab6caf TT |
756 | |
757 | error_kmalloc: | |
87a0632b TT |
758 | kfree(ssi_private); |
759 | ||
760 | return ret; | |
17467f23 | 761 | } |
17467f23 | 762 | |
38fec727 | 763 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 764 | { |
38fec727 | 765 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
17467f23 | 766 | |
f0fba2ad | 767 | platform_device_unregister(ssi_private->pdev); |
38fec727 TT |
768 | snd_soc_unregister_dai(&pdev->dev); |
769 | device_remove_file(&pdev->dev, &ssi_private->dev_attr); | |
3f4b783c | 770 | |
1fab6caf TT |
771 | free_irq(ssi_private->irq, ssi_private); |
772 | irq_dispose_mapping(ssi_private->irq); | |
773 | ||
17467f23 | 774 | kfree(ssi_private); |
38fec727 | 775 | dev_set_drvdata(&pdev->dev, NULL); |
f0fba2ad LG |
776 | |
777 | return 0; | |
17467f23 | 778 | } |
f0fba2ad LG |
779 | |
780 | static const struct of_device_id fsl_ssi_ids[] = { | |
781 | { .compatible = "fsl,mpc8610-ssi", }, | |
782 | {} | |
783 | }; | |
784 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
785 | ||
f07eb223 | 786 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
787 | .driver = { |
788 | .name = "fsl-ssi-dai", | |
789 | .owner = THIS_MODULE, | |
790 | .of_match_table = fsl_ssi_ids, | |
791 | }, | |
792 | .probe = fsl_ssi_probe, | |
793 | .remove = fsl_ssi_remove, | |
794 | }; | |
17467f23 | 795 | |
ba0a7e02 | 796 | module_platform_driver(fsl_ssi_driver); |
a454dad1 | 797 | |
17467f23 TT |
798 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
799 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 800 | MODULE_LICENSE("GPL v2"); |