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17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
de623ece MP |
11 | * |
12 | * | |
13 | * Some notes why imx-pcm-fiq is used instead of DMA on some boards: | |
14 | * | |
15 | * The i.MX SSI core has some nasty limitations in AC97 mode. While most | |
16 | * sane processor vendors have a FIFO per AC97 slot, the i.MX has only | |
17 | * one FIFO which combines all valid receive slots. We cannot even select | |
18 | * which slots we want to receive. The WM9712 with which this driver | |
19 | * was developed with always sends GPIO status data in slot 12 which | |
20 | * we receive in our (PCM-) data stream. The only chance we have is to | |
21 | * manually skip this data in the FIQ handler. With sampling rates different | |
22 | * from 48000Hz not every frame has valid receive data, so the ratio | |
23 | * between pcm data and GPIO status data changes. Our FIQ handler is not | |
24 | * able to handle this, hence this driver only works with 48000Hz sampling | |
25 | * rate. | |
26 | * Reading and writing AC97 registers is another challenge. The core | |
27 | * provides us status bits when the read register is updated with *another* | |
28 | * value. When we read the same register two times (and the register still | |
29 | * contains the same value) these status bits are not set. We work | |
30 | * around this by not polling these bits but only wait a fixed delay. | |
17467f23 TT |
31 | */ |
32 | ||
33 | #include <linux/init.h> | |
dfa1a107 | 34 | #include <linux/io.h> |
17467f23 TT |
35 | #include <linux/module.h> |
36 | #include <linux/interrupt.h> | |
95cd98f9 | 37 | #include <linux/clk.h> |
17467f23 TT |
38 | #include <linux/device.h> |
39 | #include <linux/delay.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
aafa85e7 | 41 | #include <linux/spinlock.h> |
dfa1a107 SG |
42 | #include <linux/of_address.h> |
43 | #include <linux/of_irq.h> | |
f0fba2ad | 44 | #include <linux/of_platform.h> |
17467f23 | 45 | |
17467f23 TT |
46 | #include <sound/core.h> |
47 | #include <sound/pcm.h> | |
48 | #include <sound/pcm_params.h> | |
49 | #include <sound/initval.h> | |
50 | #include <sound/soc.h> | |
a8909c9b | 51 | #include <sound/dmaengine_pcm.h> |
17467f23 | 52 | |
17467f23 | 53 | #include "fsl_ssi.h" |
09ce1111 | 54 | #include "imx-pcm.h" |
17467f23 | 55 | |
dfa1a107 SG |
56 | #ifdef PPC |
57 | #define read_ssi(addr) in_be32(addr) | |
58 | #define write_ssi(val, addr) out_be32(addr, val) | |
59 | #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set) | |
0a9eaa39 | 60 | #else |
dfa1a107 SG |
61 | #define read_ssi(addr) readl(addr) |
62 | #define write_ssi(val, addr) writel(val, addr) | |
63 | /* | |
64 | * FIXME: Proper locking should be added at write_ssi_mask caller level | |
65 | * to ensure this register read/modify/write sequence is race free. | |
66 | */ | |
67 | static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set) | |
68 | { | |
69 | u32 val = readl(addr); | |
70 | val = (val & ~clear) | set; | |
71 | writel(val, addr); | |
72 | } | |
73 | #endif | |
74 | ||
17467f23 TT |
75 | /** |
76 | * FSLSSI_I2S_RATES: sample rates supported by the I2S | |
77 | * | |
78 | * This driver currently only supports the SSI running in I2S slave mode, | |
79 | * which means the codec determines the sample rate. Therefore, we tell | |
80 | * ALSA that we support all rates and let the codec driver decide what rates | |
81 | * are really supported. | |
82 | */ | |
83 | #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ | |
84 | SNDRV_PCM_RATE_CONTINUOUS) | |
85 | ||
86 | /** | |
87 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
88 | * | |
89 | * This driver currently only supports the SSI running in I2S slave mode. | |
90 | * | |
91 | * The SSI has a limitation in that the samples must be in the same byte | |
92 | * order as the host CPU. This is because when multiple bytes are written | |
93 | * to the STX register, the bytes and bits must be written in the same | |
94 | * order. The STX is a shift register, so all the bits need to be aligned | |
95 | * (bit-endianness must match byte-endianness). Processors typically write | |
96 | * the bits within a byte in the same order that the bytes of a word are | |
97 | * written in. So if the host CPU is big-endian, then only big-endian | |
98 | * samples will be written to STX properly. | |
99 | */ | |
100 | #ifdef __BIG_ENDIAN | |
101 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
102 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
103 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
104 | #else | |
105 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
106 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
107 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
108 | #endif | |
109 | ||
d5a908b2 TT |
110 | /* SIER bitflag of interrupts to enable */ |
111 | #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \ | |
112 | CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \ | |
113 | CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \ | |
114 | CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \ | |
115 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN) | |
116 | ||
17467f23 TT |
117 | /** |
118 | * fsl_ssi_private: per-SSI private data | |
119 | * | |
17467f23 TT |
120 | * @ssi: pointer to the SSI's registers |
121 | * @ssi_phys: physical address of the SSI registers | |
122 | * @irq: IRQ of this SSI | |
17467f23 TT |
123 | * @playback: the number of playback streams opened |
124 | * @capture: the number of capture streams opened | |
125 | * @cpu_dai: the CPU DAI for this device | |
126 | * @dev_attr: the sysfs device attribute structure | |
127 | * @stats: SSI statistics | |
f0fba2ad | 128 | * @name: name for this device |
17467f23 TT |
129 | */ |
130 | struct fsl_ssi_private { | |
17467f23 TT |
131 | struct ccsr_ssi __iomem *ssi; |
132 | dma_addr_t ssi_phys; | |
133 | unsigned int irq; | |
8e9d8690 | 134 | unsigned int fifo_depth; |
f0fba2ad | 135 | struct snd_soc_dai_driver cpu_dai_drv; |
17467f23 | 136 | struct device_attribute dev_attr; |
f0fba2ad | 137 | struct platform_device *pdev; |
17467f23 | 138 | |
09ce1111 SG |
139 | bool new_binding; |
140 | bool ssi_on_imx; | |
cd7f0295 | 141 | bool imx_ac97; |
de623ece | 142 | bool use_dma; |
aafa85e7 | 143 | bool baudclk_locked; |
2924a998 | 144 | u8 i2s_mode; |
aafa85e7 NC |
145 | spinlock_t baudclk_lock; |
146 | struct clk *baudclk; | |
95cd98f9 | 147 | struct clk *clk; |
a8909c9b LPC |
148 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
149 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
150 | struct imx_dma_data filter_data_tx; | |
151 | struct imx_dma_data filter_data_rx; | |
de623ece | 152 | struct imx_pcm_fiq_params fiq_params; |
09ce1111 | 153 | |
17467f23 TT |
154 | struct { |
155 | unsigned int rfrc; | |
156 | unsigned int tfrc; | |
157 | unsigned int cmdau; | |
158 | unsigned int cmddu; | |
159 | unsigned int rxt; | |
160 | unsigned int rdr1; | |
161 | unsigned int rdr0; | |
162 | unsigned int tde1; | |
163 | unsigned int tde0; | |
164 | unsigned int roe1; | |
165 | unsigned int roe0; | |
166 | unsigned int tue1; | |
167 | unsigned int tue0; | |
168 | unsigned int tfs; | |
169 | unsigned int rfs; | |
170 | unsigned int tls; | |
171 | unsigned int rls; | |
172 | unsigned int rff1; | |
173 | unsigned int rff0; | |
174 | unsigned int tfe1; | |
175 | unsigned int tfe0; | |
176 | } stats; | |
f0fba2ad LG |
177 | |
178 | char name[1]; | |
17467f23 TT |
179 | }; |
180 | ||
181 | /** | |
182 | * fsl_ssi_isr: SSI interrupt handler | |
183 | * | |
184 | * Although it's possible to use the interrupt handler to send and receive | |
185 | * data to/from the SSI, we use the DMA instead. Programming is more | |
186 | * complicated, but the performance is much better. | |
187 | * | |
188 | * This interrupt handler is used only to gather statistics. | |
189 | * | |
190 | * @irq: IRQ of the SSI device | |
191 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
192 | */ | |
193 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
194 | { | |
195 | struct fsl_ssi_private *ssi_private = dev_id; | |
196 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
197 | irqreturn_t ret = IRQ_NONE; | |
198 | __be32 sisr; | |
199 | __be32 sisr2 = 0; | |
200 | ||
201 | /* We got an interrupt, so read the status register to see what we | |
202 | were interrupted for. We mask it with the Interrupt Enable register | |
203 | so that we only check for events that we're interested in. | |
204 | */ | |
dfa1a107 | 205 | sisr = read_ssi(&ssi->sisr) & SIER_FLAGS; |
17467f23 TT |
206 | |
207 | if (sisr & CCSR_SSI_SISR_RFRC) { | |
208 | ssi_private->stats.rfrc++; | |
209 | sisr2 |= CCSR_SSI_SISR_RFRC; | |
210 | ret = IRQ_HANDLED; | |
211 | } | |
212 | ||
213 | if (sisr & CCSR_SSI_SISR_TFRC) { | |
214 | ssi_private->stats.tfrc++; | |
215 | sisr2 |= CCSR_SSI_SISR_TFRC; | |
216 | ret = IRQ_HANDLED; | |
217 | } | |
218 | ||
219 | if (sisr & CCSR_SSI_SISR_CMDAU) { | |
220 | ssi_private->stats.cmdau++; | |
221 | ret = IRQ_HANDLED; | |
222 | } | |
223 | ||
224 | if (sisr & CCSR_SSI_SISR_CMDDU) { | |
225 | ssi_private->stats.cmddu++; | |
226 | ret = IRQ_HANDLED; | |
227 | } | |
228 | ||
229 | if (sisr & CCSR_SSI_SISR_RXT) { | |
230 | ssi_private->stats.rxt++; | |
231 | ret = IRQ_HANDLED; | |
232 | } | |
233 | ||
234 | if (sisr & CCSR_SSI_SISR_RDR1) { | |
235 | ssi_private->stats.rdr1++; | |
236 | ret = IRQ_HANDLED; | |
237 | } | |
238 | ||
239 | if (sisr & CCSR_SSI_SISR_RDR0) { | |
240 | ssi_private->stats.rdr0++; | |
241 | ret = IRQ_HANDLED; | |
242 | } | |
243 | ||
244 | if (sisr & CCSR_SSI_SISR_TDE1) { | |
245 | ssi_private->stats.tde1++; | |
246 | ret = IRQ_HANDLED; | |
247 | } | |
248 | ||
249 | if (sisr & CCSR_SSI_SISR_TDE0) { | |
250 | ssi_private->stats.tde0++; | |
251 | ret = IRQ_HANDLED; | |
252 | } | |
253 | ||
254 | if (sisr & CCSR_SSI_SISR_ROE1) { | |
255 | ssi_private->stats.roe1++; | |
256 | sisr2 |= CCSR_SSI_SISR_ROE1; | |
257 | ret = IRQ_HANDLED; | |
258 | } | |
259 | ||
260 | if (sisr & CCSR_SSI_SISR_ROE0) { | |
261 | ssi_private->stats.roe0++; | |
262 | sisr2 |= CCSR_SSI_SISR_ROE0; | |
263 | ret = IRQ_HANDLED; | |
264 | } | |
265 | ||
266 | if (sisr & CCSR_SSI_SISR_TUE1) { | |
267 | ssi_private->stats.tue1++; | |
268 | sisr2 |= CCSR_SSI_SISR_TUE1; | |
269 | ret = IRQ_HANDLED; | |
270 | } | |
271 | ||
272 | if (sisr & CCSR_SSI_SISR_TUE0) { | |
273 | ssi_private->stats.tue0++; | |
274 | sisr2 |= CCSR_SSI_SISR_TUE0; | |
275 | ret = IRQ_HANDLED; | |
276 | } | |
277 | ||
278 | if (sisr & CCSR_SSI_SISR_TFS) { | |
279 | ssi_private->stats.tfs++; | |
280 | ret = IRQ_HANDLED; | |
281 | } | |
282 | ||
283 | if (sisr & CCSR_SSI_SISR_RFS) { | |
284 | ssi_private->stats.rfs++; | |
285 | ret = IRQ_HANDLED; | |
286 | } | |
287 | ||
288 | if (sisr & CCSR_SSI_SISR_TLS) { | |
289 | ssi_private->stats.tls++; | |
290 | ret = IRQ_HANDLED; | |
291 | } | |
292 | ||
293 | if (sisr & CCSR_SSI_SISR_RLS) { | |
294 | ssi_private->stats.rls++; | |
295 | ret = IRQ_HANDLED; | |
296 | } | |
297 | ||
298 | if (sisr & CCSR_SSI_SISR_RFF1) { | |
299 | ssi_private->stats.rff1++; | |
300 | ret = IRQ_HANDLED; | |
301 | } | |
302 | ||
303 | if (sisr & CCSR_SSI_SISR_RFF0) { | |
304 | ssi_private->stats.rff0++; | |
305 | ret = IRQ_HANDLED; | |
306 | } | |
307 | ||
308 | if (sisr & CCSR_SSI_SISR_TFE1) { | |
309 | ssi_private->stats.tfe1++; | |
310 | ret = IRQ_HANDLED; | |
311 | } | |
312 | ||
313 | if (sisr & CCSR_SSI_SISR_TFE0) { | |
314 | ssi_private->stats.tfe0++; | |
315 | ret = IRQ_HANDLED; | |
316 | } | |
317 | ||
318 | /* Clear the bits that we set */ | |
319 | if (sisr2) | |
dfa1a107 | 320 | write_ssi(sisr2, &ssi->sisr); |
17467f23 TT |
321 | |
322 | return ret; | |
323 | } | |
324 | ||
d8764646 MP |
325 | static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) |
326 | { | |
327 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
328 | ||
329 | /* | |
330 | * Setup the clock control register | |
331 | */ | |
332 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
333 | &ssi->stccr); | |
334 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
335 | &ssi->srccr); | |
336 | ||
337 | /* | |
338 | * Enable AC97 mode and startup the SSI | |
339 | */ | |
340 | write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, | |
341 | &ssi->sacnt); | |
342 | write_ssi(0xff, &ssi->saccdis); | |
343 | write_ssi(0x300, &ssi->saccen); | |
344 | ||
345 | /* | |
346 | * Enable SSI, Transmit and Receive. AC97 has to communicate with the | |
347 | * codec before a stream is started. | |
348 | */ | |
349 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | | |
350 | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); | |
351 | ||
352 | write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); | |
353 | } | |
354 | ||
cd7f0295 MP |
355 | static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private) |
356 | { | |
357 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
cd7f0295 MP |
358 | u8 wm; |
359 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates; | |
360 | ||
361 | if (ssi_private->imx_ac97) | |
2924a998 | 362 | ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET; |
cd7f0295 | 363 | else |
2924a998 | 364 | ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE; |
cd7f0295 MP |
365 | |
366 | /* | |
367 | * Section 16.5 of the MPC8610 reference manual says that the SSI needs | |
368 | * to be disabled before updating the registers we set here. | |
369 | */ | |
370 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); | |
371 | ||
372 | /* | |
373 | * Program the SSI into I2S Slave Non-Network Synchronous mode. Also | |
374 | * enable the transmit and receive FIFO. | |
375 | * | |
376 | * FIXME: Little-endian samples require a different shift dir | |
377 | */ | |
378 | write_ssi_mask(&ssi->scr, | |
379 | CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN, | |
380 | CCSR_SSI_SCR_TFR_CLK_DIS | | |
2924a998 | 381 | ssi_private->i2s_mode | |
cd7f0295 MP |
382 | (synchronous ? CCSR_SSI_SCR_SYN : 0)); |
383 | ||
384 | write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 | | |
385 | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS | | |
386 | CCSR_SSI_STCR_TSCKP, &ssi->stcr); | |
387 | ||
388 | write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 | | |
389 | CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS | | |
390 | CCSR_SSI_SRCR_RSCKP, &ssi->srcr); | |
391 | /* | |
392 | * The DC and PM bits are only used if the SSI is the clock master. | |
393 | */ | |
394 | ||
395 | /* | |
396 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't | |
397 | * use FIFO 1. We program the transmit water to signal a DMA transfer | |
398 | * if there are only two (or fewer) elements left in the FIFO. Two | |
399 | * elements equals one frame (left channel, right channel). This value, | |
400 | * however, depends on the depth of the transmit buffer. | |
401 | * | |
402 | * We set the watermark on the same level as the DMA burstsize. For | |
403 | * fiq it is probably better to use the biggest possible watermark | |
404 | * size. | |
405 | */ | |
406 | if (ssi_private->use_dma) | |
407 | wm = ssi_private->fifo_depth - 2; | |
408 | else | |
409 | wm = ssi_private->fifo_depth; | |
410 | ||
411 | write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | | |
412 | CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm), | |
413 | &ssi->sfcsr); | |
414 | ||
cd7f0295 MP |
415 | /* |
416 | * For ac97 interrupts are enabled with the startup of the substream | |
417 | * because it is also running without an active substream. Normally SSI | |
418 | * is only enabled when there is a substream. | |
419 | */ | |
d8764646 MP |
420 | if (ssi_private->imx_ac97) |
421 | fsl_ssi_setup_ac97(ssi_private); | |
cd7f0295 MP |
422 | |
423 | return 0; | |
424 | } | |
425 | ||
426 | ||
17467f23 TT |
427 | /** |
428 | * fsl_ssi_startup: create a new substream | |
429 | * | |
430 | * This is the first function called when a stream is opened. | |
431 | * | |
432 | * If this is the first stream open, then grab the IRQ and program most of | |
433 | * the SSI registers. | |
434 | */ | |
dee89c4d MB |
435 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
436 | struct snd_soc_dai *dai) | |
17467f23 TT |
437 | { |
438 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5e538eca TT |
439 | struct fsl_ssi_private *ssi_private = |
440 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
aafa85e7 | 441 | unsigned long flags; |
17467f23 | 442 | |
07a9483a NC |
443 | /* First, we only do fsl_ssi_setup() when SSI is going to be active. |
444 | * Second, fsl_ssi_setup was already called by ac97_init earlier if | |
445 | * the driver is in ac97 mode. | |
17467f23 | 446 | */ |
aafa85e7 | 447 | if (!dai->active && !ssi_private->imx_ac97) { |
07a9483a | 448 | fsl_ssi_setup(ssi_private); |
aafa85e7 NC |
449 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); |
450 | ssi_private->baudclk_locked = false; | |
451 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
452 | } | |
be41e941 | 453 | |
17467f23 TT |
454 | return 0; |
455 | } | |
456 | ||
457 | /** | |
85ef2375 | 458 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
459 | * |
460 | * Most of the SSI registers have been programmed in the startup function, | |
461 | * but the word length must be programmed here. Unfortunately, programming | |
462 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
463 | * cause a problem with supporting simultaneous playback and capture. If | |
464 | * the SSI is already playing a stream, then that stream may be temporarily | |
465 | * stopped when you start capture. | |
466 | * | |
467 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
468 | * clock master. | |
469 | */ | |
85ef2375 TT |
470 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
471 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 472 | { |
f0fba2ad | 473 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
5e538eca | 474 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
2924a998 | 475 | unsigned int channels = params_channels(hw_params); |
5e538eca TT |
476 | unsigned int sample_size = |
477 | snd_pcm_format_width(params_format(hw_params)); | |
478 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); | |
dfa1a107 | 479 | int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; |
17467f23 | 480 | |
5e538eca TT |
481 | /* |
482 | * If we're in synchronous mode, and the SSI is already enabled, | |
483 | * then STCCR is already set properly. | |
484 | */ | |
485 | if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) | |
486 | return 0; | |
17467f23 | 487 | |
5e538eca TT |
488 | /* |
489 | * FIXME: The documentation says that SxCCR[WL] should not be | |
490 | * modified while the SSI is enabled. The only time this can | |
491 | * happen is if we're trying to do simultaneous playback and | |
492 | * capture in asynchronous mode. Unfortunately, I have been enable | |
493 | * to get that to work at all on the P1022DS. Therefore, we don't | |
494 | * bother to disable/enable the SSI when setting SxCCR[WL], because | |
495 | * the SSI will stop anyway. Maybe one day, this will get fixed. | |
496 | */ | |
17467f23 | 497 | |
5e538eca TT |
498 | /* In synchronous mode, the SSI uses STCCR for capture */ |
499 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || | |
500 | ssi_private->cpu_dai_drv.symmetric_rates) | |
dfa1a107 | 501 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
5e538eca | 502 | else |
dfa1a107 | 503 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
17467f23 | 504 | |
2924a998 NC |
505 | if (!ssi_private->imx_ac97) |
506 | write_ssi_mask(&ssi->scr, | |
507 | CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, | |
508 | channels == 1 ? 0 : ssi_private->i2s_mode); | |
509 | ||
17467f23 TT |
510 | return 0; |
511 | } | |
512 | ||
aafa85e7 NC |
513 | /** |
514 | * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. | |
515 | */ | |
516 | static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
517 | { | |
518 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
519 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
520 | u32 strcr = 0, stcr, srcr, scr, mask; | |
521 | ||
522 | scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); | |
523 | scr |= CCSR_SSI_SCR_NET; | |
524 | ||
525 | mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | | |
526 | CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | | |
527 | CCSR_SSI_STCR_TEFS; | |
528 | stcr = read_ssi(&ssi->stcr) & ~mask; | |
529 | srcr = read_ssi(&ssi->srcr) & ~mask; | |
530 | ||
531 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
532 | case SND_SOC_DAIFMT_I2S: | |
533 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
534 | case SND_SOC_DAIFMT_CBS_CFS: | |
535 | ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_MASTER; | |
536 | break; | |
537 | case SND_SOC_DAIFMT_CBM_CFM: | |
538 | ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE; | |
539 | break; | |
540 | default: | |
541 | return -EINVAL; | |
542 | } | |
543 | scr |= ssi_private->i2s_mode; | |
544 | ||
545 | /* Data on rising edge of bclk, frame low, 1clk before data */ | |
546 | strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | | |
547 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
548 | break; | |
549 | case SND_SOC_DAIFMT_LEFT_J: | |
550 | /* Data on rising edge of bclk, frame high */ | |
551 | strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; | |
552 | break; | |
553 | case SND_SOC_DAIFMT_DSP_A: | |
554 | /* Data on rising edge of bclk, frame high, 1clk before data */ | |
555 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
556 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
557 | break; | |
558 | case SND_SOC_DAIFMT_DSP_B: | |
559 | /* Data on rising edge of bclk, frame high */ | |
560 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
561 | CCSR_SSI_STCR_TXBIT0; | |
562 | break; | |
563 | default: | |
564 | return -EINVAL; | |
565 | } | |
566 | ||
567 | /* DAI clock inversion */ | |
568 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
569 | case SND_SOC_DAIFMT_NB_NF: | |
570 | /* Nothing to do for both normal cases */ | |
571 | break; | |
572 | case SND_SOC_DAIFMT_IB_NF: | |
573 | /* Invert bit clock */ | |
574 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
575 | break; | |
576 | case SND_SOC_DAIFMT_NB_IF: | |
577 | /* Invert frame clock */ | |
578 | strcr ^= CCSR_SSI_STCR_TFSI; | |
579 | break; | |
580 | case SND_SOC_DAIFMT_IB_IF: | |
581 | /* Invert both clocks */ | |
582 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
583 | strcr ^= CCSR_SSI_STCR_TFSI; | |
584 | break; | |
585 | default: | |
586 | return -EINVAL; | |
587 | } | |
588 | ||
589 | /* DAI clock master masks */ | |
590 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
591 | case SND_SOC_DAIFMT_CBS_CFS: | |
592 | strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; | |
593 | scr |= CCSR_SSI_SCR_SYS_CLK_EN; | |
594 | break; | |
595 | case SND_SOC_DAIFMT_CBM_CFM: | |
596 | scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; | |
597 | break; | |
598 | default: | |
599 | return -EINVAL; | |
600 | } | |
601 | ||
602 | stcr |= strcr; | |
603 | srcr |= strcr; | |
604 | ||
605 | if (ssi_private->cpu_dai_drv.symmetric_rates) { | |
606 | /* Need to clear RXDIR when using SYNC mode */ | |
607 | srcr &= ~CCSR_SSI_SRCR_RXDIR; | |
608 | scr |= CCSR_SSI_SCR_SYN; | |
609 | } | |
610 | ||
611 | write_ssi(stcr, &ssi->stcr); | |
612 | write_ssi(srcr, &ssi->srcr); | |
613 | write_ssi(scr, &ssi->scr); | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | /** | |
619 | * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock | |
620 | * | |
621 | * Note: This function can be only called when using SSI as DAI master | |
622 | * | |
623 | * Quick instruction for parameters: | |
624 | * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels | |
625 | * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. | |
626 | */ | |
627 | static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
628 | int clk_id, unsigned int freq, int dir) | |
629 | { | |
630 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
631 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
632 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; | |
633 | u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; | |
634 | unsigned long flags, clkrate, baudrate, tmprate; | |
635 | u64 sub, savesub = 100000; | |
636 | ||
637 | /* Don't apply it to any non-baudclk circumstance */ | |
638 | if (IS_ERR(ssi_private->baudclk)) | |
639 | return -EINVAL; | |
640 | ||
641 | /* It should be already enough to divide clock by setting pm alone */ | |
642 | psr = 0; | |
643 | div2 = 0; | |
644 | ||
645 | factor = (div2 + 1) * (7 * psr + 1) * 2; | |
646 | ||
647 | for (i = 0; i < 255; i++) { | |
648 | /* The bclk rate must be smaller than 1/5 sysclk rate */ | |
649 | if (factor * (i + 1) < 5) | |
650 | continue; | |
651 | ||
652 | tmprate = freq * factor * (i + 2); | |
653 | clkrate = clk_round_rate(ssi_private->baudclk, tmprate); | |
654 | ||
655 | do_div(clkrate, factor); | |
656 | afreq = (u32)clkrate / (i + 1); | |
657 | ||
658 | if (freq == afreq) | |
659 | sub = 0; | |
660 | else if (freq / afreq == 1) | |
661 | sub = freq - afreq; | |
662 | else if (afreq / freq == 1) | |
663 | sub = afreq - freq; | |
664 | else | |
665 | continue; | |
666 | ||
667 | /* Calculate the fraction */ | |
668 | sub *= 100000; | |
669 | do_div(sub, freq); | |
670 | ||
671 | if (sub < savesub) { | |
672 | baudrate = tmprate; | |
673 | savesub = sub; | |
674 | pm = i; | |
675 | } | |
676 | ||
677 | /* We are lucky */ | |
678 | if (savesub == 0) | |
679 | break; | |
680 | } | |
681 | ||
682 | /* No proper pm found if it is still remaining the initial value */ | |
683 | if (pm == 999) { | |
684 | dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); | |
685 | return -EINVAL; | |
686 | } | |
687 | ||
688 | stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | | |
689 | (psr ? CCSR_SSI_SxCCR_PSR : 0); | |
690 | mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR; | |
691 | ||
692 | if (dir == SND_SOC_CLOCK_OUT || synchronous) | |
693 | write_ssi_mask(&ssi->stccr, mask, stccr); | |
694 | else | |
695 | write_ssi_mask(&ssi->srccr, mask, stccr); | |
696 | ||
697 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); | |
698 | if (!ssi_private->baudclk_locked) { | |
699 | ret = clk_set_rate(ssi_private->baudclk, baudrate); | |
700 | if (ret) { | |
701 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
702 | dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); | |
703 | return -EINVAL; | |
704 | } | |
705 | ssi_private->baudclk_locked = true; | |
706 | } | |
707 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
712 | /** | |
713 | * fsl_ssi_set_dai_tdm_slot - set TDM slot number | |
714 | * | |
715 | * Note: This function can be only called when using SSI as DAI master | |
716 | */ | |
717 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, | |
718 | u32 rx_mask, int slots, int slot_width) | |
719 | { | |
720 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
721 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
722 | u32 val; | |
723 | ||
724 | /* The slot number should be >= 2 if using Network mode or I2S mode */ | |
725 | val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET); | |
726 | if (val && slots < 2) { | |
727 | dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); | |
728 | return -EINVAL; | |
729 | } | |
730 | ||
731 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, | |
732 | CCSR_SSI_SxCCR_DC(slots)); | |
733 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, | |
734 | CCSR_SSI_SxCCR_DC(slots)); | |
735 | ||
736 | /* The register SxMSKs needs SSI to provide essential clock due to | |
737 | * hardware design. So we here temporarily enable SSI to set them. | |
738 | */ | |
739 | val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; | |
740 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); | |
741 | ||
742 | write_ssi(tx_mask, &ssi->stmsk); | |
743 | write_ssi(rx_mask, &ssi->srmsk); | |
744 | ||
745 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val); | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
17467f23 TT |
750 | /** |
751 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
752 | * | |
753 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
754 | * transfer of data. | |
755 | * | |
756 | * The DMA channel is in external master start and pause mode, which | |
757 | * means the SSI completely controls the flow of data. | |
758 | */ | |
dee89c4d MB |
759 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
760 | struct snd_soc_dai *dai) | |
17467f23 TT |
761 | { |
762 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 763 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 | 764 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
9b443e3d | 765 | unsigned int sier_bits; |
aafa85e7 | 766 | unsigned long flags; |
9b443e3d MG |
767 | |
768 | /* | |
769 | * Enable only the interrupts and DMA requests | |
770 | * that are needed for the channel. As the fiq | |
771 | * is polling for this bits, we have to ensure | |
772 | * that this are aligned with the preallocated | |
773 | * buffers | |
774 | */ | |
775 | ||
776 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
777 | if (ssi_private->use_dma) | |
778 | sier_bits = SIER_FLAGS; | |
779 | else | |
780 | sier_bits = CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN; | |
781 | } else { | |
782 | if (ssi_private->use_dma) | |
783 | sier_bits = SIER_FLAGS; | |
784 | else | |
785 | sier_bits = CCSR_SSI_SIER_RIE | CCSR_SSI_SIER_RFF0_EN; | |
786 | } | |
17467f23 TT |
787 | |
788 | switch (cmd) { | |
789 | case SNDRV_PCM_TRIGGER_START: | |
17467f23 | 790 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 791 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
dfa1a107 | 792 | write_ssi_mask(&ssi->scr, 0, |
be41e941 | 793 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE); |
a4d11fe5 | 794 | else |
dfa1a107 | 795 | write_ssi_mask(&ssi->scr, 0, |
be41e941 | 796 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE); |
17467f23 TT |
797 | break; |
798 | ||
799 | case SNDRV_PCM_TRIGGER_STOP: | |
17467f23 TT |
800 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
801 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
dfa1a107 | 802 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0); |
17467f23 | 803 | else |
dfa1a107 | 804 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0); |
b2c119b0 | 805 | |
cd7f0295 | 806 | if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) & |
aafa85e7 | 807 | (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) { |
b2c119b0 | 808 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); |
aafa85e7 NC |
809 | spin_lock_irqsave(&ssi_private->baudclk_lock, flags); |
810 | ssi_private->baudclk_locked = false; | |
811 | spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); | |
812 | } | |
17467f23 TT |
813 | break; |
814 | ||
815 | default: | |
816 | return -EINVAL; | |
817 | } | |
818 | ||
9b443e3d MG |
819 | write_ssi(sier_bits, &ssi->sier); |
820 | ||
17467f23 TT |
821 | return 0; |
822 | } | |
823 | ||
fc8ba7f9 LPC |
824 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
825 | { | |
826 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); | |
827 | ||
de623ece | 828 | if (ssi_private->ssi_on_imx && ssi_private->use_dma) { |
fc8ba7f9 LPC |
829 | dai->playback_dma_data = &ssi_private->dma_params_tx; |
830 | dai->capture_dma_data = &ssi_private->dma_params_rx; | |
831 | } | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
85e7652d | 836 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
6335d055 EM |
837 | .startup = fsl_ssi_startup, |
838 | .hw_params = fsl_ssi_hw_params, | |
aafa85e7 NC |
839 | .set_fmt = fsl_ssi_set_dai_fmt, |
840 | .set_sysclk = fsl_ssi_set_dai_sysclk, | |
841 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, | |
6335d055 | 842 | .trigger = fsl_ssi_trigger, |
6335d055 EM |
843 | }; |
844 | ||
f0fba2ad LG |
845 | /* Template for the CPU dai driver structure */ |
846 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
fc8ba7f9 | 847 | .probe = fsl_ssi_dai_probe, |
17467f23 | 848 | .playback = { |
2924a998 | 849 | .channels_min = 1, |
17467f23 TT |
850 | .channels_max = 2, |
851 | .rates = FSLSSI_I2S_RATES, | |
852 | .formats = FSLSSI_I2S_FORMATS, | |
853 | }, | |
854 | .capture = { | |
2924a998 | 855 | .channels_min = 1, |
17467f23 TT |
856 | .channels_max = 2, |
857 | .rates = FSLSSI_I2S_RATES, | |
858 | .formats = FSLSSI_I2S_FORMATS, | |
859 | }, | |
6335d055 | 860 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
861 | }; |
862 | ||
3580aa10 KM |
863 | static const struct snd_soc_component_driver fsl_ssi_component = { |
864 | .name = "fsl-ssi", | |
865 | }; | |
866 | ||
cd7f0295 MP |
867 | /** |
868 | * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit. | |
869 | * | |
870 | * This function is called by ALSA to start, stop, pause, and resume the | |
871 | * transfer of data. | |
872 | */ | |
873 | static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd, | |
874 | struct snd_soc_dai *dai) | |
875 | { | |
876 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
877 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata( | |
878 | rtd->cpu_dai); | |
879 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
880 | ||
881 | switch (cmd) { | |
882 | case SNDRV_PCM_TRIGGER_START: | |
883 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
884 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
885 | write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE | | |
886 | CCSR_SSI_SIER_TFE0_EN); | |
887 | else | |
888 | write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE | | |
889 | CCSR_SSI_SIER_RFF0_EN); | |
890 | break; | |
891 | ||
892 | case SNDRV_PCM_TRIGGER_STOP: | |
893 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
894 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
895 | write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE | | |
896 | CCSR_SSI_SIER_TFE0_EN, 0); | |
897 | else | |
898 | write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE | | |
899 | CCSR_SSI_SIER_RFF0_EN, 0); | |
900 | break; | |
901 | ||
902 | default: | |
903 | return -EINVAL; | |
904 | } | |
905 | ||
906 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
907 | write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor); | |
908 | else | |
909 | write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor); | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
914 | static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = { | |
915 | .startup = fsl_ssi_startup, | |
cd7f0295 MP |
916 | .trigger = fsl_ssi_ac97_trigger, |
917 | }; | |
918 | ||
919 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { | |
920 | .ac97_control = 1, | |
921 | .playback = { | |
922 | .stream_name = "AC97 Playback", | |
923 | .channels_min = 2, | |
924 | .channels_max = 2, | |
925 | .rates = SNDRV_PCM_RATE_8000_48000, | |
926 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
927 | }, | |
928 | .capture = { | |
929 | .stream_name = "AC97 Capture", | |
930 | .channels_min = 2, | |
931 | .channels_max = 2, | |
932 | .rates = SNDRV_PCM_RATE_48000, | |
933 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
934 | }, | |
935 | .ops = &fsl_ssi_ac97_dai_ops, | |
936 | }; | |
937 | ||
938 | ||
939 | static struct fsl_ssi_private *fsl_ac97_data; | |
940 | ||
941 | static void fsl_ssi_ac97_init(void) | |
942 | { | |
943 | fsl_ssi_setup(fsl_ac97_data); | |
944 | } | |
945 | ||
a851a2bb | 946 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
cd7f0295 MP |
947 | unsigned short val) |
948 | { | |
949 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
950 | unsigned int lreg; | |
951 | unsigned int lval; | |
952 | ||
953 | if (reg > 0x7f) | |
954 | return; | |
955 | ||
956 | ||
957 | lreg = reg << 12; | |
958 | write_ssi(lreg, &ssi->sacadd); | |
959 | ||
960 | lval = val << 4; | |
961 | write_ssi(lval , &ssi->sacdat); | |
962 | ||
963 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
964 | CCSR_SSI_SACNT_WR); | |
965 | udelay(100); | |
966 | } | |
967 | ||
a851a2bb | 968 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
cd7f0295 MP |
969 | unsigned short reg) |
970 | { | |
971 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
972 | ||
973 | unsigned short val = -1; | |
974 | unsigned int lreg; | |
975 | ||
976 | lreg = (reg & 0x7f) << 12; | |
977 | write_ssi(lreg, &ssi->sacadd); | |
978 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
979 | CCSR_SSI_SACNT_RD); | |
980 | ||
981 | udelay(100); | |
982 | ||
983 | val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff; | |
984 | ||
985 | return val; | |
986 | } | |
987 | ||
988 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { | |
989 | .read = fsl_ssi_ac97_read, | |
990 | .write = fsl_ssi_ac97_write, | |
991 | }; | |
992 | ||
d5a908b2 TT |
993 | /* Show the statistics of a flag only if its interrupt is enabled. The |
994 | * compiler will optimze this code to a no-op if the interrupt is not | |
995 | * enabled. | |
996 | */ | |
997 | #define SIER_SHOW(flag, name) \ | |
998 | do { \ | |
999 | if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \ | |
1000 | length += sprintf(buf + length, #name "=%u\n", \ | |
1001 | ssi_private->stats.name); \ | |
1002 | } while (0) | |
1003 | ||
1004 | ||
17467f23 TT |
1005 | /** |
1006 | * fsl_sysfs_ssi_show: display SSI statistics | |
1007 | * | |
d5a908b2 TT |
1008 | * Display the statistics for the current SSI device. To avoid confusion, |
1009 | * we only show those counts that are enabled. | |
17467f23 TT |
1010 | */ |
1011 | static ssize_t fsl_sysfs_ssi_show(struct device *dev, | |
1012 | struct device_attribute *attr, char *buf) | |
1013 | { | |
1014 | struct fsl_ssi_private *ssi_private = | |
d5a908b2 TT |
1015 | container_of(attr, struct fsl_ssi_private, dev_attr); |
1016 | ssize_t length = 0; | |
1017 | ||
1018 | SIER_SHOW(RFRC_EN, rfrc); | |
1019 | SIER_SHOW(TFRC_EN, tfrc); | |
1020 | SIER_SHOW(CMDAU_EN, cmdau); | |
1021 | SIER_SHOW(CMDDU_EN, cmddu); | |
1022 | SIER_SHOW(RXT_EN, rxt); | |
1023 | SIER_SHOW(RDR1_EN, rdr1); | |
1024 | SIER_SHOW(RDR0_EN, rdr0); | |
1025 | SIER_SHOW(TDE1_EN, tde1); | |
1026 | SIER_SHOW(TDE0_EN, tde0); | |
1027 | SIER_SHOW(ROE1_EN, roe1); | |
1028 | SIER_SHOW(ROE0_EN, roe0); | |
1029 | SIER_SHOW(TUE1_EN, tue1); | |
1030 | SIER_SHOW(TUE0_EN, tue0); | |
1031 | SIER_SHOW(TFS_EN, tfs); | |
1032 | SIER_SHOW(RFS_EN, rfs); | |
1033 | SIER_SHOW(TLS_EN, tls); | |
1034 | SIER_SHOW(RLS_EN, rls); | |
1035 | SIER_SHOW(RFF1_EN, rff1); | |
1036 | SIER_SHOW(RFF0_EN, rff0); | |
1037 | SIER_SHOW(TFE1_EN, tfe1); | |
1038 | SIER_SHOW(TFE0_EN, tfe0); | |
17467f23 TT |
1039 | |
1040 | return length; | |
1041 | } | |
1042 | ||
1043 | /** | |
f0fba2ad | 1044 | * Make every character in a string lower-case |
17467f23 | 1045 | */ |
f0fba2ad LG |
1046 | static void make_lowercase(char *s) |
1047 | { | |
1048 | char *p = s; | |
1049 | char c; | |
1050 | ||
1051 | while ((c = *p)) { | |
1052 | if ((c >= 'A') && (c <= 'Z')) | |
1053 | *p = c + ('a' - 'A'); | |
1054 | p++; | |
1055 | } | |
1056 | } | |
1057 | ||
a0a3d518 | 1058 | static int fsl_ssi_probe(struct platform_device *pdev) |
17467f23 | 1059 | { |
17467f23 TT |
1060 | struct fsl_ssi_private *ssi_private; |
1061 | int ret = 0; | |
87a0632b | 1062 | struct device_attribute *dev_attr = NULL; |
38fec727 | 1063 | struct device_node *np = pdev->dev.of_node; |
f0fba2ad | 1064 | const char *p, *sprop; |
8e9d8690 | 1065 | const uint32_t *iprop; |
f0fba2ad LG |
1066 | struct resource res; |
1067 | char name[64]; | |
312bb4f6 | 1068 | bool shared; |
cd7f0295 | 1069 | bool ac97 = false; |
17467f23 | 1070 | |
ff71334a TT |
1071 | /* SSIs that are not connected on the board should have a |
1072 | * status = "disabled" | |
1073 | * property in their device tree nodes. | |
f0fba2ad | 1074 | */ |
ff71334a | 1075 | if (!of_device_is_available(np)) |
f0fba2ad LG |
1076 | return -ENODEV; |
1077 | ||
1078 | /* We only support the SSI in "I2S Slave" mode */ | |
1079 | sprop = of_get_property(np, "fsl,mode", NULL); | |
cd7f0295 MP |
1080 | if (!sprop) { |
1081 | dev_err(&pdev->dev, "fsl,mode property is necessary\n"); | |
1082 | return -EINVAL; | |
1083 | } | |
1084 | if (!strcmp(sprop, "ac97-slave")) { | |
1085 | ac97 = true; | |
1086 | } else if (strcmp(sprop, "i2s-slave")) { | |
38fec727 | 1087 | dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop); |
f0fba2ad LG |
1088 | return -ENODEV; |
1089 | } | |
1090 | ||
1091 | /* The DAI name is the last part of the full name of the node. */ | |
1092 | p = strrchr(np->full_name, '/') + 1; | |
b0a4747a | 1093 | ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p), |
f0fba2ad | 1094 | GFP_KERNEL); |
17467f23 | 1095 | if (!ssi_private) { |
38fec727 | 1096 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
f0fba2ad | 1097 | return -ENOMEM; |
17467f23 | 1098 | } |
17467f23 | 1099 | |
f0fba2ad | 1100 | strcpy(ssi_private->name, p); |
17467f23 | 1101 | |
de623ece MP |
1102 | ssi_private->use_dma = !of_property_read_bool(np, |
1103 | "fsl,fiq-stream-filter"); | |
1104 | ||
cd7f0295 MP |
1105 | if (ac97) { |
1106 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, | |
1107 | sizeof(fsl_ssi_ac97_dai)); | |
1108 | ||
1109 | fsl_ac97_data = ssi_private; | |
1110 | ssi_private->imx_ac97 = true; | |
1111 | ||
1112 | snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); | |
1113 | } else { | |
1114 | /* Initialize this copy of the CPU DAI driver structure */ | |
1115 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
1116 | sizeof(fsl_ssi_dai_template)); | |
1117 | } | |
f0fba2ad LG |
1118 | ssi_private->cpu_dai_drv.name = ssi_private->name; |
1119 | ||
1120 | /* Get the addresses and IRQ */ | |
1121 | ret = of_address_to_resource(np, 0, &res); | |
1122 | if (ret) { | |
38fec727 | 1123 | dev_err(&pdev->dev, "could not determine device resources\n"); |
b0a4747a | 1124 | return ret; |
f0fba2ad | 1125 | } |
147dfe90 TT |
1126 | ssi_private->ssi = of_iomap(np, 0); |
1127 | if (!ssi_private->ssi) { | |
1128 | dev_err(&pdev->dev, "could not map device resources\n"); | |
b0a4747a | 1129 | return -ENOMEM; |
147dfe90 | 1130 | } |
f0fba2ad | 1131 | ssi_private->ssi_phys = res.start; |
1fab6caf | 1132 | |
f0fba2ad | 1133 | ssi_private->irq = irq_of_parse_and_map(np, 0); |
d60336e2 | 1134 | if (!ssi_private->irq) { |
1fab6caf | 1135 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); |
b0a4747a | 1136 | return -ENXIO; |
1fab6caf TT |
1137 | } |
1138 | ||
f0fba2ad | 1139 | /* Are the RX and the TX clocks locked? */ |
07a9483a | 1140 | if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { |
f0fba2ad | 1141 | ssi_private->cpu_dai_drv.symmetric_rates = 1; |
07a9483a NC |
1142 | ssi_private->cpu_dai_drv.symmetric_channels = 1; |
1143 | ssi_private->cpu_dai_drv.symmetric_samplebits = 1; | |
1144 | } | |
17467f23 | 1145 | |
8e9d8690 TT |
1146 | /* Determine the FIFO depth. */ |
1147 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
1148 | if (iprop) | |
147dfe90 | 1149 | ssi_private->fifo_depth = be32_to_cpup(iprop); |
8e9d8690 TT |
1150 | else |
1151 | /* Older 8610 DTs didn't have the fifo-depth property */ | |
1152 | ssi_private->fifo_depth = 8; | |
1153 | ||
aafa85e7 NC |
1154 | ssi_private->baudclk_locked = false; |
1155 | spin_lock_init(&ssi_private->baudclk_lock); | |
1156 | ||
09ce1111 SG |
1157 | if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) { |
1158 | u32 dma_events[2]; | |
1159 | ssi_private->ssi_on_imx = true; | |
95cd98f9 | 1160 | |
b0a4747a | 1161 | ssi_private->clk = devm_clk_get(&pdev->dev, NULL); |
95cd98f9 SG |
1162 | if (IS_ERR(ssi_private->clk)) { |
1163 | ret = PTR_ERR(ssi_private->clk); | |
1164 | dev_err(&pdev->dev, "could not get clock: %d\n", ret); | |
b0a4747a | 1165 | goto error_irqmap; |
95cd98f9 | 1166 | } |
ede32d3a FE |
1167 | ret = clk_prepare_enable(ssi_private->clk); |
1168 | if (ret) { | |
1169 | dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", | |
1170 | ret); | |
1171 | goto error_irqmap; | |
1172 | } | |
95cd98f9 | 1173 | |
aafa85e7 NC |
1174 | /* For those SLAVE implementations, we ingore non-baudclk cases |
1175 | * and, instead, abandon MASTER mode that needs baud clock. | |
1176 | */ | |
1177 | ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); | |
1178 | if (IS_ERR(ssi_private->baudclk)) | |
1179 | dev_warn(&pdev->dev, "could not get baud clock: %d\n", ret); | |
1180 | else | |
1181 | clk_prepare_enable(ssi_private->baudclk); | |
1182 | ||
09ce1111 SG |
1183 | /* |
1184 | * We have burstsize be "fifo_depth - 2" to match the SSI | |
1185 | * watermark setting in fsl_ssi_startup(). | |
1186 | */ | |
a8909c9b | 1187 | ssi_private->dma_params_tx.maxburst = |
09ce1111 | 1188 | ssi_private->fifo_depth - 2; |
a8909c9b | 1189 | ssi_private->dma_params_rx.maxburst = |
09ce1111 | 1190 | ssi_private->fifo_depth - 2; |
a8909c9b | 1191 | ssi_private->dma_params_tx.addr = |
09ce1111 | 1192 | ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0); |
a8909c9b | 1193 | ssi_private->dma_params_rx.addr = |
09ce1111 | 1194 | ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0); |
a8909c9b LPC |
1195 | ssi_private->dma_params_tx.filter_data = |
1196 | &ssi_private->filter_data_tx; | |
1197 | ssi_private->dma_params_rx.filter_data = | |
1198 | &ssi_private->filter_data_rx; | |
3a5e517b MP |
1199 | if (!of_property_read_bool(pdev->dev.of_node, "dmas") && |
1200 | ssi_private->use_dma) { | |
1201 | /* | |
1202 | * FIXME: This is a temporary solution until all | |
1203 | * necessary dma drivers support the generic dma | |
1204 | * bindings. | |
1205 | */ | |
1206 | ret = of_property_read_u32_array(pdev->dev.of_node, | |
09ce1111 | 1207 | "fsl,ssi-dma-events", dma_events, 2); |
3a5e517b MP |
1208 | if (ret && ssi_private->use_dma) { |
1209 | dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n"); | |
1210 | goto error_clk; | |
1211 | } | |
09ce1111 | 1212 | } |
312bb4f6 LPC |
1213 | |
1214 | shared = of_device_is_compatible(of_get_parent(np), | |
1215 | "fsl,spba-bus"); | |
1216 | ||
a8909c9b | 1217 | imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx, |
32bd8cd2 | 1218 | dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI); |
a8909c9b | 1219 | imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx, |
32bd8cd2 | 1220 | dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI); |
f0377086 MG |
1221 | } else if (ssi_private->use_dma) { |
1222 | /* The 'name' should not have any slashes in it. */ | |
1223 | ret = devm_request_irq(&pdev->dev, ssi_private->irq, | |
1224 | fsl_ssi_isr, 0, ssi_private->name, | |
1225 | ssi_private); | |
1226 | if (ret < 0) { | |
1227 | dev_err(&pdev->dev, "could not claim irq %u\n", | |
1228 | ssi_private->irq); | |
1229 | goto error_irqmap; | |
1230 | } | |
09ce1111 SG |
1231 | } |
1232 | ||
17467f23 | 1233 | /* Initialize the the device_attribute structure */ |
f0fba2ad | 1234 | dev_attr = &ssi_private->dev_attr; |
0f768a72 | 1235 | sysfs_attr_init(&dev_attr->attr); |
f0fba2ad | 1236 | dev_attr->attr.name = "statistics"; |
17467f23 TT |
1237 | dev_attr->attr.mode = S_IRUGO; |
1238 | dev_attr->show = fsl_sysfs_ssi_show; | |
1239 | ||
38fec727 | 1240 | ret = device_create_file(&pdev->dev, dev_attr); |
17467f23 | 1241 | if (ret) { |
38fec727 | 1242 | dev_err(&pdev->dev, "could not create sysfs %s file\n", |
17467f23 | 1243 | ssi_private->dev_attr.attr.name); |
b0a4747a | 1244 | goto error_clk; |
17467f23 TT |
1245 | } |
1246 | ||
f0fba2ad | 1247 | /* Register with ASoC */ |
38fec727 | 1248 | dev_set_drvdata(&pdev->dev, ssi_private); |
3f4b783c | 1249 | |
3580aa10 KM |
1250 | ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component, |
1251 | &ssi_private->cpu_dai_drv, 1); | |
87a0632b | 1252 | if (ret) { |
38fec727 | 1253 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); |
1fab6caf | 1254 | goto error_dev; |
f0fba2ad LG |
1255 | } |
1256 | ||
09ce1111 | 1257 | if (ssi_private->ssi_on_imx) { |
de623ece MP |
1258 | if (!ssi_private->use_dma) { |
1259 | ||
1260 | /* | |
1261 | * Some boards use an incompatible codec. To get it | |
1262 | * working, we are using imx-fiq-pcm-audio, that | |
1263 | * can handle those codecs. DMA is not possible in this | |
1264 | * situation. | |
1265 | */ | |
1266 | ||
1267 | ssi_private->fiq_params.irq = ssi_private->irq; | |
1268 | ssi_private->fiq_params.base = ssi_private->ssi; | |
1269 | ssi_private->fiq_params.dma_params_rx = | |
1270 | &ssi_private->dma_params_rx; | |
1271 | ssi_private->fiq_params.dma_params_tx = | |
1272 | &ssi_private->dma_params_tx; | |
1273 | ||
1274 | ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); | |
1275 | if (ret) | |
1276 | goto error_dev; | |
1277 | } else { | |
1278 | ret = imx_pcm_dma_init(pdev); | |
1279 | if (ret) | |
1280 | goto error_dev; | |
1281 | } | |
09ce1111 SG |
1282 | } |
1283 | ||
1284 | /* | |
1285 | * If codec-handle property is missing from SSI node, we assume | |
1286 | * that the machine driver uses new binding which does not require | |
1287 | * SSI driver to trigger machine driver's probe. | |
1288 | */ | |
1289 | if (!of_get_property(np, "codec-handle", NULL)) { | |
1290 | ssi_private->new_binding = true; | |
1291 | goto done; | |
1292 | } | |
1293 | ||
f0fba2ad | 1294 | /* Trigger the machine driver's probe function. The platform driver |
2b81ec69 | 1295 | * name of the machine driver is taken from /compatible property of the |
f0fba2ad LG |
1296 | * device tree. We also pass the address of the CPU DAI driver |
1297 | * structure. | |
1298 | */ | |
2b81ec69 SG |
1299 | sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); |
1300 | /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ | |
f0fba2ad LG |
1301 | p = strrchr(sprop, ','); |
1302 | if (p) | |
1303 | sprop = p + 1; | |
1304 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
1305 | make_lowercase(name); | |
1306 | ||
1307 | ssi_private->pdev = | |
38fec727 | 1308 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
f0fba2ad LG |
1309 | if (IS_ERR(ssi_private->pdev)) { |
1310 | ret = PTR_ERR(ssi_private->pdev); | |
38fec727 | 1311 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
1fab6caf | 1312 | goto error_dai; |
3f4b783c | 1313 | } |
17467f23 | 1314 | |
09ce1111 | 1315 | done: |
cd7f0295 MP |
1316 | if (ssi_private->imx_ac97) |
1317 | fsl_ssi_ac97_init(); | |
1318 | ||
f0fba2ad | 1319 | return 0; |
87a0632b | 1320 | |
1fab6caf | 1321 | error_dai: |
3580aa10 | 1322 | snd_soc_unregister_component(&pdev->dev); |
1fab6caf TT |
1323 | |
1324 | error_dev: | |
1fab6caf TT |
1325 | device_remove_file(&pdev->dev, dev_attr); |
1326 | ||
95cd98f9 | 1327 | error_clk: |
aafa85e7 NC |
1328 | if (ssi_private->ssi_on_imx) { |
1329 | if (!IS_ERR(ssi_private->baudclk)) | |
1330 | clk_disable_unprepare(ssi_private->baudclk); | |
95cd98f9 | 1331 | clk_disable_unprepare(ssi_private->clk); |
aafa85e7 | 1332 | } |
1fab6caf TT |
1333 | |
1334 | error_irqmap: | |
87a0632b | 1335 | irq_dispose_mapping(ssi_private->irq); |
1fab6caf | 1336 | |
87a0632b | 1337 | return ret; |
17467f23 | 1338 | } |
17467f23 | 1339 | |
38fec727 | 1340 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 1341 | { |
38fec727 | 1342 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
17467f23 | 1343 | |
09ce1111 SG |
1344 | if (!ssi_private->new_binding) |
1345 | platform_device_unregister(ssi_private->pdev); | |
3580aa10 | 1346 | snd_soc_unregister_component(&pdev->dev); |
38fec727 | 1347 | device_remove_file(&pdev->dev, &ssi_private->dev_attr); |
aafa85e7 NC |
1348 | if (ssi_private->ssi_on_imx) { |
1349 | if (!IS_ERR(ssi_private->baudclk)) | |
1350 | clk_disable_unprepare(ssi_private->baudclk); | |
0783e648 | 1351 | clk_disable_unprepare(ssi_private->clk); |
aafa85e7 | 1352 | } |
1fab6caf | 1353 | irq_dispose_mapping(ssi_private->irq); |
f0fba2ad LG |
1354 | |
1355 | return 0; | |
17467f23 | 1356 | } |
f0fba2ad LG |
1357 | |
1358 | static const struct of_device_id fsl_ssi_ids[] = { | |
1359 | { .compatible = "fsl,mpc8610-ssi", }, | |
09ce1111 | 1360 | { .compatible = "fsl,imx21-ssi", }, |
f0fba2ad LG |
1361 | {} |
1362 | }; | |
1363 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
1364 | ||
f07eb223 | 1365 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
1366 | .driver = { |
1367 | .name = "fsl-ssi-dai", | |
1368 | .owner = THIS_MODULE, | |
1369 | .of_match_table = fsl_ssi_ids, | |
1370 | }, | |
1371 | .probe = fsl_ssi_probe, | |
1372 | .remove = fsl_ssi_remove, | |
1373 | }; | |
17467f23 | 1374 | |
ba0a7e02 | 1375 | module_platform_driver(fsl_ssi_driver); |
a454dad1 | 1376 | |
f3142807 | 1377 | MODULE_ALIAS("platform:fsl-ssi-dai"); |
17467f23 TT |
1378 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
1379 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 1380 | MODULE_LICENSE("GPL v2"); |