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17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
de623ece MP |
11 | * |
12 | * | |
13 | * Some notes why imx-pcm-fiq is used instead of DMA on some boards: | |
14 | * | |
15 | * The i.MX SSI core has some nasty limitations in AC97 mode. While most | |
16 | * sane processor vendors have a FIFO per AC97 slot, the i.MX has only | |
17 | * one FIFO which combines all valid receive slots. We cannot even select | |
18 | * which slots we want to receive. The WM9712 with which this driver | |
19 | * was developed with always sends GPIO status data in slot 12 which | |
20 | * we receive in our (PCM-) data stream. The only chance we have is to | |
21 | * manually skip this data in the FIQ handler. With sampling rates different | |
22 | * from 48000Hz not every frame has valid receive data, so the ratio | |
23 | * between pcm data and GPIO status data changes. Our FIQ handler is not | |
24 | * able to handle this, hence this driver only works with 48000Hz sampling | |
25 | * rate. | |
26 | * Reading and writing AC97 registers is another challenge. The core | |
27 | * provides us status bits when the read register is updated with *another* | |
28 | * value. When we read the same register two times (and the register still | |
29 | * contains the same value) these status bits are not set. We work | |
30 | * around this by not polling these bits but only wait a fixed delay. | |
17467f23 TT |
31 | */ |
32 | ||
33 | #include <linux/init.h> | |
dfa1a107 | 34 | #include <linux/io.h> |
17467f23 TT |
35 | #include <linux/module.h> |
36 | #include <linux/interrupt.h> | |
95cd98f9 | 37 | #include <linux/clk.h> |
17467f23 TT |
38 | #include <linux/device.h> |
39 | #include <linux/delay.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
aafa85e7 | 41 | #include <linux/spinlock.h> |
dfa1a107 SG |
42 | #include <linux/of_address.h> |
43 | #include <linux/of_irq.h> | |
f0fba2ad | 44 | #include <linux/of_platform.h> |
17467f23 | 45 | |
17467f23 TT |
46 | #include <sound/core.h> |
47 | #include <sound/pcm.h> | |
48 | #include <sound/pcm_params.h> | |
49 | #include <sound/initval.h> | |
50 | #include <sound/soc.h> | |
a8909c9b | 51 | #include <sound/dmaengine_pcm.h> |
17467f23 | 52 | |
17467f23 | 53 | #include "fsl_ssi.h" |
09ce1111 | 54 | #include "imx-pcm.h" |
17467f23 | 55 | |
dfa1a107 SG |
56 | #ifdef PPC |
57 | #define read_ssi(addr) in_be32(addr) | |
58 | #define write_ssi(val, addr) out_be32(addr, val) | |
59 | #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set) | |
0a9eaa39 | 60 | #else |
dfa1a107 SG |
61 | #define read_ssi(addr) readl(addr) |
62 | #define write_ssi(val, addr) writel(val, addr) | |
63 | /* | |
64 | * FIXME: Proper locking should be added at write_ssi_mask caller level | |
65 | * to ensure this register read/modify/write sequence is race free. | |
66 | */ | |
67 | static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set) | |
68 | { | |
69 | u32 val = readl(addr); | |
70 | val = (val & ~clear) | set; | |
71 | writel(val, addr); | |
72 | } | |
73 | #endif | |
74 | ||
17467f23 TT |
75 | /** |
76 | * FSLSSI_I2S_RATES: sample rates supported by the I2S | |
77 | * | |
78 | * This driver currently only supports the SSI running in I2S slave mode, | |
79 | * which means the codec determines the sample rate. Therefore, we tell | |
80 | * ALSA that we support all rates and let the codec driver decide what rates | |
81 | * are really supported. | |
82 | */ | |
24710c97 | 83 | #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS |
17467f23 TT |
84 | |
85 | /** | |
86 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
87 | * | |
88 | * This driver currently only supports the SSI running in I2S slave mode. | |
89 | * | |
90 | * The SSI has a limitation in that the samples must be in the same byte | |
91 | * order as the host CPU. This is because when multiple bytes are written | |
92 | * to the STX register, the bytes and bits must be written in the same | |
93 | * order. The STX is a shift register, so all the bits need to be aligned | |
94 | * (bit-endianness must match byte-endianness). Processors typically write | |
95 | * the bits within a byte in the same order that the bytes of a word are | |
96 | * written in. So if the host CPU is big-endian, then only big-endian | |
97 | * samples will be written to STX properly. | |
98 | */ | |
99 | #ifdef __BIG_ENDIAN | |
100 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
101 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
102 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
103 | #else | |
104 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
105 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
106 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
107 | #endif | |
108 | ||
9368acc4 MP |
109 | #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ |
110 | CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ | |
111 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) | |
112 | #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ | |
113 | CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ | |
114 | CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) | |
c1953bfe MP |
115 | |
116 | enum fsl_ssi_type { | |
117 | FSL_SSI_MCP8610, | |
118 | FSL_SSI_MX21, | |
0888efd1 | 119 | FSL_SSI_MX35, |
c1953bfe MP |
120 | FSL_SSI_MX51, |
121 | }; | |
122 | ||
4e6ec0d9 MP |
123 | struct fsl_ssi_reg_val { |
124 | u32 sier; | |
125 | u32 srcr; | |
126 | u32 stcr; | |
127 | u32 scr; | |
128 | }; | |
129 | ||
130 | struct fsl_ssi_rxtx_reg_val { | |
131 | struct fsl_ssi_reg_val rx; | |
132 | struct fsl_ssi_reg_val tx; | |
133 | }; | |
d5a908b2 | 134 | |
fcdbadef SH |
135 | struct fsl_ssi_soc_data { |
136 | bool imx; | |
137 | bool offline_config; | |
138 | u32 sisr_write_mask; | |
139 | }; | |
140 | ||
17467f23 TT |
141 | /** |
142 | * fsl_ssi_private: per-SSI private data | |
143 | * | |
17467f23 TT |
144 | * @ssi: pointer to the SSI's registers |
145 | * @ssi_phys: physical address of the SSI registers | |
146 | * @irq: IRQ of this SSI | |
17467f23 TT |
147 | * @playback: the number of playback streams opened |
148 | * @capture: the number of capture streams opened | |
149 | * @cpu_dai: the CPU DAI for this device | |
150 | * @dev_attr: the sysfs device attribute structure | |
151 | * @stats: SSI statistics | |
152 | */ | |
153 | struct fsl_ssi_private { | |
17467f23 TT |
154 | struct ccsr_ssi __iomem *ssi; |
155 | dma_addr_t ssi_phys; | |
156 | unsigned int irq; | |
8e9d8690 | 157 | unsigned int fifo_depth; |
f0fba2ad | 158 | struct snd_soc_dai_driver cpu_dai_drv; |
f0fba2ad | 159 | struct platform_device *pdev; |
171d683d | 160 | unsigned int dai_fmt; |
17467f23 | 161 | |
de623ece | 162 | bool use_dma; |
aafa85e7 | 163 | bool baudclk_locked; |
0da9e55e | 164 | bool use_dual_fifo; |
2924a998 | 165 | u8 i2s_mode; |
aafa85e7 | 166 | struct clk *baudclk; |
95cd98f9 | 167 | struct clk *clk; |
8dd51e23 | 168 | unsigned int bitclk_freq; |
a8909c9b LPC |
169 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
170 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
de623ece | 171 | struct imx_pcm_fiq_params fiq_params; |
4e6ec0d9 MP |
172 | /* Register values for rx/tx configuration */ |
173 | struct fsl_ssi_rxtx_reg_val rxtx_reg_val; | |
09ce1111 | 174 | |
f138e621 | 175 | struct fsl_ssi_dbg dbg_stats; |
17467f23 | 176 | |
fcdbadef | 177 | const struct fsl_ssi_soc_data *soc; |
c1953bfe | 178 | }; |
171d683d MP |
179 | |
180 | /* | |
181 | * imx51 and later SoCs have a slightly different IP that allows the | |
182 | * SSI configuration while the SSI unit is running. | |
183 | * | |
184 | * More important, it is necessary on those SoCs to configure the | |
185 | * sperate TX/RX DMA bits just before starting the stream | |
186 | * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi | |
187 | * sends any DMA requests to the SDMA unit, otherwise it is not defined | |
188 | * how the SDMA unit handles the DMA request. | |
189 | * | |
190 | * SDMA units are present on devices starting at imx35 but the imx35 | |
191 | * reference manual states that the DMA bits should not be changed | |
192 | * while the SSI unit is running (SSIEN). So we support the necessary | |
193 | * online configuration of fsl-ssi starting at imx51. | |
194 | */ | |
171d683d | 195 | |
fcdbadef SH |
196 | static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { |
197 | .imx = false, | |
198 | .offline_config = true, | |
199 | .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | | |
200 | CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
201 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, | |
202 | }; | |
203 | ||
204 | static struct fsl_ssi_soc_data fsl_ssi_imx21 = { | |
205 | .imx = true, | |
206 | .offline_config = true, | |
207 | .sisr_write_mask = 0, | |
208 | }; | |
209 | ||
210 | static struct fsl_ssi_soc_data fsl_ssi_imx35 = { | |
211 | .imx = true, | |
212 | .offline_config = true, | |
213 | .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | | |
214 | CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
215 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, | |
216 | }; | |
217 | ||
218 | static struct fsl_ssi_soc_data fsl_ssi_imx51 = { | |
219 | .imx = true, | |
220 | .offline_config = false, | |
221 | .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
222 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, | |
223 | }; | |
224 | ||
225 | static const struct of_device_id fsl_ssi_ids[] = { | |
226 | { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, | |
227 | { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, | |
228 | { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, | |
229 | { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, | |
230 | {} | |
231 | }; | |
232 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
233 | ||
234 | static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private) | |
235 | { | |
236 | return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97); | |
171d683d MP |
237 | } |
238 | ||
8dd51e23 SH |
239 | static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private) |
240 | { | |
241 | return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == | |
242 | SND_SOC_DAIFMT_CBS_CFS; | |
243 | } | |
244 | ||
17467f23 TT |
245 | /** |
246 | * fsl_ssi_isr: SSI interrupt handler | |
247 | * | |
248 | * Although it's possible to use the interrupt handler to send and receive | |
249 | * data to/from the SSI, we use the DMA instead. Programming is more | |
250 | * complicated, but the performance is much better. | |
251 | * | |
252 | * This interrupt handler is used only to gather statistics. | |
253 | * | |
254 | * @irq: IRQ of the SSI device | |
255 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
256 | */ | |
257 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
258 | { | |
259 | struct fsl_ssi_private *ssi_private = dev_id; | |
260 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
17467f23 | 261 | __be32 sisr; |
0888efd1 | 262 | __be32 sisr2; |
17467f23 TT |
263 | |
264 | /* We got an interrupt, so read the status register to see what we | |
265 | were interrupted for. We mask it with the Interrupt Enable register | |
266 | so that we only check for events that we're interested in. | |
267 | */ | |
f138e621 | 268 | sisr = read_ssi(&ssi->sisr); |
17467f23 | 269 | |
fcdbadef | 270 | sisr2 = sisr & ssi_private->soc->sisr_write_mask; |
17467f23 TT |
271 | /* Clear the bits that we set */ |
272 | if (sisr2) | |
dfa1a107 | 273 | write_ssi(sisr2, &ssi->sisr); |
17467f23 | 274 | |
f138e621 | 275 | fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); |
9368acc4 | 276 | |
f138e621 | 277 | return IRQ_HANDLED; |
9368acc4 MP |
278 | } |
279 | ||
4e6ec0d9 MP |
280 | /* |
281 | * Enable/Disable all rx/tx config flags at once. | |
282 | */ | |
283 | static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, | |
284 | bool enable) | |
285 | { | |
286 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
287 | struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; | |
288 | ||
289 | if (enable) { | |
290 | write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier); | |
291 | write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr); | |
292 | write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr); | |
293 | } else { | |
294 | write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0); | |
295 | write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0); | |
296 | write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0); | |
297 | } | |
298 | } | |
299 | ||
65c961cc MP |
300 | /* |
301 | * Calculate the bits that have to be disabled for the current stream that is | |
302 | * getting disabled. This keeps the bits enabled that are necessary for the | |
303 | * second stream to work if 'stream_active' is true. | |
304 | * | |
305 | * Detailed calculation: | |
306 | * These are the values that need to be active after disabling. For non-active | |
307 | * second stream, this is 0: | |
308 | * vals_stream * !!stream_active | |
309 | * | |
310 | * The following computes the overall differences between the setup for the | |
311 | * to-disable stream and the active stream, a simple XOR: | |
312 | * vals_disable ^ (vals_stream * !!(stream_active)) | |
313 | * | |
314 | * The full expression adds a mask on all values we care about | |
315 | */ | |
316 | #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ | |
317 | ((vals_disable) & \ | |
318 | ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) | |
319 | ||
4e6ec0d9 MP |
320 | /* |
321 | * Enable/Disable a ssi configuration. You have to pass either | |
322 | * ssi_private->rxtx_reg_val.rx or tx as vals parameter. | |
323 | */ | |
324 | static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, | |
325 | struct fsl_ssi_reg_val *vals) | |
326 | { | |
327 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
328 | struct fsl_ssi_reg_val *avals; | |
329 | u32 scr_val = read_ssi(&ssi->scr); | |
330 | int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + | |
331 | !!(scr_val & CCSR_SSI_SCR_RE); | |
65c961cc MP |
332 | int keep_active; |
333 | ||
334 | if (nr_active_streams - 1 > 0) | |
335 | keep_active = 1; | |
336 | else | |
337 | keep_active = 0; | |
4e6ec0d9 MP |
338 | |
339 | /* Find the other direction values rx or tx which we do not want to | |
340 | * modify */ | |
341 | if (&ssi_private->rxtx_reg_val.rx == vals) | |
342 | avals = &ssi_private->rxtx_reg_val.tx; | |
343 | else | |
344 | avals = &ssi_private->rxtx_reg_val.rx; | |
345 | ||
346 | /* If vals should be disabled, start with disabling the unit */ | |
347 | if (!enable) { | |
65c961cc MP |
348 | u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, |
349 | keep_active); | |
4e6ec0d9 MP |
350 | write_ssi_mask(&ssi->scr, scr, 0); |
351 | } | |
352 | ||
353 | /* | |
354 | * We are running on a SoC which does not support online SSI | |
355 | * reconfiguration, so we have to enable all necessary flags at once | |
356 | * even if we do not use them later (capture and playback configuration) | |
357 | */ | |
fcdbadef | 358 | if (ssi_private->soc->offline_config) { |
4e6ec0d9 | 359 | if ((enable && !nr_active_streams) || |
65c961cc | 360 | (!enable && !keep_active)) |
4e6ec0d9 MP |
361 | fsl_ssi_rxtx_config(ssi_private, enable); |
362 | ||
363 | goto config_done; | |
364 | } | |
365 | ||
366 | /* | |
367 | * Configure single direction units while the SSI unit is running | |
368 | * (online configuration) | |
369 | */ | |
370 | if (enable) { | |
371 | write_ssi_mask(&ssi->sier, 0, vals->sier); | |
372 | write_ssi_mask(&ssi->srcr, 0, vals->srcr); | |
373 | write_ssi_mask(&ssi->stcr, 0, vals->stcr); | |
374 | } else { | |
375 | u32 sier; | |
376 | u32 srcr; | |
377 | u32 stcr; | |
378 | ||
379 | /* | |
380 | * Disabling the necessary flags for one of rx/tx while the | |
381 | * other stream is active is a little bit more difficult. We | |
382 | * have to disable only those flags that differ between both | |
383 | * streams (rx XOR tx) and that are set in the stream that is | |
384 | * disabled now. Otherwise we could alter flags of the other | |
385 | * stream | |
386 | */ | |
387 | ||
388 | /* These assignments are simply vals without bits set in avals*/ | |
65c961cc MP |
389 | sier = fsl_ssi_disable_val(vals->sier, avals->sier, |
390 | keep_active); | |
391 | srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, | |
392 | keep_active); | |
393 | stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, | |
394 | keep_active); | |
4e6ec0d9 MP |
395 | |
396 | write_ssi_mask(&ssi->srcr, srcr, 0); | |
397 | write_ssi_mask(&ssi->stcr, stcr, 0); | |
398 | write_ssi_mask(&ssi->sier, sier, 0); | |
399 | } | |
400 | ||
401 | config_done: | |
402 | /* Enabling of subunits is done after configuration */ | |
403 | if (enable) | |
404 | write_ssi_mask(&ssi->scr, 0, vals->scr); | |
405 | } | |
406 | ||
407 | ||
408 | static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) | |
409 | { | |
410 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); | |
411 | } | |
412 | ||
413 | static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) | |
414 | { | |
415 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); | |
416 | } | |
417 | ||
6de83879 MP |
418 | /* |
419 | * Setup rx/tx register values used to enable/disable the streams. These will | |
420 | * be used later in fsl_ssi_config to setup the streams without the need to | |
421 | * check for all different SSI modes. | |
422 | */ | |
423 | static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) | |
424 | { | |
425 | struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; | |
426 | ||
427 | reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; | |
428 | reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; | |
429 | reg->rx.scr = 0; | |
430 | reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; | |
431 | reg->tx.stcr = CCSR_SSI_STCR_TFEN0; | |
432 | reg->tx.scr = 0; | |
433 | ||
171d683d | 434 | if (!fsl_ssi_is_ac97(ssi_private)) { |
6de83879 MP |
435 | reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; |
436 | reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; | |
437 | reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; | |
438 | reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; | |
439 | } | |
440 | ||
441 | if (ssi_private->use_dma) { | |
442 | reg->rx.sier |= CCSR_SSI_SIER_RDMAE; | |
443 | reg->tx.sier |= CCSR_SSI_SIER_TDMAE; | |
444 | } else { | |
445 | reg->rx.sier |= CCSR_SSI_SIER_RIE; | |
446 | reg->tx.sier |= CCSR_SSI_SIER_TIE; | |
447 | } | |
448 | ||
449 | reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; | |
450 | reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; | |
451 | } | |
452 | ||
d8764646 MP |
453 | static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) |
454 | { | |
455 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
456 | ||
457 | /* | |
458 | * Setup the clock control register | |
459 | */ | |
460 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
461 | &ssi->stccr); | |
462 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | |
463 | &ssi->srccr); | |
464 | ||
465 | /* | |
466 | * Enable AC97 mode and startup the SSI | |
467 | */ | |
468 | write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, | |
469 | &ssi->sacnt); | |
470 | write_ssi(0xff, &ssi->saccdis); | |
471 | write_ssi(0x300, &ssi->saccen); | |
472 | ||
473 | /* | |
474 | * Enable SSI, Transmit and Receive. AC97 has to communicate with the | |
475 | * codec before a stream is started. | |
476 | */ | |
477 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | | |
478 | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); | |
479 | ||
480 | write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); | |
481 | } | |
482 | ||
17467f23 TT |
483 | /** |
484 | * fsl_ssi_startup: create a new substream | |
485 | * | |
486 | * This is the first function called when a stream is opened. | |
487 | * | |
488 | * If this is the first stream open, then grab the IRQ and program most of | |
489 | * the SSI registers. | |
490 | */ | |
dee89c4d MB |
491 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
492 | struct snd_soc_dai *dai) | |
17467f23 TT |
493 | { |
494 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5e538eca TT |
495 | struct fsl_ssi_private *ssi_private = |
496 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
17467f23 | 497 | |
d8ced479 | 498 | if (!dai->active && !fsl_ssi_is_ac97(ssi_private)) |
aafa85e7 | 499 | ssi_private->baudclk_locked = false; |
be41e941 | 500 | |
0da9e55e NC |
501 | /* When using dual fifo mode, it is safer to ensure an even period |
502 | * size. If appearing to an odd number while DMA always starts its | |
503 | * task from fifo0, fifo1 would be neglected at the end of each | |
504 | * period. But SSI would still access fifo1 with an invalid data. | |
505 | */ | |
506 | if (ssi_private->use_dual_fifo) | |
507 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
508 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); | |
509 | ||
17467f23 TT |
510 | return 0; |
511 | } | |
512 | ||
ee9daad4 | 513 | /** |
8dd51e23 | 514 | * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock |
ee9daad4 SH |
515 | * |
516 | * Note: This function can be only called when using SSI as DAI master | |
517 | * | |
518 | * Quick instruction for parameters: | |
519 | * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels | |
520 | * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. | |
521 | */ | |
8dd51e23 SH |
522 | static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, |
523 | struct snd_soc_dai *cpu_dai, | |
524 | struct snd_pcm_hw_params *hw_params) | |
ee9daad4 SH |
525 | { |
526 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
527 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
528 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; | |
529 | u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; | |
d8ced479 | 530 | unsigned long clkrate, baudrate, tmprate; |
ee9daad4 | 531 | u64 sub, savesub = 100000; |
8dd51e23 SH |
532 | unsigned int freq; |
533 | ||
534 | /* Prefer the explicitly set bitclock frequency */ | |
535 | if (ssi_private->bitclk_freq) | |
536 | freq = ssi_private->bitclk_freq; | |
537 | else | |
538 | freq = params_channels(hw_params) * 32 * params_rate(hw_params); | |
ee9daad4 SH |
539 | |
540 | /* Don't apply it to any non-baudclk circumstance */ | |
541 | if (IS_ERR(ssi_private->baudclk)) | |
542 | return -EINVAL; | |
543 | ||
544 | /* It should be already enough to divide clock by setting pm alone */ | |
545 | psr = 0; | |
546 | div2 = 0; | |
547 | ||
548 | factor = (div2 + 1) * (7 * psr + 1) * 2; | |
549 | ||
550 | for (i = 0; i < 255; i++) { | |
551 | /* The bclk rate must be smaller than 1/5 sysclk rate */ | |
552 | if (factor * (i + 1) < 5) | |
553 | continue; | |
554 | ||
555 | tmprate = freq * factor * (i + 2); | |
556 | clkrate = clk_round_rate(ssi_private->baudclk, tmprate); | |
557 | ||
558 | do_div(clkrate, factor); | |
559 | afreq = (u32)clkrate / (i + 1); | |
560 | ||
561 | if (freq == afreq) | |
562 | sub = 0; | |
563 | else if (freq / afreq == 1) | |
564 | sub = freq - afreq; | |
565 | else if (afreq / freq == 1) | |
566 | sub = afreq - freq; | |
567 | else | |
568 | continue; | |
569 | ||
570 | /* Calculate the fraction */ | |
571 | sub *= 100000; | |
572 | do_div(sub, freq); | |
573 | ||
574 | if (sub < savesub) { | |
575 | baudrate = tmprate; | |
576 | savesub = sub; | |
577 | pm = i; | |
578 | } | |
579 | ||
580 | /* We are lucky */ | |
581 | if (savesub == 0) | |
582 | break; | |
583 | } | |
584 | ||
585 | /* No proper pm found if it is still remaining the initial value */ | |
586 | if (pm == 999) { | |
587 | dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); | |
588 | return -EINVAL; | |
589 | } | |
590 | ||
591 | stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | | |
592 | (psr ? CCSR_SSI_SxCCR_PSR : 0); | |
593 | mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | | |
594 | CCSR_SSI_SxCCR_PSR; | |
595 | ||
8dd51e23 | 596 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) |
ee9daad4 SH |
597 | write_ssi_mask(&ssi->stccr, mask, stccr); |
598 | else | |
599 | write_ssi_mask(&ssi->srccr, mask, stccr); | |
600 | ||
ee9daad4 SH |
601 | if (!ssi_private->baudclk_locked) { |
602 | ret = clk_set_rate(ssi_private->baudclk, baudrate); | |
603 | if (ret) { | |
ee9daad4 SH |
604 | dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); |
605 | return -EINVAL; | |
606 | } | |
607 | ssi_private->baudclk_locked = true; | |
608 | } | |
ee9daad4 SH |
609 | |
610 | return 0; | |
611 | } | |
612 | ||
8dd51e23 SH |
613 | static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
614 | int clk_id, unsigned int freq, int dir) | |
615 | { | |
616 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
617 | ||
618 | ssi_private->bitclk_freq = freq; | |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
17467f23 | 623 | /** |
85ef2375 | 624 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
625 | * |
626 | * Most of the SSI registers have been programmed in the startup function, | |
627 | * but the word length must be programmed here. Unfortunately, programming | |
628 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
629 | * cause a problem with supporting simultaneous playback and capture. If | |
630 | * the SSI is already playing a stream, then that stream may be temporarily | |
631 | * stopped when you start capture. | |
632 | * | |
633 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
634 | * clock master. | |
635 | */ | |
85ef2375 TT |
636 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
637 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 638 | { |
f0fba2ad | 639 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
5e538eca | 640 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
2924a998 | 641 | unsigned int channels = params_channels(hw_params); |
5e538eca TT |
642 | unsigned int sample_size = |
643 | snd_pcm_format_width(params_format(hw_params)); | |
644 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); | |
dfa1a107 | 645 | int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; |
8dd51e23 | 646 | int ret; |
17467f23 | 647 | |
5e538eca TT |
648 | /* |
649 | * If we're in synchronous mode, and the SSI is already enabled, | |
650 | * then STCCR is already set properly. | |
651 | */ | |
652 | if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) | |
653 | return 0; | |
17467f23 | 654 | |
8dd51e23 SH |
655 | if (fsl_ssi_is_i2s_master(ssi_private)) { |
656 | ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params); | |
657 | if (ret) | |
658 | return ret; | |
659 | } | |
660 | ||
5e538eca TT |
661 | /* |
662 | * FIXME: The documentation says that SxCCR[WL] should not be | |
663 | * modified while the SSI is enabled. The only time this can | |
664 | * happen is if we're trying to do simultaneous playback and | |
665 | * capture in asynchronous mode. Unfortunately, I have been enable | |
666 | * to get that to work at all on the P1022DS. Therefore, we don't | |
667 | * bother to disable/enable the SSI when setting SxCCR[WL], because | |
668 | * the SSI will stop anyway. Maybe one day, this will get fixed. | |
669 | */ | |
17467f23 | 670 | |
5e538eca TT |
671 | /* In synchronous mode, the SSI uses STCCR for capture */ |
672 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || | |
673 | ssi_private->cpu_dai_drv.symmetric_rates) | |
dfa1a107 | 674 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
5e538eca | 675 | else |
dfa1a107 | 676 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
17467f23 | 677 | |
171d683d | 678 | if (!fsl_ssi_is_ac97(ssi_private)) |
2924a998 NC |
679 | write_ssi_mask(&ssi->scr, |
680 | CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, | |
681 | channels == 1 ? 0 : ssi_private->i2s_mode); | |
682 | ||
17467f23 TT |
683 | return 0; |
684 | } | |
685 | ||
85e59af2 MP |
686 | static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private, |
687 | unsigned int fmt) | |
aafa85e7 | 688 | { |
aafa85e7 NC |
689 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
690 | u32 strcr = 0, stcr, srcr, scr, mask; | |
2b0db996 MP |
691 | u8 wm; |
692 | ||
171d683d MP |
693 | ssi_private->dai_fmt = fmt; |
694 | ||
2b0db996 | 695 | fsl_ssi_setup_reg_vals(ssi_private); |
aafa85e7 NC |
696 | |
697 | scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); | |
50489479 | 698 | scr |= CCSR_SSI_SCR_SYNC_TX_FS; |
aafa85e7 NC |
699 | |
700 | mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | | |
701 | CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | | |
702 | CCSR_SSI_STCR_TEFS; | |
703 | stcr = read_ssi(&ssi->stcr) & ~mask; | |
704 | srcr = read_ssi(&ssi->srcr) & ~mask; | |
705 | ||
07a28dbe | 706 | ssi_private->i2s_mode = CCSR_SSI_SCR_NET; |
aafa85e7 NC |
707 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
708 | case SND_SOC_DAIFMT_I2S: | |
709 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
710 | case SND_SOC_DAIFMT_CBS_CFS: | |
07a28dbe | 711 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; |
b5dd91b3 SH |
712 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, |
713 | CCSR_SSI_SxCCR_DC(2)); | |
714 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, | |
715 | CCSR_SSI_SxCCR_DC(2)); | |
aafa85e7 NC |
716 | break; |
717 | case SND_SOC_DAIFMT_CBM_CFM: | |
07a28dbe | 718 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; |
aafa85e7 NC |
719 | break; |
720 | default: | |
721 | return -EINVAL; | |
722 | } | |
aafa85e7 NC |
723 | |
724 | /* Data on rising edge of bclk, frame low, 1clk before data */ | |
725 | strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | | |
726 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
727 | break; | |
728 | case SND_SOC_DAIFMT_LEFT_J: | |
729 | /* Data on rising edge of bclk, frame high */ | |
730 | strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; | |
731 | break; | |
732 | case SND_SOC_DAIFMT_DSP_A: | |
733 | /* Data on rising edge of bclk, frame high, 1clk before data */ | |
734 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
735 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
736 | break; | |
737 | case SND_SOC_DAIFMT_DSP_B: | |
738 | /* Data on rising edge of bclk, frame high */ | |
739 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
740 | CCSR_SSI_STCR_TXBIT0; | |
741 | break; | |
2b0db996 | 742 | case SND_SOC_DAIFMT_AC97: |
07a28dbe | 743 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; |
2b0db996 | 744 | break; |
aafa85e7 NC |
745 | default: |
746 | return -EINVAL; | |
747 | } | |
2b0db996 | 748 | scr |= ssi_private->i2s_mode; |
aafa85e7 NC |
749 | |
750 | /* DAI clock inversion */ | |
751 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
752 | case SND_SOC_DAIFMT_NB_NF: | |
753 | /* Nothing to do for both normal cases */ | |
754 | break; | |
755 | case SND_SOC_DAIFMT_IB_NF: | |
756 | /* Invert bit clock */ | |
757 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
758 | break; | |
759 | case SND_SOC_DAIFMT_NB_IF: | |
760 | /* Invert frame clock */ | |
761 | strcr ^= CCSR_SSI_STCR_TFSI; | |
762 | break; | |
763 | case SND_SOC_DAIFMT_IB_IF: | |
764 | /* Invert both clocks */ | |
765 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
766 | strcr ^= CCSR_SSI_STCR_TFSI; | |
767 | break; | |
768 | default: | |
769 | return -EINVAL; | |
770 | } | |
771 | ||
772 | /* DAI clock master masks */ | |
773 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
774 | case SND_SOC_DAIFMT_CBS_CFS: | |
775 | strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; | |
776 | scr |= CCSR_SSI_SCR_SYS_CLK_EN; | |
777 | break; | |
778 | case SND_SOC_DAIFMT_CBM_CFM: | |
779 | scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; | |
780 | break; | |
781 | default: | |
782 | return -EINVAL; | |
783 | } | |
784 | ||
785 | stcr |= strcr; | |
786 | srcr |= strcr; | |
787 | ||
788 | if (ssi_private->cpu_dai_drv.symmetric_rates) { | |
789 | /* Need to clear RXDIR when using SYNC mode */ | |
790 | srcr &= ~CCSR_SSI_SRCR_RXDIR; | |
791 | scr |= CCSR_SSI_SCR_SYN; | |
792 | } | |
793 | ||
794 | write_ssi(stcr, &ssi->stcr); | |
795 | write_ssi(srcr, &ssi->srcr); | |
796 | write_ssi(scr, &ssi->scr); | |
797 | ||
2b0db996 MP |
798 | /* |
799 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't | |
800 | * use FIFO 1. We program the transmit water to signal a DMA transfer | |
801 | * if there are only two (or fewer) elements left in the FIFO. Two | |
802 | * elements equals one frame (left channel, right channel). This value, | |
803 | * however, depends on the depth of the transmit buffer. | |
804 | * | |
805 | * We set the watermark on the same level as the DMA burstsize. For | |
806 | * fiq it is probably better to use the biggest possible watermark | |
807 | * size. | |
808 | */ | |
809 | if (ssi_private->use_dma) | |
810 | wm = ssi_private->fifo_depth - 2; | |
811 | else | |
812 | wm = ssi_private->fifo_depth; | |
813 | ||
814 | write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | | |
815 | CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm), | |
816 | &ssi->sfcsr); | |
817 | ||
818 | if (ssi_private->use_dual_fifo) { | |
819 | write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1, | |
820 | CCSR_SSI_SRCR_RFEN1); | |
821 | write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1, | |
822 | CCSR_SSI_STCR_TFEN1); | |
823 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN, | |
824 | CCSR_SSI_SCR_TCH_EN); | |
825 | } | |
826 | ||
827 | if (fmt & SND_SOC_DAIFMT_AC97) | |
828 | fsl_ssi_setup_ac97(ssi_private); | |
829 | ||
aafa85e7 | 830 | return 0; |
85e59af2 MP |
831 | |
832 | } | |
833 | ||
834 | /** | |
835 | * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. | |
836 | */ | |
837 | static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
838 | { | |
839 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
840 | ||
841 | return _fsl_ssi_set_dai_fmt(ssi_private, fmt); | |
aafa85e7 NC |
842 | } |
843 | ||
aafa85e7 NC |
844 | /** |
845 | * fsl_ssi_set_dai_tdm_slot - set TDM slot number | |
846 | * | |
847 | * Note: This function can be only called when using SSI as DAI master | |
848 | */ | |
849 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, | |
850 | u32 rx_mask, int slots, int slot_width) | |
851 | { | |
852 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
853 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
854 | u32 val; | |
855 | ||
856 | /* The slot number should be >= 2 if using Network mode or I2S mode */ | |
857 | val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET); | |
858 | if (val && slots < 2) { | |
859 | dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); | |
860 | return -EINVAL; | |
861 | } | |
862 | ||
863 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, | |
864 | CCSR_SSI_SxCCR_DC(slots)); | |
865 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, | |
866 | CCSR_SSI_SxCCR_DC(slots)); | |
867 | ||
868 | /* The register SxMSKs needs SSI to provide essential clock due to | |
869 | * hardware design. So we here temporarily enable SSI to set them. | |
870 | */ | |
871 | val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; | |
872 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); | |
873 | ||
874 | write_ssi(tx_mask, &ssi->stmsk); | |
875 | write_ssi(rx_mask, &ssi->srmsk); | |
876 | ||
877 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val); | |
878 | ||
879 | return 0; | |
880 | } | |
881 | ||
17467f23 TT |
882 | /** |
883 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
884 | * | |
885 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
886 | * transfer of data. | |
887 | * | |
888 | * The DMA channel is in external master start and pause mode, which | |
889 | * means the SSI completely controls the flow of data. | |
890 | */ | |
dee89c4d MB |
891 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
892 | struct snd_soc_dai *dai) | |
17467f23 TT |
893 | { |
894 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 895 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 | 896 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
9b443e3d | 897 | |
17467f23 TT |
898 | switch (cmd) { |
899 | case SNDRV_PCM_TRIGGER_START: | |
b20e53a8 | 900 | case SNDRV_PCM_TRIGGER_RESUME: |
17467f23 | 901 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 902 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
6de83879 | 903 | fsl_ssi_tx_config(ssi_private, true); |
a4d11fe5 | 904 | else |
6de83879 | 905 | fsl_ssi_rx_config(ssi_private, true); |
17467f23 TT |
906 | break; |
907 | ||
908 | case SNDRV_PCM_TRIGGER_STOP: | |
b20e53a8 | 909 | case SNDRV_PCM_TRIGGER_SUSPEND: |
17467f23 TT |
910 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
911 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
6de83879 | 912 | fsl_ssi_tx_config(ssi_private, false); |
17467f23 | 913 | else |
6de83879 | 914 | fsl_ssi_rx_config(ssi_private, false); |
b2c119b0 | 915 | |
171d683d | 916 | if (!fsl_ssi_is_ac97(ssi_private) && (read_ssi(&ssi->scr) & |
d8ced479 | 917 | (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) |
aafa85e7 | 918 | ssi_private->baudclk_locked = false; |
d8ced479 | 919 | |
17467f23 TT |
920 | break; |
921 | ||
922 | default: | |
923 | return -EINVAL; | |
924 | } | |
925 | ||
171d683d | 926 | if (fsl_ssi_is_ac97(ssi_private)) { |
a5a7ee7c MP |
927 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
928 | write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor); | |
929 | else | |
930 | write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor); | |
931 | } | |
9b443e3d | 932 | |
17467f23 TT |
933 | return 0; |
934 | } | |
935 | ||
fc8ba7f9 LPC |
936 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
937 | { | |
938 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); | |
939 | ||
fcdbadef | 940 | if (ssi_private->soc->imx && ssi_private->use_dma) { |
fc8ba7f9 LPC |
941 | dai->playback_dma_data = &ssi_private->dma_params_tx; |
942 | dai->capture_dma_data = &ssi_private->dma_params_rx; | |
943 | } | |
944 | ||
945 | return 0; | |
946 | } | |
947 | ||
85e7652d | 948 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
6335d055 EM |
949 | .startup = fsl_ssi_startup, |
950 | .hw_params = fsl_ssi_hw_params, | |
aafa85e7 NC |
951 | .set_fmt = fsl_ssi_set_dai_fmt, |
952 | .set_sysclk = fsl_ssi_set_dai_sysclk, | |
953 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, | |
6335d055 | 954 | .trigger = fsl_ssi_trigger, |
6335d055 EM |
955 | }; |
956 | ||
f0fba2ad LG |
957 | /* Template for the CPU dai driver structure */ |
958 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
fc8ba7f9 | 959 | .probe = fsl_ssi_dai_probe, |
17467f23 | 960 | .playback = { |
2924a998 | 961 | .channels_min = 1, |
17467f23 TT |
962 | .channels_max = 2, |
963 | .rates = FSLSSI_I2S_RATES, | |
964 | .formats = FSLSSI_I2S_FORMATS, | |
965 | }, | |
966 | .capture = { | |
2924a998 | 967 | .channels_min = 1, |
17467f23 TT |
968 | .channels_max = 2, |
969 | .rates = FSLSSI_I2S_RATES, | |
970 | .formats = FSLSSI_I2S_FORMATS, | |
971 | }, | |
6335d055 | 972 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
973 | }; |
974 | ||
3580aa10 KM |
975 | static const struct snd_soc_component_driver fsl_ssi_component = { |
976 | .name = "fsl-ssi", | |
977 | }; | |
978 | ||
cd7f0295 MP |
979 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { |
980 | .ac97_control = 1, | |
981 | .playback = { | |
982 | .stream_name = "AC97 Playback", | |
983 | .channels_min = 2, | |
984 | .channels_max = 2, | |
985 | .rates = SNDRV_PCM_RATE_8000_48000, | |
986 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
987 | }, | |
988 | .capture = { | |
989 | .stream_name = "AC97 Capture", | |
990 | .channels_min = 2, | |
991 | .channels_max = 2, | |
992 | .rates = SNDRV_PCM_RATE_48000, | |
993 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
994 | }, | |
a5a7ee7c | 995 | .ops = &fsl_ssi_dai_ops, |
cd7f0295 MP |
996 | }; |
997 | ||
998 | ||
999 | static struct fsl_ssi_private *fsl_ac97_data; | |
1000 | ||
a851a2bb | 1001 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
cd7f0295 MP |
1002 | unsigned short val) |
1003 | { | |
1004 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
1005 | unsigned int lreg; | |
1006 | unsigned int lval; | |
1007 | ||
1008 | if (reg > 0x7f) | |
1009 | return; | |
1010 | ||
1011 | ||
1012 | lreg = reg << 12; | |
1013 | write_ssi(lreg, &ssi->sacadd); | |
1014 | ||
1015 | lval = val << 4; | |
1016 | write_ssi(lval , &ssi->sacdat); | |
1017 | ||
1018 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
1019 | CCSR_SSI_SACNT_WR); | |
1020 | udelay(100); | |
1021 | } | |
1022 | ||
a851a2bb | 1023 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
cd7f0295 MP |
1024 | unsigned short reg) |
1025 | { | |
1026 | struct ccsr_ssi *ssi = fsl_ac97_data->ssi; | |
1027 | ||
1028 | unsigned short val = -1; | |
1029 | unsigned int lreg; | |
1030 | ||
1031 | lreg = (reg & 0x7f) << 12; | |
1032 | write_ssi(lreg, &ssi->sacadd); | |
1033 | write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, | |
1034 | CCSR_SSI_SACNT_RD); | |
1035 | ||
1036 | udelay(100); | |
1037 | ||
1038 | val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff; | |
1039 | ||
1040 | return val; | |
1041 | } | |
1042 | ||
1043 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { | |
1044 | .read = fsl_ssi_ac97_read, | |
1045 | .write = fsl_ssi_ac97_write, | |
1046 | }; | |
1047 | ||
17467f23 | 1048 | /** |
f0fba2ad | 1049 | * Make every character in a string lower-case |
17467f23 | 1050 | */ |
f0fba2ad LG |
1051 | static void make_lowercase(char *s) |
1052 | { | |
1053 | char *p = s; | |
1054 | char c; | |
1055 | ||
1056 | while ((c = *p)) { | |
1057 | if ((c >= 'A') && (c <= 'Z')) | |
1058 | *p = c + ('a' - 'A'); | |
1059 | p++; | |
1060 | } | |
1061 | } | |
1062 | ||
49da09e2 | 1063 | static int fsl_ssi_imx_probe(struct platform_device *pdev, |
4d9b7926 | 1064 | struct fsl_ssi_private *ssi_private, void __iomem *iomem) |
49da09e2 MP |
1065 | { |
1066 | struct device_node *np = pdev->dev.of_node; | |
ed0f1604 | 1067 | u32 dmas[4]; |
49da09e2 MP |
1068 | int ret; |
1069 | ||
1070 | ssi_private->clk = devm_clk_get(&pdev->dev, NULL); | |
1071 | if (IS_ERR(ssi_private->clk)) { | |
1072 | ret = PTR_ERR(ssi_private->clk); | |
1073 | dev_err(&pdev->dev, "could not get clock: %d\n", ret); | |
1074 | return ret; | |
1075 | } | |
1076 | ||
1077 | ret = clk_prepare_enable(ssi_private->clk); | |
1078 | if (ret) { | |
1079 | dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); | |
1080 | return ret; | |
1081 | } | |
1082 | ||
1083 | /* For those SLAVE implementations, we ingore non-baudclk cases | |
1084 | * and, instead, abandon MASTER mode that needs baud clock. | |
1085 | */ | |
1086 | ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); | |
1087 | if (IS_ERR(ssi_private->baudclk)) | |
1088 | dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", | |
1089 | PTR_ERR(ssi_private->baudclk)); | |
1090 | else | |
1091 | clk_prepare_enable(ssi_private->baudclk); | |
1092 | ||
1093 | /* | |
1094 | * We have burstsize be "fifo_depth - 2" to match the SSI | |
1095 | * watermark setting in fsl_ssi_startup(). | |
1096 | */ | |
1097 | ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2; | |
1098 | ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2; | |
1099 | ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + | |
1100 | offsetof(struct ccsr_ssi, stx0); | |
1101 | ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + | |
1102 | offsetof(struct ccsr_ssi, srx0); | |
49da09e2 | 1103 | |
ed0f1604 MP |
1104 | ret = !of_property_read_u32_array(np, "dmas", dmas, 4); |
1105 | if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { | |
49da09e2 MP |
1106 | ssi_private->use_dual_fifo = true; |
1107 | /* When using dual fifo mode, we need to keep watermark | |
1108 | * as even numbers due to dma script limitation. | |
1109 | */ | |
1110 | ssi_private->dma_params_tx.maxburst &= ~0x1; | |
1111 | ssi_private->dma_params_rx.maxburst &= ~0x1; | |
1112 | } | |
1113 | ||
4d9b7926 MP |
1114 | if (!ssi_private->use_dma) { |
1115 | ||
1116 | /* | |
1117 | * Some boards use an incompatible codec. To get it | |
1118 | * working, we are using imx-fiq-pcm-audio, that | |
1119 | * can handle those codecs. DMA is not possible in this | |
1120 | * situation. | |
1121 | */ | |
1122 | ||
1123 | ssi_private->fiq_params.irq = ssi_private->irq; | |
1124 | ssi_private->fiq_params.base = iomem; | |
1125 | ssi_private->fiq_params.dma_params_rx = | |
1126 | &ssi_private->dma_params_rx; | |
1127 | ssi_private->fiq_params.dma_params_tx = | |
1128 | &ssi_private->dma_params_tx; | |
1129 | ||
1130 | ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); | |
1131 | if (ret) | |
1132 | goto error_pcm; | |
1133 | } else { | |
1134 | ret = imx_pcm_dma_init(pdev); | |
1135 | if (ret) | |
1136 | goto error_pcm; | |
1137 | } | |
1138 | ||
49da09e2 | 1139 | return 0; |
4d9b7926 MP |
1140 | |
1141 | error_pcm: | |
1142 | if (!IS_ERR(ssi_private->baudclk)) | |
1143 | clk_disable_unprepare(ssi_private->baudclk); | |
1144 | ||
1145 | clk_disable_unprepare(ssi_private->clk); | |
1146 | ||
1147 | return ret; | |
49da09e2 MP |
1148 | } |
1149 | ||
1150 | static void fsl_ssi_imx_clean(struct platform_device *pdev, | |
1151 | struct fsl_ssi_private *ssi_private) | |
1152 | { | |
4d9b7926 MP |
1153 | if (!ssi_private->use_dma) |
1154 | imx_pcm_fiq_exit(pdev); | |
49da09e2 MP |
1155 | if (!IS_ERR(ssi_private->baudclk)) |
1156 | clk_disable_unprepare(ssi_private->baudclk); | |
1157 | clk_disable_unprepare(ssi_private->clk); | |
1158 | } | |
1159 | ||
a0a3d518 | 1160 | static int fsl_ssi_probe(struct platform_device *pdev) |
17467f23 | 1161 | { |
17467f23 TT |
1162 | struct fsl_ssi_private *ssi_private; |
1163 | int ret = 0; | |
38fec727 | 1164 | struct device_node *np = pdev->dev.of_node; |
c1953bfe | 1165 | const struct of_device_id *of_id; |
f0fba2ad | 1166 | const char *p, *sprop; |
8e9d8690 | 1167 | const uint32_t *iprop; |
f0fba2ad LG |
1168 | struct resource res; |
1169 | char name[64]; | |
17467f23 | 1170 | |
ff71334a TT |
1171 | /* SSIs that are not connected on the board should have a |
1172 | * status = "disabled" | |
1173 | * property in their device tree nodes. | |
f0fba2ad | 1174 | */ |
ff71334a | 1175 | if (!of_device_is_available(np)) |
f0fba2ad LG |
1176 | return -ENODEV; |
1177 | ||
c1953bfe | 1178 | of_id = of_match_device(fsl_ssi_ids, &pdev->dev); |
fcdbadef | 1179 | if (!of_id || !of_id->data) |
c1953bfe | 1180 | return -EINVAL; |
c1953bfe | 1181 | |
2a1d102d MP |
1182 | ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), |
1183 | GFP_KERNEL); | |
17467f23 | 1184 | if (!ssi_private) { |
38fec727 | 1185 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
f0fba2ad | 1186 | return -ENOMEM; |
17467f23 | 1187 | } |
17467f23 | 1188 | |
fcdbadef SH |
1189 | ssi_private->soc = of_id->data; |
1190 | ||
85e59af2 MP |
1191 | sprop = of_get_property(np, "fsl,mode", NULL); |
1192 | if (sprop) { | |
1193 | if (!strcmp(sprop, "ac97-slave")) | |
1194 | ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97; | |
1195 | else if (!strcmp(sprop, "i2s-slave")) | |
1196 | ssi_private->dai_fmt = SND_SOC_DAIFMT_I2S | | |
1197 | SND_SOC_DAIFMT_CBM_CFM; | |
1198 | } | |
1199 | ||
de623ece MP |
1200 | ssi_private->use_dma = !of_property_read_bool(np, |
1201 | "fsl,fiq-stream-filter"); | |
1202 | ||
85e59af2 | 1203 | if (fsl_ssi_is_ac97(ssi_private)) { |
cd7f0295 MP |
1204 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, |
1205 | sizeof(fsl_ssi_ac97_dai)); | |
1206 | ||
1207 | fsl_ac97_data = ssi_private; | |
cd7f0295 MP |
1208 | |
1209 | snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); | |
1210 | } else { | |
1211 | /* Initialize this copy of the CPU DAI driver structure */ | |
1212 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
1213 | sizeof(fsl_ssi_dai_template)); | |
1214 | } | |
2a1d102d | 1215 | ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); |
f0fba2ad LG |
1216 | |
1217 | /* Get the addresses and IRQ */ | |
1218 | ret = of_address_to_resource(np, 0, &res); | |
1219 | if (ret) { | |
38fec727 | 1220 | dev_err(&pdev->dev, "could not determine device resources\n"); |
b0a4747a | 1221 | return ret; |
f0fba2ad | 1222 | } |
147dfe90 TT |
1223 | ssi_private->ssi = of_iomap(np, 0); |
1224 | if (!ssi_private->ssi) { | |
1225 | dev_err(&pdev->dev, "could not map device resources\n"); | |
b0a4747a | 1226 | return -ENOMEM; |
147dfe90 | 1227 | } |
f0fba2ad | 1228 | ssi_private->ssi_phys = res.start; |
1fab6caf | 1229 | |
f0fba2ad | 1230 | ssi_private->irq = irq_of_parse_and_map(np, 0); |
d60336e2 | 1231 | if (!ssi_private->irq) { |
1fab6caf | 1232 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); |
b0a4747a | 1233 | return -ENXIO; |
1fab6caf TT |
1234 | } |
1235 | ||
f0fba2ad | 1236 | /* Are the RX and the TX clocks locked? */ |
07a9483a | 1237 | if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { |
f0fba2ad | 1238 | ssi_private->cpu_dai_drv.symmetric_rates = 1; |
07a9483a NC |
1239 | ssi_private->cpu_dai_drv.symmetric_channels = 1; |
1240 | ssi_private->cpu_dai_drv.symmetric_samplebits = 1; | |
1241 | } | |
17467f23 | 1242 | |
8e9d8690 TT |
1243 | /* Determine the FIFO depth. */ |
1244 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
1245 | if (iprop) | |
147dfe90 | 1246 | ssi_private->fifo_depth = be32_to_cpup(iprop); |
8e9d8690 TT |
1247 | else |
1248 | /* Older 8610 DTs didn't have the fifo-depth property */ | |
1249 | ssi_private->fifo_depth = 8; | |
1250 | ||
aafa85e7 | 1251 | ssi_private->baudclk_locked = false; |
aafa85e7 | 1252 | |
4d9b7926 MP |
1253 | dev_set_drvdata(&pdev->dev, ssi_private); |
1254 | ||
fcdbadef | 1255 | if (ssi_private->soc->imx) { |
4d9b7926 | 1256 | ret = fsl_ssi_imx_probe(pdev, ssi_private, ssi_private->ssi); |
49da09e2 | 1257 | if (ret) |
b0a4747a | 1258 | goto error_irqmap; |
0888efd1 MP |
1259 | } |
1260 | ||
4d9b7926 MP |
1261 | ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component, |
1262 | &ssi_private->cpu_dai_drv, 1); | |
1263 | if (ret) { | |
1264 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); | |
1265 | goto error_asoc_register; | |
1266 | } | |
1267 | ||
0888efd1 | 1268 | if (ssi_private->use_dma) { |
f0377086 | 1269 | ret = devm_request_irq(&pdev->dev, ssi_private->irq, |
171d683d | 1270 | fsl_ssi_isr, 0, dev_name(&pdev->dev), |
f0377086 MG |
1271 | ssi_private); |
1272 | if (ret < 0) { | |
1273 | dev_err(&pdev->dev, "could not claim irq %u\n", | |
1274 | ssi_private->irq); | |
49da09e2 | 1275 | goto error_irq; |
f0377086 | 1276 | } |
09ce1111 SG |
1277 | } |
1278 | ||
f138e621 | 1279 | ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); |
9368acc4 | 1280 | if (ret) |
4d9b7926 | 1281 | goto error_asoc_register; |
09ce1111 SG |
1282 | |
1283 | /* | |
1284 | * If codec-handle property is missing from SSI node, we assume | |
1285 | * that the machine driver uses new binding which does not require | |
1286 | * SSI driver to trigger machine driver's probe. | |
1287 | */ | |
171d683d | 1288 | if (!of_get_property(np, "codec-handle", NULL)) |
09ce1111 | 1289 | goto done; |
09ce1111 | 1290 | |
f0fba2ad | 1291 | /* Trigger the machine driver's probe function. The platform driver |
2b81ec69 | 1292 | * name of the machine driver is taken from /compatible property of the |
f0fba2ad LG |
1293 | * device tree. We also pass the address of the CPU DAI driver |
1294 | * structure. | |
1295 | */ | |
2b81ec69 SG |
1296 | sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); |
1297 | /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ | |
f0fba2ad LG |
1298 | p = strrchr(sprop, ','); |
1299 | if (p) | |
1300 | sprop = p + 1; | |
1301 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
1302 | make_lowercase(name); | |
1303 | ||
1304 | ssi_private->pdev = | |
38fec727 | 1305 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
f0fba2ad LG |
1306 | if (IS_ERR(ssi_private->pdev)) { |
1307 | ret = PTR_ERR(ssi_private->pdev); | |
38fec727 | 1308 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
4d9b7926 | 1309 | goto error_sound_card; |
3f4b783c | 1310 | } |
17467f23 | 1311 | |
09ce1111 | 1312 | done: |
85e59af2 MP |
1313 | if (ssi_private->dai_fmt) |
1314 | _fsl_ssi_set_dai_fmt(ssi_private, ssi_private->dai_fmt); | |
1315 | ||
f0fba2ad | 1316 | return 0; |
87a0632b | 1317 | |
4d9b7926 | 1318 | error_sound_card: |
f138e621 | 1319 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
9368acc4 | 1320 | |
4d9b7926 | 1321 | error_irq: |
3580aa10 | 1322 | snd_soc_unregister_component(&pdev->dev); |
1fab6caf | 1323 | |
4d9b7926 | 1324 | error_asoc_register: |
fcdbadef | 1325 | if (ssi_private->soc->imx) |
49da09e2 | 1326 | fsl_ssi_imx_clean(pdev, ssi_private); |
1fab6caf TT |
1327 | |
1328 | error_irqmap: | |
4d9b7926 | 1329 | if (ssi_private->use_dma) |
2841be9a | 1330 | irq_dispose_mapping(ssi_private->irq); |
1fab6caf | 1331 | |
87a0632b | 1332 | return ret; |
17467f23 | 1333 | } |
17467f23 | 1334 | |
38fec727 | 1335 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 1336 | { |
38fec727 | 1337 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
17467f23 | 1338 | |
f138e621 | 1339 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
9368acc4 | 1340 | |
171d683d | 1341 | if (ssi_private->pdev) |
09ce1111 | 1342 | platform_device_unregister(ssi_private->pdev); |
3580aa10 | 1343 | snd_soc_unregister_component(&pdev->dev); |
49da09e2 | 1344 | |
fcdbadef | 1345 | if (ssi_private->soc->imx) |
49da09e2 MP |
1346 | fsl_ssi_imx_clean(pdev, ssi_private); |
1347 | ||
4d9b7926 | 1348 | if (ssi_private->use_dma) |
2841be9a | 1349 | irq_dispose_mapping(ssi_private->irq); |
f0fba2ad LG |
1350 | |
1351 | return 0; | |
17467f23 | 1352 | } |
f0fba2ad | 1353 | |
f07eb223 | 1354 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
1355 | .driver = { |
1356 | .name = "fsl-ssi-dai", | |
1357 | .owner = THIS_MODULE, | |
1358 | .of_match_table = fsl_ssi_ids, | |
1359 | }, | |
1360 | .probe = fsl_ssi_probe, | |
1361 | .remove = fsl_ssi_remove, | |
1362 | }; | |
17467f23 | 1363 | |
ba0a7e02 | 1364 | module_platform_driver(fsl_ssi_driver); |
a454dad1 | 1365 | |
f3142807 | 1366 | MODULE_ALIAS("platform:fsl-ssi-dai"); |
17467f23 TT |
1367 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
1368 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 1369 | MODULE_LICENSE("GPL v2"); |