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17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
17467f23 TT |
11 | */ |
12 | ||
13 | #include <linux/init.h> | |
dfa1a107 | 14 | #include <linux/io.h> |
17467f23 TT |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
95cd98f9 | 17 | #include <linux/clk.h> |
17467f23 TT |
18 | #include <linux/device.h> |
19 | #include <linux/delay.h> | |
5a0e3ad6 | 20 | #include <linux/slab.h> |
dfa1a107 SG |
21 | #include <linux/of_address.h> |
22 | #include <linux/of_irq.h> | |
f0fba2ad | 23 | #include <linux/of_platform.h> |
17467f23 | 24 | |
17467f23 TT |
25 | #include <sound/core.h> |
26 | #include <sound/pcm.h> | |
27 | #include <sound/pcm_params.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/soc.h> | |
a8909c9b | 30 | #include <sound/dmaengine_pcm.h> |
17467f23 | 31 | |
17467f23 | 32 | #include "fsl_ssi.h" |
09ce1111 | 33 | #include "imx-pcm.h" |
17467f23 | 34 | |
dfa1a107 SG |
35 | #ifdef PPC |
36 | #define read_ssi(addr) in_be32(addr) | |
37 | #define write_ssi(val, addr) out_be32(addr, val) | |
38 | #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set) | |
39 | #elif defined ARM | |
40 | #define read_ssi(addr) readl(addr) | |
41 | #define write_ssi(val, addr) writel(val, addr) | |
42 | /* | |
43 | * FIXME: Proper locking should be added at write_ssi_mask caller level | |
44 | * to ensure this register read/modify/write sequence is race free. | |
45 | */ | |
46 | static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set) | |
47 | { | |
48 | u32 val = readl(addr); | |
49 | val = (val & ~clear) | set; | |
50 | writel(val, addr); | |
51 | } | |
52 | #endif | |
53 | ||
17467f23 TT |
54 | /** |
55 | * FSLSSI_I2S_RATES: sample rates supported by the I2S | |
56 | * | |
57 | * This driver currently only supports the SSI running in I2S slave mode, | |
58 | * which means the codec determines the sample rate. Therefore, we tell | |
59 | * ALSA that we support all rates and let the codec driver decide what rates | |
60 | * are really supported. | |
61 | */ | |
62 | #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ | |
63 | SNDRV_PCM_RATE_CONTINUOUS) | |
64 | ||
65 | /** | |
66 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
67 | * | |
68 | * This driver currently only supports the SSI running in I2S slave mode. | |
69 | * | |
70 | * The SSI has a limitation in that the samples must be in the same byte | |
71 | * order as the host CPU. This is because when multiple bytes are written | |
72 | * to the STX register, the bytes and bits must be written in the same | |
73 | * order. The STX is a shift register, so all the bits need to be aligned | |
74 | * (bit-endianness must match byte-endianness). Processors typically write | |
75 | * the bits within a byte in the same order that the bytes of a word are | |
76 | * written in. So if the host CPU is big-endian, then only big-endian | |
77 | * samples will be written to STX properly. | |
78 | */ | |
79 | #ifdef __BIG_ENDIAN | |
80 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
81 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
82 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
83 | #else | |
84 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
85 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
86 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
87 | #endif | |
88 | ||
d5a908b2 TT |
89 | /* SIER bitflag of interrupts to enable */ |
90 | #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \ | |
91 | CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \ | |
92 | CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \ | |
93 | CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \ | |
94 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN) | |
95 | ||
17467f23 TT |
96 | /** |
97 | * fsl_ssi_private: per-SSI private data | |
98 | * | |
17467f23 TT |
99 | * @ssi: pointer to the SSI's registers |
100 | * @ssi_phys: physical address of the SSI registers | |
101 | * @irq: IRQ of this SSI | |
be41e941 TT |
102 | * @first_stream: pointer to the stream that was opened first |
103 | * @second_stream: pointer to second stream | |
17467f23 TT |
104 | * @playback: the number of playback streams opened |
105 | * @capture: the number of capture streams opened | |
106 | * @cpu_dai: the CPU DAI for this device | |
107 | * @dev_attr: the sysfs device attribute structure | |
108 | * @stats: SSI statistics | |
f0fba2ad | 109 | * @name: name for this device |
17467f23 TT |
110 | */ |
111 | struct fsl_ssi_private { | |
17467f23 TT |
112 | struct ccsr_ssi __iomem *ssi; |
113 | dma_addr_t ssi_phys; | |
114 | unsigned int irq; | |
be41e941 TT |
115 | struct snd_pcm_substream *first_stream; |
116 | struct snd_pcm_substream *second_stream; | |
8e9d8690 | 117 | unsigned int fifo_depth; |
f0fba2ad | 118 | struct snd_soc_dai_driver cpu_dai_drv; |
17467f23 | 119 | struct device_attribute dev_attr; |
f0fba2ad | 120 | struct platform_device *pdev; |
17467f23 | 121 | |
09ce1111 SG |
122 | bool new_binding; |
123 | bool ssi_on_imx; | |
95cd98f9 | 124 | struct clk *clk; |
a8909c9b LPC |
125 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
126 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
127 | struct imx_dma_data filter_data_tx; | |
128 | struct imx_dma_data filter_data_rx; | |
09ce1111 | 129 | |
17467f23 TT |
130 | struct { |
131 | unsigned int rfrc; | |
132 | unsigned int tfrc; | |
133 | unsigned int cmdau; | |
134 | unsigned int cmddu; | |
135 | unsigned int rxt; | |
136 | unsigned int rdr1; | |
137 | unsigned int rdr0; | |
138 | unsigned int tde1; | |
139 | unsigned int tde0; | |
140 | unsigned int roe1; | |
141 | unsigned int roe0; | |
142 | unsigned int tue1; | |
143 | unsigned int tue0; | |
144 | unsigned int tfs; | |
145 | unsigned int rfs; | |
146 | unsigned int tls; | |
147 | unsigned int rls; | |
148 | unsigned int rff1; | |
149 | unsigned int rff0; | |
150 | unsigned int tfe1; | |
151 | unsigned int tfe0; | |
152 | } stats; | |
f0fba2ad LG |
153 | |
154 | char name[1]; | |
17467f23 TT |
155 | }; |
156 | ||
157 | /** | |
158 | * fsl_ssi_isr: SSI interrupt handler | |
159 | * | |
160 | * Although it's possible to use the interrupt handler to send and receive | |
161 | * data to/from the SSI, we use the DMA instead. Programming is more | |
162 | * complicated, but the performance is much better. | |
163 | * | |
164 | * This interrupt handler is used only to gather statistics. | |
165 | * | |
166 | * @irq: IRQ of the SSI device | |
167 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
168 | */ | |
169 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
170 | { | |
171 | struct fsl_ssi_private *ssi_private = dev_id; | |
172 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | |
173 | irqreturn_t ret = IRQ_NONE; | |
174 | __be32 sisr; | |
175 | __be32 sisr2 = 0; | |
176 | ||
177 | /* We got an interrupt, so read the status register to see what we | |
178 | were interrupted for. We mask it with the Interrupt Enable register | |
179 | so that we only check for events that we're interested in. | |
180 | */ | |
dfa1a107 | 181 | sisr = read_ssi(&ssi->sisr) & SIER_FLAGS; |
17467f23 TT |
182 | |
183 | if (sisr & CCSR_SSI_SISR_RFRC) { | |
184 | ssi_private->stats.rfrc++; | |
185 | sisr2 |= CCSR_SSI_SISR_RFRC; | |
186 | ret = IRQ_HANDLED; | |
187 | } | |
188 | ||
189 | if (sisr & CCSR_SSI_SISR_TFRC) { | |
190 | ssi_private->stats.tfrc++; | |
191 | sisr2 |= CCSR_SSI_SISR_TFRC; | |
192 | ret = IRQ_HANDLED; | |
193 | } | |
194 | ||
195 | if (sisr & CCSR_SSI_SISR_CMDAU) { | |
196 | ssi_private->stats.cmdau++; | |
197 | ret = IRQ_HANDLED; | |
198 | } | |
199 | ||
200 | if (sisr & CCSR_SSI_SISR_CMDDU) { | |
201 | ssi_private->stats.cmddu++; | |
202 | ret = IRQ_HANDLED; | |
203 | } | |
204 | ||
205 | if (sisr & CCSR_SSI_SISR_RXT) { | |
206 | ssi_private->stats.rxt++; | |
207 | ret = IRQ_HANDLED; | |
208 | } | |
209 | ||
210 | if (sisr & CCSR_SSI_SISR_RDR1) { | |
211 | ssi_private->stats.rdr1++; | |
212 | ret = IRQ_HANDLED; | |
213 | } | |
214 | ||
215 | if (sisr & CCSR_SSI_SISR_RDR0) { | |
216 | ssi_private->stats.rdr0++; | |
217 | ret = IRQ_HANDLED; | |
218 | } | |
219 | ||
220 | if (sisr & CCSR_SSI_SISR_TDE1) { | |
221 | ssi_private->stats.tde1++; | |
222 | ret = IRQ_HANDLED; | |
223 | } | |
224 | ||
225 | if (sisr & CCSR_SSI_SISR_TDE0) { | |
226 | ssi_private->stats.tde0++; | |
227 | ret = IRQ_HANDLED; | |
228 | } | |
229 | ||
230 | if (sisr & CCSR_SSI_SISR_ROE1) { | |
231 | ssi_private->stats.roe1++; | |
232 | sisr2 |= CCSR_SSI_SISR_ROE1; | |
233 | ret = IRQ_HANDLED; | |
234 | } | |
235 | ||
236 | if (sisr & CCSR_SSI_SISR_ROE0) { | |
237 | ssi_private->stats.roe0++; | |
238 | sisr2 |= CCSR_SSI_SISR_ROE0; | |
239 | ret = IRQ_HANDLED; | |
240 | } | |
241 | ||
242 | if (sisr & CCSR_SSI_SISR_TUE1) { | |
243 | ssi_private->stats.tue1++; | |
244 | sisr2 |= CCSR_SSI_SISR_TUE1; | |
245 | ret = IRQ_HANDLED; | |
246 | } | |
247 | ||
248 | if (sisr & CCSR_SSI_SISR_TUE0) { | |
249 | ssi_private->stats.tue0++; | |
250 | sisr2 |= CCSR_SSI_SISR_TUE0; | |
251 | ret = IRQ_HANDLED; | |
252 | } | |
253 | ||
254 | if (sisr & CCSR_SSI_SISR_TFS) { | |
255 | ssi_private->stats.tfs++; | |
256 | ret = IRQ_HANDLED; | |
257 | } | |
258 | ||
259 | if (sisr & CCSR_SSI_SISR_RFS) { | |
260 | ssi_private->stats.rfs++; | |
261 | ret = IRQ_HANDLED; | |
262 | } | |
263 | ||
264 | if (sisr & CCSR_SSI_SISR_TLS) { | |
265 | ssi_private->stats.tls++; | |
266 | ret = IRQ_HANDLED; | |
267 | } | |
268 | ||
269 | if (sisr & CCSR_SSI_SISR_RLS) { | |
270 | ssi_private->stats.rls++; | |
271 | ret = IRQ_HANDLED; | |
272 | } | |
273 | ||
274 | if (sisr & CCSR_SSI_SISR_RFF1) { | |
275 | ssi_private->stats.rff1++; | |
276 | ret = IRQ_HANDLED; | |
277 | } | |
278 | ||
279 | if (sisr & CCSR_SSI_SISR_RFF0) { | |
280 | ssi_private->stats.rff0++; | |
281 | ret = IRQ_HANDLED; | |
282 | } | |
283 | ||
284 | if (sisr & CCSR_SSI_SISR_TFE1) { | |
285 | ssi_private->stats.tfe1++; | |
286 | ret = IRQ_HANDLED; | |
287 | } | |
288 | ||
289 | if (sisr & CCSR_SSI_SISR_TFE0) { | |
290 | ssi_private->stats.tfe0++; | |
291 | ret = IRQ_HANDLED; | |
292 | } | |
293 | ||
294 | /* Clear the bits that we set */ | |
295 | if (sisr2) | |
dfa1a107 | 296 | write_ssi(sisr2, &ssi->sisr); |
17467f23 TT |
297 | |
298 | return ret; | |
299 | } | |
300 | ||
301 | /** | |
302 | * fsl_ssi_startup: create a new substream | |
303 | * | |
304 | * This is the first function called when a stream is opened. | |
305 | * | |
306 | * If this is the first stream open, then grab the IRQ and program most of | |
307 | * the SSI registers. | |
308 | */ | |
dee89c4d MB |
309 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
310 | struct snd_soc_dai *dai) | |
17467f23 TT |
311 | { |
312 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5e538eca TT |
313 | struct fsl_ssi_private *ssi_private = |
314 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
315 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates; | |
17467f23 TT |
316 | |
317 | /* | |
318 | * If this is the first stream opened, then request the IRQ | |
319 | * and initialize the SSI registers. | |
320 | */ | |
5e538eca | 321 | if (!ssi_private->first_stream) { |
17467f23 | 322 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
17467f23 | 323 | |
5e538eca TT |
324 | ssi_private->first_stream = substream; |
325 | ||
17467f23 TT |
326 | /* |
327 | * Section 16.5 of the MPC8610 reference manual says that the | |
328 | * SSI needs to be disabled before updating the registers we set | |
329 | * here. | |
330 | */ | |
dfa1a107 | 331 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); |
17467f23 TT |
332 | |
333 | /* | |
334 | * Program the SSI into I2S Slave Non-Network Synchronous mode. | |
335 | * Also enable the transmit and receive FIFO. | |
336 | * | |
337 | * FIXME: Little-endian samples require a different shift dir | |
338 | */ | |
dfa1a107 | 339 | write_ssi_mask(&ssi->scr, |
a454dad1 TT |
340 | CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN, |
341 | CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE | |
5e538eca | 342 | | (synchronous ? CCSR_SSI_SCR_SYN : 0)); |
17467f23 | 343 | |
dfa1a107 | 344 | write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 | |
17467f23 | 345 | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS | |
dfa1a107 | 346 | CCSR_SSI_STCR_TSCKP, &ssi->stcr); |
17467f23 | 347 | |
dfa1a107 | 348 | write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 | |
17467f23 | 349 | CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS | |
dfa1a107 | 350 | CCSR_SSI_SRCR_RSCKP, &ssi->srcr); |
17467f23 TT |
351 | |
352 | /* | |
353 | * The DC and PM bits are only used if the SSI is the clock | |
354 | * master. | |
355 | */ | |
356 | ||
5e538eca | 357 | /* Enable the interrupts and DMA requests */ |
dfa1a107 | 358 | write_ssi(SIER_FLAGS, &ssi->sier); |
17467f23 TT |
359 | |
360 | /* | |
361 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We | |
8e9d8690 TT |
362 | * don't use FIFO 1. We program the transmit water to signal a |
363 | * DMA transfer if there are only two (or fewer) elements left | |
364 | * in the FIFO. Two elements equals one frame (left channel, | |
365 | * right channel). This value, however, depends on the depth of | |
366 | * the transmit buffer. | |
367 | * | |
368 | * We program the receive FIFO to notify us if at least two | |
369 | * elements (one frame) have been written to the FIFO. We could | |
370 | * make this value larger (and maybe we should), but this way | |
371 | * data will be written to memory as soon as it's available. | |
17467f23 | 372 | */ |
dfa1a107 SG |
373 | write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) | |
374 | CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2), | |
375 | &ssi->sfcsr); | |
17467f23 TT |
376 | |
377 | /* | |
378 | * We keep the SSI disabled because if we enable it, then the | |
379 | * DMA controller will start. It's not supposed to start until | |
380 | * the SCR.TE (or SCR.RE) bit is set, but it does anyway. The | |
381 | * DMA controller will transfer one "BWC" of data (i.e. the | |
382 | * amount of data that the MR.BWC bits are set to). The reason | |
383 | * this is bad is because at this point, the PCM driver has not | |
384 | * finished initializing the DMA controller. | |
385 | */ | |
5e538eca TT |
386 | } else { |
387 | if (synchronous) { | |
388 | struct snd_pcm_runtime *first_runtime = | |
389 | ssi_private->first_stream->runtime; | |
390 | /* | |
391 | * This is the second stream open, and we're in | |
392 | * synchronous mode, so we need to impose sample | |
393 | * sample size constraints. This is because STCCR is | |
394 | * used for playback and capture in synchronous mode, | |
395 | * so there's no way to specify different word | |
396 | * lengths. | |
397 | * | |
398 | * Note that this can cause a race condition if the | |
399 | * second stream is opened before the first stream is | |
400 | * fully initialized. We provide some protection by | |
401 | * checking to make sure the first stream is | |
402 | * initialized, but it's not perfect. ALSA sometimes | |
403 | * re-initializes the driver with a different sample | |
404 | * rate or size. If the second stream is opened | |
405 | * before the first stream has received its final | |
406 | * parameters, then the second stream may be | |
407 | * constrained to the wrong sample rate or size. | |
408 | */ | |
409 | if (!first_runtime->sample_bits) { | |
410 | dev_err(substream->pcm->card->dev, | |
411 | "set sample size in %s stream first\n", | |
412 | substream->stream == | |
413 | SNDRV_PCM_STREAM_PLAYBACK | |
414 | ? "capture" : "playback"); | |
415 | return -EAGAIN; | |
416 | } | |
be41e941 | 417 | |
a454dad1 TT |
418 | snd_pcm_hw_constraint_minmax(substream->runtime, |
419 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
420 | first_runtime->sample_bits, | |
421 | first_runtime->sample_bits); | |
5e538eca | 422 | } |
be41e941 TT |
423 | |
424 | ssi_private->second_stream = substream; | |
425 | } | |
426 | ||
17467f23 TT |
427 | return 0; |
428 | } | |
429 | ||
430 | /** | |
85ef2375 | 431 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
432 | * |
433 | * Most of the SSI registers have been programmed in the startup function, | |
434 | * but the word length must be programmed here. Unfortunately, programming | |
435 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
436 | * cause a problem with supporting simultaneous playback and capture. If | |
437 | * the SSI is already playing a stream, then that stream may be temporarily | |
438 | * stopped when you start capture. | |
439 | * | |
440 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
441 | * clock master. | |
442 | */ | |
85ef2375 TT |
443 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
444 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 445 | { |
f0fba2ad | 446 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
5e538eca TT |
447 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
448 | unsigned int sample_size = | |
449 | snd_pcm_format_width(params_format(hw_params)); | |
450 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); | |
dfa1a107 | 451 | int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; |
17467f23 | 452 | |
5e538eca TT |
453 | /* |
454 | * If we're in synchronous mode, and the SSI is already enabled, | |
455 | * then STCCR is already set properly. | |
456 | */ | |
457 | if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) | |
458 | return 0; | |
17467f23 | 459 | |
5e538eca TT |
460 | /* |
461 | * FIXME: The documentation says that SxCCR[WL] should not be | |
462 | * modified while the SSI is enabled. The only time this can | |
463 | * happen is if we're trying to do simultaneous playback and | |
464 | * capture in asynchronous mode. Unfortunately, I have been enable | |
465 | * to get that to work at all on the P1022DS. Therefore, we don't | |
466 | * bother to disable/enable the SSI when setting SxCCR[WL], because | |
467 | * the SSI will stop anyway. Maybe one day, this will get fixed. | |
468 | */ | |
17467f23 | 469 | |
5e538eca TT |
470 | /* In synchronous mode, the SSI uses STCCR for capture */ |
471 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || | |
472 | ssi_private->cpu_dai_drv.symmetric_rates) | |
dfa1a107 | 473 | write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
5e538eca | 474 | else |
dfa1a107 | 475 | write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); |
17467f23 TT |
476 | |
477 | return 0; | |
478 | } | |
479 | ||
480 | /** | |
481 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
482 | * | |
483 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
484 | * transfer of data. | |
485 | * | |
486 | * The DMA channel is in external master start and pause mode, which | |
487 | * means the SSI completely controls the flow of data. | |
488 | */ | |
dee89c4d MB |
489 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
490 | struct snd_soc_dai *dai) | |
17467f23 TT |
491 | { |
492 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 493 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 TT |
494 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
495 | ||
496 | switch (cmd) { | |
497 | case SNDRV_PCM_TRIGGER_START: | |
17467f23 | 498 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 499 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
dfa1a107 | 500 | write_ssi_mask(&ssi->scr, 0, |
be41e941 | 501 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE); |
a4d11fe5 | 502 | else |
dfa1a107 | 503 | write_ssi_mask(&ssi->scr, 0, |
be41e941 | 504 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE); |
17467f23 TT |
505 | break; |
506 | ||
507 | case SNDRV_PCM_TRIGGER_STOP: | |
17467f23 TT |
508 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
509 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
dfa1a107 | 510 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0); |
17467f23 | 511 | else |
dfa1a107 | 512 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0); |
b2c119b0 NC |
513 | |
514 | if ((read_ssi(&ssi->scr) & (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) | |
515 | write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0); | |
17467f23 TT |
516 | break; |
517 | ||
518 | default: | |
519 | return -EINVAL; | |
520 | } | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | /** | |
526 | * fsl_ssi_shutdown: shutdown the SSI | |
527 | * | |
528 | * Shutdown the SSI if there are no other substreams open. | |
529 | */ | |
dee89c4d MB |
530 | static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, |
531 | struct snd_soc_dai *dai) | |
17467f23 TT |
532 | { |
533 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 534 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
17467f23 | 535 | |
be41e941 TT |
536 | if (ssi_private->first_stream == substream) |
537 | ssi_private->first_stream = ssi_private->second_stream; | |
538 | ||
539 | ssi_private->second_stream = NULL; | |
17467f23 TT |
540 | } |
541 | ||
fc8ba7f9 LPC |
542 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
543 | { | |
544 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); | |
545 | ||
546 | if (ssi_private->ssi_on_imx) { | |
547 | dai->playback_dma_data = &ssi_private->dma_params_tx; | |
548 | dai->capture_dma_data = &ssi_private->dma_params_rx; | |
549 | } | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
85e7652d | 554 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
6335d055 EM |
555 | .startup = fsl_ssi_startup, |
556 | .hw_params = fsl_ssi_hw_params, | |
557 | .shutdown = fsl_ssi_shutdown, | |
558 | .trigger = fsl_ssi_trigger, | |
6335d055 EM |
559 | }; |
560 | ||
f0fba2ad LG |
561 | /* Template for the CPU dai driver structure */ |
562 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
fc8ba7f9 | 563 | .probe = fsl_ssi_dai_probe, |
17467f23 TT |
564 | .playback = { |
565 | /* The SSI does not support monaural audio. */ | |
566 | .channels_min = 2, | |
567 | .channels_max = 2, | |
568 | .rates = FSLSSI_I2S_RATES, | |
569 | .formats = FSLSSI_I2S_FORMATS, | |
570 | }, | |
571 | .capture = { | |
572 | .channels_min = 2, | |
573 | .channels_max = 2, | |
574 | .rates = FSLSSI_I2S_RATES, | |
575 | .formats = FSLSSI_I2S_FORMATS, | |
576 | }, | |
6335d055 | 577 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
578 | }; |
579 | ||
3580aa10 KM |
580 | static const struct snd_soc_component_driver fsl_ssi_component = { |
581 | .name = "fsl-ssi", | |
582 | }; | |
583 | ||
d5a908b2 TT |
584 | /* Show the statistics of a flag only if its interrupt is enabled. The |
585 | * compiler will optimze this code to a no-op if the interrupt is not | |
586 | * enabled. | |
587 | */ | |
588 | #define SIER_SHOW(flag, name) \ | |
589 | do { \ | |
590 | if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \ | |
591 | length += sprintf(buf + length, #name "=%u\n", \ | |
592 | ssi_private->stats.name); \ | |
593 | } while (0) | |
594 | ||
595 | ||
17467f23 TT |
596 | /** |
597 | * fsl_sysfs_ssi_show: display SSI statistics | |
598 | * | |
d5a908b2 TT |
599 | * Display the statistics for the current SSI device. To avoid confusion, |
600 | * we only show those counts that are enabled. | |
17467f23 TT |
601 | */ |
602 | static ssize_t fsl_sysfs_ssi_show(struct device *dev, | |
603 | struct device_attribute *attr, char *buf) | |
604 | { | |
605 | struct fsl_ssi_private *ssi_private = | |
d5a908b2 TT |
606 | container_of(attr, struct fsl_ssi_private, dev_attr); |
607 | ssize_t length = 0; | |
608 | ||
609 | SIER_SHOW(RFRC_EN, rfrc); | |
610 | SIER_SHOW(TFRC_EN, tfrc); | |
611 | SIER_SHOW(CMDAU_EN, cmdau); | |
612 | SIER_SHOW(CMDDU_EN, cmddu); | |
613 | SIER_SHOW(RXT_EN, rxt); | |
614 | SIER_SHOW(RDR1_EN, rdr1); | |
615 | SIER_SHOW(RDR0_EN, rdr0); | |
616 | SIER_SHOW(TDE1_EN, tde1); | |
617 | SIER_SHOW(TDE0_EN, tde0); | |
618 | SIER_SHOW(ROE1_EN, roe1); | |
619 | SIER_SHOW(ROE0_EN, roe0); | |
620 | SIER_SHOW(TUE1_EN, tue1); | |
621 | SIER_SHOW(TUE0_EN, tue0); | |
622 | SIER_SHOW(TFS_EN, tfs); | |
623 | SIER_SHOW(RFS_EN, rfs); | |
624 | SIER_SHOW(TLS_EN, tls); | |
625 | SIER_SHOW(RLS_EN, rls); | |
626 | SIER_SHOW(RFF1_EN, rff1); | |
627 | SIER_SHOW(RFF0_EN, rff0); | |
628 | SIER_SHOW(TFE1_EN, tfe1); | |
629 | SIER_SHOW(TFE0_EN, tfe0); | |
17467f23 TT |
630 | |
631 | return length; | |
632 | } | |
633 | ||
634 | /** | |
f0fba2ad | 635 | * Make every character in a string lower-case |
17467f23 | 636 | */ |
f0fba2ad LG |
637 | static void make_lowercase(char *s) |
638 | { | |
639 | char *p = s; | |
640 | char c; | |
641 | ||
642 | while ((c = *p)) { | |
643 | if ((c >= 'A') && (c <= 'Z')) | |
644 | *p = c + ('a' - 'A'); | |
645 | p++; | |
646 | } | |
647 | } | |
648 | ||
a0a3d518 | 649 | static int fsl_ssi_probe(struct platform_device *pdev) |
17467f23 | 650 | { |
17467f23 TT |
651 | struct fsl_ssi_private *ssi_private; |
652 | int ret = 0; | |
87a0632b | 653 | struct device_attribute *dev_attr = NULL; |
38fec727 | 654 | struct device_node *np = pdev->dev.of_node; |
f0fba2ad | 655 | const char *p, *sprop; |
8e9d8690 | 656 | const uint32_t *iprop; |
f0fba2ad LG |
657 | struct resource res; |
658 | char name[64]; | |
312bb4f6 | 659 | bool shared; |
17467f23 | 660 | |
ff71334a TT |
661 | /* SSIs that are not connected on the board should have a |
662 | * status = "disabled" | |
663 | * property in their device tree nodes. | |
f0fba2ad | 664 | */ |
ff71334a | 665 | if (!of_device_is_available(np)) |
f0fba2ad LG |
666 | return -ENODEV; |
667 | ||
668 | /* We only support the SSI in "I2S Slave" mode */ | |
669 | sprop = of_get_property(np, "fsl,mode", NULL); | |
670 | if (!sprop || strcmp(sprop, "i2s-slave")) { | |
38fec727 | 671 | dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop); |
f0fba2ad LG |
672 | return -ENODEV; |
673 | } | |
674 | ||
675 | /* The DAI name is the last part of the full name of the node. */ | |
676 | p = strrchr(np->full_name, '/') + 1; | |
677 | ssi_private = kzalloc(sizeof(struct fsl_ssi_private) + strlen(p), | |
678 | GFP_KERNEL); | |
17467f23 | 679 | if (!ssi_private) { |
38fec727 | 680 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
f0fba2ad | 681 | return -ENOMEM; |
17467f23 | 682 | } |
17467f23 | 683 | |
f0fba2ad | 684 | strcpy(ssi_private->name, p); |
17467f23 | 685 | |
f0fba2ad LG |
686 | /* Initialize this copy of the CPU DAI driver structure */ |
687 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
688 | sizeof(fsl_ssi_dai_template)); | |
689 | ssi_private->cpu_dai_drv.name = ssi_private->name; | |
690 | ||
691 | /* Get the addresses and IRQ */ | |
692 | ret = of_address_to_resource(np, 0, &res); | |
693 | if (ret) { | |
38fec727 | 694 | dev_err(&pdev->dev, "could not determine device resources\n"); |
1fab6caf | 695 | goto error_kmalloc; |
f0fba2ad | 696 | } |
147dfe90 TT |
697 | ssi_private->ssi = of_iomap(np, 0); |
698 | if (!ssi_private->ssi) { | |
699 | dev_err(&pdev->dev, "could not map device resources\n"); | |
1fab6caf TT |
700 | ret = -ENOMEM; |
701 | goto error_kmalloc; | |
147dfe90 | 702 | } |
f0fba2ad | 703 | ssi_private->ssi_phys = res.start; |
1fab6caf | 704 | |
f0fba2ad | 705 | ssi_private->irq = irq_of_parse_and_map(np, 0); |
1fab6caf TT |
706 | if (ssi_private->irq == NO_IRQ) { |
707 | dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); | |
708 | ret = -ENXIO; | |
709 | goto error_iomap; | |
710 | } | |
711 | ||
712 | /* The 'name' should not have any slashes in it. */ | |
713 | ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, ssi_private->name, | |
714 | ssi_private); | |
715 | if (ret < 0) { | |
716 | dev_err(&pdev->dev, "could not claim irq %u\n", ssi_private->irq); | |
717 | goto error_irqmap; | |
718 | } | |
17467f23 | 719 | |
f0fba2ad | 720 | /* Are the RX and the TX clocks locked? */ |
5e538eca | 721 | if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) |
f0fba2ad | 722 | ssi_private->cpu_dai_drv.symmetric_rates = 1; |
17467f23 | 723 | |
8e9d8690 TT |
724 | /* Determine the FIFO depth. */ |
725 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
726 | if (iprop) | |
147dfe90 | 727 | ssi_private->fifo_depth = be32_to_cpup(iprop); |
8e9d8690 TT |
728 | else |
729 | /* Older 8610 DTs didn't have the fifo-depth property */ | |
730 | ssi_private->fifo_depth = 8; | |
731 | ||
09ce1111 SG |
732 | if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) { |
733 | u32 dma_events[2]; | |
734 | ssi_private->ssi_on_imx = true; | |
95cd98f9 SG |
735 | |
736 | ssi_private->clk = clk_get(&pdev->dev, NULL); | |
737 | if (IS_ERR(ssi_private->clk)) { | |
738 | ret = PTR_ERR(ssi_private->clk); | |
739 | dev_err(&pdev->dev, "could not get clock: %d\n", ret); | |
740 | goto error_irq; | |
741 | } | |
742 | clk_prepare_enable(ssi_private->clk); | |
743 | ||
09ce1111 SG |
744 | /* |
745 | * We have burstsize be "fifo_depth - 2" to match the SSI | |
746 | * watermark setting in fsl_ssi_startup(). | |
747 | */ | |
a8909c9b | 748 | ssi_private->dma_params_tx.maxburst = |
09ce1111 | 749 | ssi_private->fifo_depth - 2; |
a8909c9b | 750 | ssi_private->dma_params_rx.maxburst = |
09ce1111 | 751 | ssi_private->fifo_depth - 2; |
a8909c9b | 752 | ssi_private->dma_params_tx.addr = |
09ce1111 | 753 | ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0); |
a8909c9b | 754 | ssi_private->dma_params_rx.addr = |
09ce1111 | 755 | ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0); |
a8909c9b LPC |
756 | ssi_private->dma_params_tx.filter_data = |
757 | &ssi_private->filter_data_tx; | |
758 | ssi_private->dma_params_rx.filter_data = | |
759 | &ssi_private->filter_data_rx; | |
09ce1111 SG |
760 | /* |
761 | * TODO: This is a temporary solution and should be changed | |
762 | * to use generic DMA binding later when the helplers get in. | |
763 | */ | |
764 | ret = of_property_read_u32_array(pdev->dev.of_node, | |
765 | "fsl,ssi-dma-events", dma_events, 2); | |
766 | if (ret) { | |
767 | dev_err(&pdev->dev, "could not get dma events\n"); | |
95cd98f9 | 768 | goto error_clk; |
09ce1111 | 769 | } |
312bb4f6 LPC |
770 | |
771 | shared = of_device_is_compatible(of_get_parent(np), | |
772 | "fsl,spba-bus"); | |
773 | ||
a8909c9b | 774 | imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx, |
312bb4f6 | 775 | dma_events[0], shared); |
a8909c9b | 776 | imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx, |
312bb4f6 | 777 | dma_events[1], shared); |
09ce1111 SG |
778 | } |
779 | ||
17467f23 | 780 | /* Initialize the the device_attribute structure */ |
f0fba2ad | 781 | dev_attr = &ssi_private->dev_attr; |
0f768a72 | 782 | sysfs_attr_init(&dev_attr->attr); |
f0fba2ad | 783 | dev_attr->attr.name = "statistics"; |
17467f23 TT |
784 | dev_attr->attr.mode = S_IRUGO; |
785 | dev_attr->show = fsl_sysfs_ssi_show; | |
786 | ||
38fec727 | 787 | ret = device_create_file(&pdev->dev, dev_attr); |
17467f23 | 788 | if (ret) { |
38fec727 | 789 | dev_err(&pdev->dev, "could not create sysfs %s file\n", |
17467f23 | 790 | ssi_private->dev_attr.attr.name); |
1fab6caf | 791 | goto error_irq; |
17467f23 TT |
792 | } |
793 | ||
f0fba2ad | 794 | /* Register with ASoC */ |
38fec727 | 795 | dev_set_drvdata(&pdev->dev, ssi_private); |
3f4b783c | 796 | |
3580aa10 KM |
797 | ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component, |
798 | &ssi_private->cpu_dai_drv, 1); | |
87a0632b | 799 | if (ret) { |
38fec727 | 800 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); |
1fab6caf | 801 | goto error_dev; |
f0fba2ad LG |
802 | } |
803 | ||
09ce1111 | 804 | if (ssi_private->ssi_on_imx) { |
bd41bc96 SG |
805 | ret = imx_pcm_dma_init(pdev); |
806 | if (ret) | |
09ce1111 | 807 | goto error_dev; |
09ce1111 SG |
808 | } |
809 | ||
810 | /* | |
811 | * If codec-handle property is missing from SSI node, we assume | |
812 | * that the machine driver uses new binding which does not require | |
813 | * SSI driver to trigger machine driver's probe. | |
814 | */ | |
815 | if (!of_get_property(np, "codec-handle", NULL)) { | |
816 | ssi_private->new_binding = true; | |
817 | goto done; | |
818 | } | |
819 | ||
f0fba2ad | 820 | /* Trigger the machine driver's probe function. The platform driver |
2b81ec69 | 821 | * name of the machine driver is taken from /compatible property of the |
f0fba2ad LG |
822 | * device tree. We also pass the address of the CPU DAI driver |
823 | * structure. | |
824 | */ | |
2b81ec69 SG |
825 | sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); |
826 | /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ | |
f0fba2ad LG |
827 | p = strrchr(sprop, ','); |
828 | if (p) | |
829 | sprop = p + 1; | |
830 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
831 | make_lowercase(name); | |
832 | ||
833 | ssi_private->pdev = | |
38fec727 | 834 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
f0fba2ad LG |
835 | if (IS_ERR(ssi_private->pdev)) { |
836 | ret = PTR_ERR(ssi_private->pdev); | |
38fec727 | 837 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
1fab6caf | 838 | goto error_dai; |
3f4b783c | 839 | } |
17467f23 | 840 | |
09ce1111 | 841 | done: |
f0fba2ad | 842 | return 0; |
87a0632b | 843 | |
1fab6caf | 844 | error_dai: |
09ce1111 | 845 | if (ssi_private->ssi_on_imx) |
bd41bc96 | 846 | imx_pcm_dma_exit(pdev); |
3580aa10 | 847 | snd_soc_unregister_component(&pdev->dev); |
1fab6caf TT |
848 | |
849 | error_dev: | |
38fec727 | 850 | dev_set_drvdata(&pdev->dev, NULL); |
1fab6caf TT |
851 | device_remove_file(&pdev->dev, dev_attr); |
852 | ||
95cd98f9 SG |
853 | error_clk: |
854 | if (ssi_private->ssi_on_imx) { | |
855 | clk_disable_unprepare(ssi_private->clk); | |
856 | clk_put(ssi_private->clk); | |
857 | } | |
858 | ||
1fab6caf TT |
859 | error_irq: |
860 | free_irq(ssi_private->irq, ssi_private); | |
861 | ||
862 | error_irqmap: | |
87a0632b | 863 | irq_dispose_mapping(ssi_private->irq); |
1fab6caf TT |
864 | |
865 | error_iomap: | |
87a0632b | 866 | iounmap(ssi_private->ssi); |
1fab6caf TT |
867 | |
868 | error_kmalloc: | |
87a0632b TT |
869 | kfree(ssi_private); |
870 | ||
871 | return ret; | |
17467f23 | 872 | } |
17467f23 | 873 | |
38fec727 | 874 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 875 | { |
38fec727 | 876 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
17467f23 | 877 | |
09ce1111 SG |
878 | if (!ssi_private->new_binding) |
879 | platform_device_unregister(ssi_private->pdev); | |
95cd98f9 | 880 | if (ssi_private->ssi_on_imx) { |
bd41bc96 | 881 | imx_pcm_dma_exit(pdev); |
95cd98f9 SG |
882 | clk_disable_unprepare(ssi_private->clk); |
883 | clk_put(ssi_private->clk); | |
884 | } | |
3580aa10 | 885 | snd_soc_unregister_component(&pdev->dev); |
38fec727 | 886 | device_remove_file(&pdev->dev, &ssi_private->dev_attr); |
3f4b783c | 887 | |
1fab6caf TT |
888 | free_irq(ssi_private->irq, ssi_private); |
889 | irq_dispose_mapping(ssi_private->irq); | |
890 | ||
17467f23 | 891 | kfree(ssi_private); |
38fec727 | 892 | dev_set_drvdata(&pdev->dev, NULL); |
f0fba2ad LG |
893 | |
894 | return 0; | |
17467f23 | 895 | } |
f0fba2ad LG |
896 | |
897 | static const struct of_device_id fsl_ssi_ids[] = { | |
898 | { .compatible = "fsl,mpc8610-ssi", }, | |
09ce1111 | 899 | { .compatible = "fsl,imx21-ssi", }, |
f0fba2ad LG |
900 | {} |
901 | }; | |
902 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
903 | ||
f07eb223 | 904 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
905 | .driver = { |
906 | .name = "fsl-ssi-dai", | |
907 | .owner = THIS_MODULE, | |
908 | .of_match_table = fsl_ssi_ids, | |
909 | }, | |
910 | .probe = fsl_ssi_probe, | |
911 | .remove = fsl_ssi_remove, | |
912 | }; | |
17467f23 | 913 | |
ba0a7e02 | 914 | module_platform_driver(fsl_ssi_driver); |
a454dad1 | 915 | |
17467f23 TT |
916 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
917 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 918 | MODULE_LICENSE("GPL v2"); |