[deliverable/linux.git] / sound / soc / fsl / imx-ssi.c

/*
 * imx-ssi.c  --  ALSA Soc Audio Layer
 *
 * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
 *
 * This code is based on code copyrighted by Freescale,
 * Liam Girdwood, Javier Martin and probably others.
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *
 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
 * one FIFO which combines all valid receive slots. We cannot even select
 * which slots we want to receive. The WM9712 with which this driver
 * was developed with always sends GPIO status data in slot 12 which
 * we receive in our (PCM-) data stream. The only chance we have is to
 * manually skip this data in the FIQ handler. With sampling rates different
 * from 48000Hz not every frame has valid receive data, so the ratio
 * between pcm data and GPIO status data changes. Our FIQ handler is not
 * able to handle this, hence this driver only works with 48000Hz sampling
 * rate.
 * Reading and writing AC97 registers is another challenge. The core
 * provides us status bits when the read register is updated with *another*
 * value. When we read the same register two times (and the register still
 * contains the same value) these status bits are not set. We work
 * around this by not polling these bits but only wait a fixed delay.
 *
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <sound/core.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include <linux/platform_data/asoc-imx-ssi.h>

#include "imx-ssi.h"

#define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)

/*
 * SSI Network Mode or TDM slots configuration.
 * Should only be called when port is inactive (i.e. SSIEN = 0).
 */
static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
	unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
	u32 sccr;

	sccr = readl(ssi->base + SSI_STCCR);
	sccr &= ~SSI_STCCR_DC_MASK;
	sccr |= SSI_STCCR_DC(slots - 1);
	writel(sccr, ssi->base + SSI_STCCR);

	sccr = readl(ssi->base + SSI_SRCCR);
	sccr &= ~SSI_STCCR_DC_MASK;
	sccr |= SSI_STCCR_DC(slots - 1);
	writel(sccr, ssi->base + SSI_SRCCR);

	writel(tx_mask, ssi->base + SSI_STMSK);
	writel(rx_mask, ssi->base + SSI_SRMSK);

	return 0;
}

/*
 * SSI DAI format configuration.
 * Should only be called when port is inactive (i.e. SSIEN = 0).
 */
static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
	u32 strcr = 0, scr;

	scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);

	/* DAI mode */
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		/* data on rising edge of bclk, frame low 1clk before data */
		strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
		scr |= SSI_SCR_NET;
		if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
			scr &= ~SSI_I2S_MODE_MASK;
			scr |= SSI_SCR_I2S_MODE_SLAVE;
		}
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		/* data on rising edge of bclk, frame high with data */
		strcr |= SSI_STCR_TXBIT0;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		/* data on rising edge of bclk, frame high with data */
		strcr |= SSI_STCR_TFSL | SSI_STCR_TXBIT0;
		break;
	case SND_SOC_DAIFMT_DSP_A:
		/* data on rising edge of bclk, frame high 1clk before data */
		strcr |= SSI_STCR_TFSL | SSI_STCR_TXBIT0 | SSI_STCR_TEFS;
		break;
	}

	/* DAI clock inversion */
	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_IF:
		strcr |= SSI_STCR_TFSI;
		strcr &= ~SSI_STCR_TSCKP;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
		break;
	case SND_SOC_DAIFMT_NB_IF:
		strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
		break;
	case SND_SOC_DAIFMT_NB_NF:
		strcr &= ~SSI_STCR_TFSI;
		strcr |= SSI_STCR_TSCKP;
		break;
	}

	/* DAI clock master masks */
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	default:
		/* Master mode not implemented, needs handling of clocks. */
		return -EINVAL;
	}

	strcr |= SSI_STCR_TFEN0;

	if (ssi->flags & IMX_SSI_NET)
		scr |= SSI_SCR_NET;
	if (ssi->flags & IMX_SSI_SYN)
		scr |= SSI_SCR_SYN;

	writel(strcr, ssi->base + SSI_STCR);
	writel(strcr, ssi->base + SSI_SRCR);
	writel(scr, ssi->base + SSI_SCR);

	return 0;
}

/*
 * SSI system clock configuration.
 * Should only be called when port is inactive (i.e. SSIEN = 0).
 */
static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
	u32 scr;

	scr = readl(ssi->base + SSI_SCR);

	switch (clk_id) {
	case IMX_SSP_SYS_CLK:
		if (dir == SND_SOC_CLOCK_OUT)
			scr |= SSI_SCR_SYS_CLK_EN;
		else
			scr &= ~SSI_SCR_SYS_CLK_EN;
		break;
	default:
		return -EINVAL;
	}

	writel(scr, ssi->base + SSI_SCR);

	return 0;
}

/*
 * SSI Clock dividers
 * Should only be called when port is inactive (i.e. SSIEN = 0).
 */
static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
				  int div_id, int div)
{
	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
	u32 stccr, srccr;

	stccr = readl(ssi->base + SSI_STCCR);
	srccr = readl(ssi->base + SSI_SRCCR);

	switch (div_id) {
	case IMX_SSI_TX_DIV_2:
		stccr &= ~SSI_STCCR_DIV2;
		stccr |= div;
		break;
	case IMX_SSI_TX_DIV_PSR:
		stccr &= ~SSI_STCCR_PSR;
		stccr |= div;
		break;
	case IMX_SSI_TX_DIV_PM:
		stccr &= ~0xff;
		stccr |= SSI_STCCR_PM(div);
		break;
	case IMX_SSI_RX_DIV_2:
		stccr &= ~SSI_STCCR_DIV2;
		stccr |= div;
		break;
	case IMX_SSI_RX_DIV_PSR:
		stccr &= ~SSI_STCCR_PSR;
		stccr |= div;
		break;
	case IMX_SSI_RX_DIV_PM:
		stccr &= ~0xff;
		stccr |= SSI_STCCR_PM(div);
		break;
	default:
		return -EINVAL;
	}

	writel(stccr, ssi->base + SSI_STCCR);
	writel(srccr, ssi->base + SSI_SRCCR);

	return 0;
}

static int imx_ssi_startup(struct snd_pcm_substream *substream,
			   struct snd_soc_dai *cpu_dai)
{
	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
	struct imx_pcm_dma_params *dma_data;

	/* Tx/Rx config */
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		dma_data = &ssi->dma_params_tx;
	else
		dma_data = &ssi->dma_params_rx;

	snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);

	return 0;
}

/*
 * Should only be called when port is inactive (i.e. SSIEN = 0),
 * although can be called multiple times by upper layers.
 */
static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
			     struct snd_pcm_hw_params *params,
			     struct snd_soc_dai *cpu_dai)
{
	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
	u32 reg, sccr;

	/* Tx/Rx config */
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		reg = SSI_STCCR;
	else
		reg = SSI_SRCCR;

	if (ssi->flags & IMX_SSI_SYN)
		reg = SSI_STCCR;

	sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;

	/* DAI data (word) size */
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		sccr |= SSI_SRCCR_WL(16);
		break;
	case SNDRV_PCM_FORMAT_S20_3LE:
		sccr |= SSI_SRCCR_WL(20);
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		sccr |= SSI_SRCCR_WL(24);
		break;
	}

	writel(sccr, ssi->base + reg);

	return 0;
}

static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
		struct snd_soc_dai *dai)
{
	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(dai);
	unsigned int sier_bits, sier;
	unsigned int scr;

	scr = readl(ssi->base + SSI_SCR);
	sier = readl(ssi->base + SSI_SIER);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		if (ssi->flags & IMX_SSI_DMA)
			sier_bits = SSI_SIER_TDMAE;
		else
			sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
	} else {
		if (ssi->flags & IMX_SSI_DMA)
			sier_bits = SSI_SIER_RDMAE;
		else
			sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
	}

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			scr |= SSI_SCR_TE;
		else
			scr |= SSI_SCR_RE;
		sier |= sier_bits;

		if (++ssi->enabled == 1)
			scr |= SSI_SCR_SSIEN;

		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			scr &= ~SSI_SCR_TE;
		else
			scr &= ~SSI_SCR_RE;
		sier &= ~sier_bits;

		if (--ssi->enabled == 0)
			scr &= ~SSI_SCR_SSIEN;

		break;
	default:
		return -EINVAL;
	}

	if (!(ssi->flags & IMX_SSI_USE_AC97))
		/* rx/tx are always enabled to access ac97 registers */
		writel(scr, ssi->base + SSI_SCR);

	writel(sier, ssi->base + SSI_SIER);

	return 0;
}

static const struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
	.startup	= imx_ssi_startup,
	.hw_params	= imx_ssi_hw_params,
	.set_fmt	= imx_ssi_set_dai_fmt,
	.set_clkdiv	= imx_ssi_set_dai_clkdiv,
	.set_sysclk	= imx_ssi_set_dai_sysclk,
	.set_tdm_slot	= imx_ssi_set_dai_tdm_slot,
	.trigger	= imx_ssi_trigger,
};

static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
{
	struct imx_ssi *ssi = dev_get_drvdata(dai->dev);
	uint32_t val;

	snd_soc_dai_set_drvdata(dai, ssi);

	val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) |
		SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
	writel(val, ssi->base + SSI_SFCSR);

	return 0;
}

static struct snd_soc_dai_driver imx_ssi_dai = {
	.probe = imx_ssi_dai_probe,
	.playback = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &imx_ssi_pcm_dai_ops,
};

static struct snd_soc_dai_driver imx_ac97_dai = {
	.probe = imx_ssi_dai_probe,
	.ac97_control = 1,
	.playback = {
		.stream_name = "AC97 Playback",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.capture = {
		.stream_name = "AC97 Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	.ops = &imx_ssi_pcm_dai_ops,
};

static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
{
	void __iomem *base = imx_ssi->base;

	writel(0x0, base + SSI_SCR);
	writel(0x0, base + SSI_STCR);
	writel(0x0, base + SSI_SRCR);

	writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);

	writel(SSI_SFCSR_RFWM0(8) |
		SSI_SFCSR_TFWM0(8) |
		SSI_SFCSR_RFWM1(8) |
		SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);

	writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
	writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);

	writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
	writel(SSI_SOR_WAIT(3), base + SSI_SOR);

	writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
			SSI_SCR_TE | SSI_SCR_RE,
			base + SSI_SCR);

	writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
	writel(0xff, base + SSI_SACCDIS);
	writel(0x300, base + SSI_SACCEN);
}

static struct imx_ssi *ac97_ssi;

static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
		unsigned short val)
{
	struct imx_ssi *imx_ssi = ac97_ssi;
	void __iomem *base = imx_ssi->base;
	unsigned int lreg;
	unsigned int lval;

	if (reg > 0x7f)
		return;

	pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);

	lreg = reg <<  12;
	writel(lreg, base + SSI_SACADD);

	lval = val << 4;
	writel(lval , base + SSI_SACDAT);

	writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
	udelay(100);
}

static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
		unsigned short reg)
{
	struct imx_ssi *imx_ssi = ac97_ssi;
	void __iomem *base = imx_ssi->base;

	unsigned short val = -1;
	unsigned int lreg;

	lreg = (reg & 0x7f) <<  12 ;
	writel(lreg, base + SSI_SACADD);
	writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);

	udelay(100);

	val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;

	pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);

	return val;
}

static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
{
	struct imx_ssi *imx_ssi = ac97_ssi;

	if (imx_ssi->ac97_reset)
		imx_ssi->ac97_reset(ac97);
}

static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
{
	struct imx_ssi *imx_ssi = ac97_ssi;

	if (imx_ssi->ac97_warm_reset)
		imx_ssi->ac97_warm_reset(ac97);
}

struct snd_ac97_bus_ops soc_ac97_ops = {
	.read		= imx_ssi_ac97_read,
	.write		= imx_ssi_ac97_write,
	.reset		= imx_ssi_ac97_reset,
	.warm_reset	= imx_ssi_ac97_warm_reset
};
EXPORT_SYMBOL_GPL(soc_ac97_ops);

static int imx_ssi_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct imx_ssi *ssi;
	struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
	int ret = 0;
	struct snd_soc_dai_driver *dai;

	ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
	if (!ssi)
		return -ENOMEM;
	dev_set_drvdata(&pdev->dev, ssi);

	if (pdata) {
		ssi->ac97_reset = pdata->ac97_reset;
		ssi->ac97_warm_reset = pdata->ac97_warm_reset;
		ssi->flags = pdata->flags;
	}

	ssi->irq = platform_get_irq(pdev, 0);

	ssi->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(ssi->clk)) {
		ret = PTR_ERR(ssi->clk);
		dev_err(&pdev->dev, "Cannot get the clock: %d\n",
			ret);
		goto failed_clk;
	}
	clk_prepare_enable(ssi->clk);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		ret = -ENODEV;
		goto failed_get_resource;
	}

	ssi->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ssi->base)) {
		ret = PTR_ERR(ssi->base);
		goto failed_register;
	}

	if (ssi->flags & IMX_SSI_USE_AC97) {
		if (ac97_ssi) {
			dev_err(&pdev->dev, "AC'97 SSI already registered\n");
			ret = -EBUSY;
			goto failed_register;
		}
		ac97_ssi = ssi;
		setup_channel_to_ac97(ssi);
		dai = &imx_ac97_dai;
	} else
		dai = &imx_ssi_dai;

	writel(0x0, ssi->base + SSI_SIER);

	ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
	ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;

	ssi->dma_params_tx.burstsize = 6;
	ssi->dma_params_rx.burstsize = 4;

	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
	if (res)
		ssi->dma_params_tx.dma = res->start;

	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
	if (res)
		ssi->dma_params_rx.dma = res->start;

	platform_set_drvdata(pdev, ssi);

	ret = snd_soc_register_dai(&pdev->dev, dai);
	if (ret) {
		dev_err(&pdev->dev, "register DAI failed\n");
		goto failed_register;
	}

	ssi->soc_platform_pdev_fiq = platform_device_alloc("imx-fiq-pcm-audio", pdev->id);
	if (!ssi->soc_platform_pdev_fiq) {
		ret = -ENOMEM;
		goto failed_pdev_fiq_alloc;
	}

	platform_set_drvdata(ssi->soc_platform_pdev_fiq, ssi);
	ret = platform_device_add(ssi->soc_platform_pdev_fiq);
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform device\n");
		goto failed_pdev_fiq_add;
	}

	ssi->soc_platform_pdev = platform_device_alloc("imx-pcm-audio", pdev->id);
	if (!ssi->soc_platform_pdev) {
		ret = -ENOMEM;
		goto failed_pdev_alloc;
	}

	platform_set_drvdata(ssi->soc_platform_pdev, ssi);
	ret = platform_device_add(ssi->soc_platform_pdev);
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform device\n");
		goto failed_pdev_add;
	}

	return 0;

failed_pdev_add:
	platform_device_put(ssi->soc_platform_pdev);
failed_pdev_alloc:
	platform_device_del(ssi->soc_platform_pdev_fiq);
failed_pdev_fiq_add:
	platform_device_put(ssi->soc_platform_pdev_fiq);
failed_pdev_fiq_alloc:
	snd_soc_unregister_dai(&pdev->dev);
failed_register:
	release_mem_region(res->start, resource_size(res));
failed_get_resource:
	clk_disable_unprepare(ssi->clk);
failed_clk:

	return ret;
}

static int imx_ssi_remove(struct platform_device *pdev)
{
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct imx_ssi *ssi = platform_get_drvdata(pdev);

	platform_device_unregister(ssi->soc_platform_pdev);
	platform_device_unregister(ssi->soc_platform_pdev_fiq);

	snd_soc_unregister_dai(&pdev->dev);

	if (ssi->flags & IMX_SSI_USE_AC97)
		ac97_ssi = NULL;

	release_mem_region(res->start, resource_size(res));
	clk_disable_unprepare(ssi->clk);

	return 0;
}

static struct platform_driver imx_ssi_driver = {
	.probe = imx_ssi_probe,
	.remove = imx_ssi_remove,

	.driver = {
		.name = "imx-ssi",
		.owner = THIS_MODULE,
	},
};

module_platform_driver(imx_ssi_driver);

/* Module information */
MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:imx-ssi");
Commit	Line	Data
8380222e SH	1	/*
	2	* imx-ssi.c -- ALSA Soc Audio Layer
	3	*
	4	* Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
	5	*
	6	* This code is based on code copyrighted by Freescale,
	7	* Liam Girdwood, Javier Martin and probably others.
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*
	14	*
	15	* The i.MX SSI core has some nasty limitations in AC97 mode. While most
	16	* sane processor vendors have a FIFO per AC97 slot, the i.MX has only
	17	* one FIFO which combines all valid receive slots. We cannot even select
	18	* which slots we want to receive. The WM9712 with which this driver
25985edc	19	* was developed with always sends GPIO status data in slot 12 which
8380222e SH	20	* we receive in our (PCM-) data stream. The only chance we have is to
	21	* manually skip this data in the FIQ handler. With sampling rates different
	22	* from 48000Hz not every frame has valid receive data, so the ratio
	23	* between pcm data and GPIO status data changes. Our FIQ handler is not
	24	* able to handle this, hence this driver only works with 48000Hz sampling
	25	* rate.
25d1fbfd	26	* Reading and writing AC97 registers is another challenge. The core
8380222e SH	27	* provides us status bits when the read register is updated with another
	28	* value. When we read the same register two times (and the register still
	29	* contains the same value) these status bits are not set. We work
	30	* around this by not polling these bits but only wait a fixed delay.
a23dc694	31	*
8380222e SH	32	*/
	33
	34	#include <linux/clk.h>
	35	#include <linux/delay.h>
	36	#include <linux/device.h>
	37	#include <linux/dma-mapping.h>
	38	#include <linux/init.h>
	39	#include <linux/interrupt.h>
	40	#include <linux/module.h>
	41	#include <linux/platform_device.h>
5a0e3ad6	42	#include <linux/slab.h>
8380222e SH	43
	44	#include <sound/core.h>
	45	#include <sound/initval.h>
	46	#include <sound/pcm.h>
	47	#include <sound/pcm_params.h>
	48	#include <sound/soc.h>
	49
82906b13	50	#include <linux/platform_data/asoc-imx-ssi.h>
8380222e SH	51
	52	#include "imx-ssi.h"
	53
	54	#define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN \| SSI_SACNT_FV)
	55
	56	/*
	57	* SSI Network Mode or TDM slots configuration.
	58	* Should only be called when port is inactive (i.e. SSIEN = 0).
	59	*/
	60	static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
	61	unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
	62	{
f0fba2ad	63	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
8380222e SH	64	u32 sccr;
	65
	66	sccr = readl(ssi->base + SSI_STCCR);
	67	sccr &= ~SSI_STCCR_DC_MASK;
	68	sccr \|= SSI_STCCR_DC(slots - 1);
	69	writel(sccr, ssi->base + SSI_STCCR);
	70
	71	sccr = readl(ssi->base + SSI_SRCCR);
	72	sccr &= ~SSI_STCCR_DC_MASK;
	73	sccr \|= SSI_STCCR_DC(slots - 1);
	74	writel(sccr, ssi->base + SSI_SRCCR);
	75
	76	writel(tx_mask, ssi->base + SSI_STMSK);
	77	writel(rx_mask, ssi->base + SSI_SRMSK);
	78
	79	return 0;
	80	}
	81
	82	/*
	83	* SSI DAI format configuration.
	84	* Should only be called when port is inactive (i.e. SSIEN = 0).
8380222e SH	85	*/
	86	static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
	87	{
f0fba2ad	88	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
8380222e SH	89	u32 strcr = 0, scr;
	90
	91	scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN \| SSI_SCR_NET);
	92
	93	/* DAI mode */
	94	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	95	case SND_SOC_DAIFMT_I2S:
	96	/* data on rising edge of bclk, frame low 1clk before data */
	97	strcr \|= SSI_STCR_TFSI \| SSI_STCR_TEFS \| SSI_STCR_TXBIT0;
	98	scr \|= SSI_SCR_NET;
0e796120 EB	99	if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
	100	scr &= ~SSI_I2S_MODE_MASK;
	101	scr \|= SSI_SCR_I2S_MODE_SLAVE;
	102	}
8380222e SH	103	break;
	104	case SND_SOC_DAIFMT_LEFT_J:
	105	/* data on rising edge of bclk, frame high with data */
	106	strcr \|= SSI_STCR_TXBIT0;
	107	break;
	108	case SND_SOC_DAIFMT_DSP_B:
	109	/* data on rising edge of bclk, frame high with data */
0a93421b	110	strcr \|= SSI_STCR_TFSL \| SSI_STCR_TXBIT0;
8380222e SH	111	break;
	112	case SND_SOC_DAIFMT_DSP_A:
	113	/* data on rising edge of bclk, frame high 1clk before data */
5ed80a75	114	strcr \|= SSI_STCR_TFSL \| SSI_STCR_TXBIT0 \| SSI_STCR_TEFS;
8380222e SH	115	break;
	116	}
	117
	118	/* DAI clock inversion */
	119	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	120	case SND_SOC_DAIFMT_IB_IF:
	121	strcr \|= SSI_STCR_TFSI;
	122	strcr &= ~SSI_STCR_TSCKP;
	123	break;
	124	case SND_SOC_DAIFMT_IB_NF:
	125	strcr &= ~(SSI_STCR_TSCKP \| SSI_STCR_TFSI);
	126	break;
	127	case SND_SOC_DAIFMT_NB_IF:
	128	strcr \|= SSI_STCR_TFSI \| SSI_STCR_TSCKP;
	129	break;
	130	case SND_SOC_DAIFMT_NB_NF:
	131	strcr &= ~SSI_STCR_TFSI;
	132	strcr \|= SSI_STCR_TSCKP;
	133	break;
	134	}
	135
	136	/* DAI clock master masks */
	137	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
d08a68bf	138	case SND_SOC_DAIFMT_CBM_CFM:
8380222e	139	break;
d08a68bf MB	140	default:
	141	/* Master mode not implemented, needs handling of clocks. */
	142	return -EINVAL;
8380222e SH	143	}
	144
	145	strcr \|= SSI_STCR_TFEN0;
	146
0e796120 EB	147	if (ssi->flags & IMX_SSI_NET)
	148	scr \|= SSI_SCR_NET;
	149	if (ssi->flags & IMX_SSI_SYN)
	150	scr \|= SSI_SCR_SYN;
	151
8380222e SH	152	writel(strcr, ssi->base + SSI_STCR);
	153	writel(strcr, ssi->base + SSI_SRCR);
	154	writel(scr, ssi->base + SSI_SCR);
	155
	156	return 0;
	157	}
	158
	159	/*
	160	* SSI system clock configuration.
	161	* Should only be called when port is inactive (i.e. SSIEN = 0).
	162	*/
	163	static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
	164	int clk_id, unsigned int freq, int dir)
	165	{
f0fba2ad	166	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
8380222e SH	167	u32 scr;
	168
	169	scr = readl(ssi->base + SSI_SCR);
	170
	171	switch (clk_id) {
	172	case IMX_SSP_SYS_CLK:
	173	if (dir == SND_SOC_CLOCK_OUT)
	174	scr \|= SSI_SCR_SYS_CLK_EN;
	175	else
	176	scr &= ~SSI_SCR_SYS_CLK_EN;
	177	break;
	178	default:
	179	return -EINVAL;
	180	}
	181
	182	writel(scr, ssi->base + SSI_SCR);
	183
	184	return 0;
	185	}
	186
	187	/*
	188	* SSI Clock dividers
	189	* Should only be called when port is inactive (i.e. SSIEN = 0).
	190	*/
	191	static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
	192	int div_id, int div)
	193	{
f0fba2ad	194	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
8380222e SH	195	u32 stccr, srccr;
	196
	197	stccr = readl(ssi->base + SSI_STCCR);
	198	srccr = readl(ssi->base + SSI_SRCCR);
	199
	200	switch (div_id) {
	201	case IMX_SSI_TX_DIV_2:
	202	stccr &= ~SSI_STCCR_DIV2;
	203	stccr \|= div;
	204	break;
	205	case IMX_SSI_TX_DIV_PSR:
	206	stccr &= ~SSI_STCCR_PSR;
	207	stccr \|= div;
	208	break;
	209	case IMX_SSI_TX_DIV_PM:
	210	stccr &= ~0xff;
	211	stccr \|= SSI_STCCR_PM(div);
	212	break;
	213	case IMX_SSI_RX_DIV_2:
	214	stccr &= ~SSI_STCCR_DIV2;
	215	stccr \|= div;
	216	break;
	217	case IMX_SSI_RX_DIV_PSR:
	218	stccr &= ~SSI_STCCR_PSR;
	219	stccr \|= div;
	220	break;
	221	case IMX_SSI_RX_DIV_PM:
	222	stccr &= ~0xff;
	223	stccr \|= SSI_STCCR_PM(div);
	224	break;
	225	default:
	226	return -EINVAL;
	227	}
	228
	229	writel(stccr, ssi->base + SSI_STCCR);
	230	writel(srccr, ssi->base + SSI_SRCCR);
	231
	232	return 0;
	233	}
	234
91a38540 LPC	235	static int imx_ssi_startup(struct snd_pcm_substream *substream,
	236	struct snd_soc_dai *cpu_dai)
	237	{
	238	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
	239	struct imx_pcm_dma_params *dma_data;
	240
	241	/* Tx/Rx config */
	242	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	243	dma_data = &ssi->dma_params_tx;
	244	else
	245	dma_data = &ssi->dma_params_rx;
	246
	247	snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
	248
	249	return 0;
	250	}
	251
8380222e SH	252	/*
	253	* Should only be called when port is inactive (i.e. SSIEN = 0),
	254	* although can be called multiple times by upper layers.
	255	*/
	256	static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
	257	struct snd_pcm_hw_params *params,
	258	struct snd_soc_dai *cpu_dai)
	259	{
f0fba2ad	260	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
8380222e SH	261	u32 reg, sccr;
	262
	263	/* Tx/Rx config */
91a38540	264	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
8380222e	265	reg = SSI_STCCR;
91a38540	266	else
8380222e	267	reg = SSI_SRCCR;
8380222e	268
70bf043b SH	269	if (ssi->flags & IMX_SSI_SYN)
	270	reg = SSI_STCCR;
	271
8380222e SH	272	sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
	273
	274	/* DAI data (word) size */
	275	switch (params_format(params)) {
	276	case SNDRV_PCM_FORMAT_S16_LE:
	277	sccr \|= SSI_SRCCR_WL(16);
	278	break;
	279	case SNDRV_PCM_FORMAT_S20_3LE:
	280	sccr \|= SSI_SRCCR_WL(20);
	281	break;
	282	case SNDRV_PCM_FORMAT_S24_LE:
	283	sccr \|= SSI_SRCCR_WL(24);
	284	break;
	285	}
	286
	287	writel(sccr, ssi->base + reg);
	288
	289	return 0;
	290	}
	291
	292	static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
	293	struct snd_soc_dai *dai)
	294	{
f0fba2ad	295	struct imx_ssi *ssi = snd_soc_dai_get_drvdata(dai);
8380222e SH	296	unsigned int sier_bits, sier;
	297	unsigned int scr;
	298
	299	scr = readl(ssi->base + SSI_SCR);
	300	sier = readl(ssi->base + SSI_SIER);
	301
	302	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	303	if (ssi->flags & IMX_SSI_DMA)
	304	sier_bits = SSI_SIER_TDMAE;
	305	else
	306	sier_bits = SSI_SIER_TIE \| SSI_SIER_TFE0_EN;
	307	} else {
	308	if (ssi->flags & IMX_SSI_DMA)
	309	sier_bits = SSI_SIER_RDMAE;
	310	else
	311	sier_bits = SSI_SIER_RIE \| SSI_SIER_RFF0_EN;
	312	}
	313
	314	switch (cmd) {
	315	case SNDRV_PCM_TRIGGER_START:
	316	case SNDRV_PCM_TRIGGER_RESUME:
	317	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	318	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	319	scr \|= SSI_SCR_TE;
	320	else
	321	scr \|= SSI_SCR_RE;
	322	sier \|= sier_bits;
	323
	324	if (++ssi->enabled == 1)
	325	scr \|= SSI_SCR_SSIEN;
	326
	327	break;
	328
	329	case SNDRV_PCM_TRIGGER_STOP:
	330	case SNDRV_PCM_TRIGGER_SUSPEND:
	331	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	332	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	333	scr &= ~SSI_SCR_TE;
	334	else
	335	scr &= ~SSI_SCR_RE;
	336	sier &= ~sier_bits;
	337
	338	if (--ssi->enabled == 0)
	339	scr &= ~SSI_SCR_SSIEN;
	340
	341	break;
	342	default:
	343	return -EINVAL;
	344	}
	345
	346	if (!(ssi->flags & IMX_SSI_USE_AC97))
	347	/* rx/tx are always enabled to access ac97 registers */
	348	writel(scr, ssi->base + SSI_SCR);
	349
	350	writel(sier, ssi->base + SSI_SIER);
	351
	352	return 0;
	353	}
	354
85e7652d	355	static const struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
91a38540	356	.startup = imx_ssi_startup,
8380222e SH	357	.hw_params = imx_ssi_hw_params,
	358	.set_fmt = imx_ssi_set_dai_fmt,
	359	.set_clkdiv = imx_ssi_set_dai_clkdiv,
	360	.set_sysclk = imx_ssi_set_dai_sysclk,
	361	.set_tdm_slot = imx_ssi_set_dai_tdm_slot,
	362	.trigger = imx_ssi_trigger,
	363	};
	364
f562be51 SH	365	static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
	366	{
	367	struct imx_ssi *ssi = dev_get_drvdata(dai->dev);
	368	uint32_t val;
	369
	370	snd_soc_dai_set_drvdata(dai, ssi);
	371
	372	val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) \|
	373	SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
	374	writel(val, ssi->base + SSI_SFCSR);
	375
	376	return 0;
	377	}
	378
f0fba2ad	379	static struct snd_soc_dai_driver imx_ssi_dai = {
f562be51	380	.probe = imx_ssi_dai_probe,
f0fba2ad	381	.playback = {
104c2299	382	.channels_min = 1,
f0fba2ad LG	383	.channels_max = 2,
	384	.rates = SNDRV_PCM_RATE_8000_96000,
	385	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	386	},
	387	.capture = {
104c2299	388	.channels_min = 1,
f0fba2ad LG	389	.channels_max = 2,
	390	.rates = SNDRV_PCM_RATE_8000_96000,
	391	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	392	},
	393	.ops = &imx_ssi_pcm_dai_ops,
8380222e	394	};
8380222e	395
f0fba2ad LG	396	static struct snd_soc_dai_driver imx_ac97_dai = {
f0fba2ad LG	397	.probe = imx_ssi_dai_probe,
8380222e SH	398	.ac97_control = 1,
	399	.playback = {
	400	.stream_name = "AC97 Playback",
	401	.channels_min = 2,
	402	.channels_max = 2,
	403	.rates = SNDRV_PCM_RATE_48000,
	404	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	405	},
	406	.capture = {
	407	.stream_name = "AC97 Capture",
	408	.channels_min = 2,
	409	.channels_max = 2,
	410	.rates = SNDRV_PCM_RATE_48000,
	411	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	412	},
	413	.ops = &imx_ssi_pcm_dai_ops,
	414	};
	415
	416	static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
	417	{
	418	void __iomem *base = imx_ssi->base;
	419
	420	writel(0x0, base + SSI_SCR);
	421	writel(0x0, base + SSI_STCR);
	422	writel(0x0, base + SSI_SRCR);
	423
	424	writel(SSI_SCR_SYN \| SSI_SCR_NET, base + SSI_SCR);
	425
	426	writel(SSI_SFCSR_RFWM0(8) \|
	427	SSI_SFCSR_TFWM0(8) \|
	428	SSI_SFCSR_RFWM1(8) \|
	429	SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
	430
	431	writel(SSI_STCCR_WL(16) \| SSI_STCCR_DC(12), base + SSI_STCCR);
	432	writel(SSI_STCCR_WL(16) \| SSI_STCCR_DC(12), base + SSI_SRCCR);
	433
	434	writel(SSI_SCR_SYN \| SSI_SCR_NET \| SSI_SCR_SSIEN, base + SSI_SCR);
	435	writel(SSI_SOR_WAIT(3), base + SSI_SOR);
	436
	437	writel(SSI_SCR_SYN \| SSI_SCR_NET \| SSI_SCR_SSIEN \|
	438	SSI_SCR_TE \| SSI_SCR_RE,
	439	base + SSI_SCR);
	440
	441	writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
	442	writel(0xff, base + SSI_SACCDIS);
	443	writel(0x300, base + SSI_SACCEN);
	444	}
	445
	446	static struct imx_ssi *ac97_ssi;
	447
	448	static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	449	unsigned short val)
	450	{
	451	struct imx_ssi *imx_ssi = ac97_ssi;
	452	void __iomem *base = imx_ssi->base;
	453	unsigned int lreg;
	454	unsigned int lval;
	455
	456	if (reg > 0x7f)
	457	return;
	458
	459	pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
	460
	461	lreg = reg << 12;
462	writel(lreg, base + SSI_SACADD);
463
464	lval = val << 4;
465	writel(lval , base + SSI_SACDAT);
466
467	writel(SSI_SACNT_DEFAULT \| SSI_SACNT_WR, base + SSI_SACNT);
468	udelay(100);
469	}
470
471	static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
472	unsigned short reg)
473	{
474	struct imx_ssi *imx_ssi = ac97_ssi;
475	void __iomem *base = imx_ssi->base;
476
477	unsigned short val = -1;
478	unsigned int lreg;
479
480	lreg = (reg & 0x7f) << 12 ;
481	writel(lreg, base + SSI_SACADD);
482	writel(SSI_SACNT_DEFAULT \| SSI_SACNT_RD, base + SSI_SACNT);
483
484	udelay(100);
485
486	val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
487
488	pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
489
490	return val;
491	}
492
493	static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
494	{
495	struct imx_ssi *imx_ssi = ac97_ssi;
496
497	if (imx_ssi->ac97_reset)
498	imx_ssi->ac97_reset(ac97);
499	}
500
501	static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
502	{
503	struct imx_ssi *imx_ssi = ac97_ssi;
504
505	if (imx_ssi->ac97_warm_reset)
506	imx_ssi->ac97_warm_reset(ac97);
507	}
508
509	struct snd_ac97_bus_ops soc_ac97_ops = {
510	.read = imx_ssi_ac97_read,
511	.write = imx_ssi_ac97_write,
512	.reset = imx_ssi_ac97_reset,
513	.warm_reset = imx_ssi_ac97_warm_reset
514	};
515	EXPORT_SYMBOL_GPL(soc_ac97_ops);
516
8380222e SH	517	static int imx_ssi_probe(struct platform_device *pdev)
	518	{
	519	struct resource *res;
	520	struct imx_ssi *ssi;
	521	struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
8380222e	522	int ret = 0;
f0fba2ad	523	struct snd_soc_dai_driver *dai;
8380222e	524
ad3ab1bb	525	ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
8380222e SH	526	if (!ssi)
8380222e SH	527	return -ENOMEM;
f0fba2ad	528	dev_set_drvdata(&pdev->dev, ssi);
8380222e SH	529
	530	if (pdata) {
	531	ssi->ac97_reset = pdata->ac97_reset;
	532	ssi->ac97_warm_reset = pdata->ac97_warm_reset;
	533	ssi->flags = pdata->flags;
	534	}
	535
8380222e SH	536	ssi->irq = platform_get_irq(pdev, 0);
8380222e SH	537
ad3ab1bb	538	ssi->clk = devm_clk_get(&pdev->dev, NULL);
8380222e SH	539	if (IS_ERR(ssi->clk)) {
	540	ret = PTR_ERR(ssi->clk);
	541	dev_err(&pdev->dev, "Cannot get the clock: %d\n",
	542	ret);
	543	goto failed_clk;
	544	}
41c73b6e	545	clk_prepare_enable(ssi->clk);
8380222e SH	546
	547	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	548	if (!res) {
	549	ret = -ENODEV;
	550	goto failed_get_resource;
	551	}
	552
b25b5aa0 TR	553	ssi->base = devm_ioremap_resource(&pdev->dev, res);
	554	if (IS_ERR(ssi->base)) {
	555	ret = PTR_ERR(ssi->base);
ad3ab1bb	556	goto failed_register;
8380222e SH	557	}
	558
	559	if (ssi->flags & IMX_SSI_USE_AC97) {
	560	if (ac97_ssi) {
a0f1e98b	561	dev_err(&pdev->dev, "AC'97 SSI already registered\n");
8380222e	562	ret = -EBUSY;
ad3ab1bb	563	goto failed_register;
8380222e SH	564	}
	565	ac97_ssi = ssi;
	566	setup_channel_to_ac97(ssi);
f0fba2ad	567	dai = &imx_ac97_dai;
8380222e	568	} else
f0fba2ad	569	dai = &imx_ssi_dai;
8380222e SH	570
	571	writel(0x0, ssi->base + SSI_SIER);
	572
	573	ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
	574	ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;
	575
9a3a101c	576	ssi->dma_params_tx.burstsize = 6;
0a93421b JM	577	ssi->dma_params_rx.burstsize = 4;
0a93421b JM	578
8380222e SH	579	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
	580	if (res)
	581	ssi->dma_params_tx.dma = res->start;
	582
	583	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
	584	if (res)
	585	ssi->dma_params_rx.dma = res->start;
	586
f0fba2ad	587	platform_set_drvdata(pdev, ssi);
8380222e	588
f0fba2ad	589	ret = snd_soc_register_dai(&pdev->dev, dai);
8380222e SH	590	if (ret) {
	591	dev_err(&pdev->dev, "register DAI failed\n");
	592	goto failed_register;
	593	}
	594
f562be51	595	ssi->soc_platform_pdev_fiq = platform_device_alloc("imx-fiq-pcm-audio", pdev->id);
ac8f924a AL	596	if (!ssi->soc_platform_pdev_fiq) {
ac8f924a AL	597	ret = -ENOMEM;
f562be51	598	goto failed_pdev_fiq_alloc;
ac8f924a AL	599	}
ac8f924a AL	600
f562be51 SH	601	platform_set_drvdata(ssi->soc_platform_pdev_fiq, ssi);
	602	ret = platform_device_add(ssi->soc_platform_pdev_fiq);
	603	if (ret) {
	604	dev_err(&pdev->dev, "failed to add platform device\n");
	605	goto failed_pdev_fiq_add;
	606	}
	607
	608	ssi->soc_platform_pdev = platform_device_alloc("imx-pcm-audio", pdev->id);
ac8f924a AL	609	if (!ssi->soc_platform_pdev) {
ac8f924a AL	610	ret = -ENOMEM;
f0fba2ad	611	goto failed_pdev_alloc;
ac8f924a AL	612	}
ac8f924a AL	613
f0fba2ad LG	614	platform_set_drvdata(ssi->soc_platform_pdev, ssi);
	615	ret = platform_device_add(ssi->soc_platform_pdev);
	616	if (ret) {
	617	dev_err(&pdev->dev, "failed to add platform device\n");
	618	goto failed_pdev_add;
	619	}
8380222e SH	620
	621	return 0;
	622
f0fba2ad LG	623	failed_pdev_add:
	624	platform_device_put(ssi->soc_platform_pdev);
	625	failed_pdev_alloc:
ac8f924a	626	platform_device_del(ssi->soc_platform_pdev_fiq);
f562be51 SH	627	failed_pdev_fiq_add:
	628	platform_device_put(ssi->soc_platform_pdev_fiq);
	629	failed_pdev_fiq_alloc:
f0fba2ad	630	snd_soc_unregister_dai(&pdev->dev);
8380222e	631	failed_register:
8380222e SH	632	release_mem_region(res->start, resource_size(res));
8380222e SH	633	failed_get_resource:
41c73b6e	634	clk_disable_unprepare(ssi->clk);
8380222e	635	failed_clk:
8380222e SH	636
	637	return ret;
	638	}
	639
a0a3d518	640	static int imx_ssi_remove(struct platform_device *pdev)
8380222e SH	641	{
	642	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	643	struct imx_ssi *ssi = platform_get_drvdata(pdev);
	644
ac8f924a AL	645	platform_device_unregister(ssi->soc_platform_pdev);
ac8f924a AL	646	platform_device_unregister(ssi->soc_platform_pdev_fiq);
f0fba2ad LG	647
f0fba2ad LG	648	snd_soc_unregister_dai(&pdev->dev);
8380222e SH	649
	650	if (ssi->flags & IMX_SSI_USE_AC97)
	651	ac97_ssi = NULL;
	652
8380222e	653	release_mem_region(res->start, resource_size(res));
41c73b6e	654	clk_disable_unprepare(ssi->clk);
8380222e SH	655
	656	return 0;
	657	}
	658
	659	static struct platform_driver imx_ssi_driver = {
	660	.probe = imx_ssi_probe,
a0a3d518	661	.remove = imx_ssi_remove,
8380222e SH	662
8380222e SH	663	.driver = {
205d231b	664	.name = "imx-ssi",
8380222e SH	665	.owner = THIS_MODULE,
	666	},
	667	};
	668
7a24b2ba	669	module_platform_driver(imx_ssi_driver);
8380222e SH	670
	671	/* Module information */
	672	MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
	673	MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
	674	MODULE_LICENSE("GPL");
96dcabb9	675	MODULE_ALIAS("platform:imx-ssi");