drivers: clean-up prom.h implicit includes
[deliverable/linux.git] / sound / soc / fsl / mpc5200_dma.c
CommitLineData
89dd0842
JS
1/*
2 * Freescale MPC5200 PSC DMA
3 * ALSA SoC Platform driver
4 *
5 * Copyright (C) 2008 Secret Lab Technologies Ltd.
dbcc3475 6 * Copyright (C) 2009 Jon Smirl, Digispeaker
89dd0842
JS
7 */
8
89dd0842 9#include <linux/module.h>
89dd0842 10#include <linux/of_device.h>
07a38b1b 11#include <linux/dma-mapping.h>
5a0e3ad6 12#include <linux/slab.h>
5af50730
RH
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
f0fba2ad 15#include <linux/of_platform.h>
89dd0842 16
89dd0842 17#include <sound/soc.h>
89dd0842 18
9a322993
PDM
19#include <linux/fsl/bestcomm/bestcomm.h>
20#include <linux/fsl/bestcomm/gen_bd.h>
89dd0842
JS
21#include <asm/mpc52xx_psc.h>
22
23#include "mpc5200_dma.h"
24
89dd0842
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25/*
26 * Interrupt handlers
27 */
cebe7767 28static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
89dd0842 29{
cebe7767
JS
30 struct psc_dma *psc_dma = _psc_dma;
31 struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
89dd0842
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32 u16 isr;
33
34 isr = in_be16(&regs->mpc52xx_psc_isr);
35
36 /* Playback underrun error */
cebe7767
JS
37 if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
38 psc_dma->stats.underrun_count++;
89dd0842
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39
40 /* Capture overrun error */
cebe7767
JS
41 if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
42 psc_dma->stats.overrun_count++;
89dd0842 43
dbcc3475 44 out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
89dd0842
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45
46 return IRQ_HANDLED;
47}
48
49/**
cebe7767 50 * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
89dd0842
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51 * @s: pointer to stream private data structure
52 *
53 * Enqueues another audio period buffer into the bestcomm queue.
54 *
55 * Note: The routine must only be called when there is space available in
56 * the queue. Otherwise the enqueue will fail and the audio ring buffer
57 * will get out of sync
58 */
cebe7767 59static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
89dd0842
JS
60{
61 struct bcom_bd *bd;
62
63 /* Prepare and enqueue the next buffer descriptor */
64 bd = bcom_prepare_next_buffer(s->bcom_task);
65 bd->status = s->period_bytes;
8f159d72 66 bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
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67 bcom_submit_next_buffer(s->bcom_task, NULL);
68
69 /* Update for next period */
8f159d72 70 s->period_next = (s->period_next + 1) % s->runtime->periods;
89dd0842
JS
71}
72
73/* Bestcomm DMA irq handler */
a68cc8da 74static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream)
89dd0842 75{
dbcc3475 76 struct psc_dma_stream *s = _psc_dma_stream;
89dd0842 77
dbcc3475
JS
78 spin_lock(&s->psc_dma->lock);
79 /* For each finished period, dequeue the completed period buffer
80 * and enqueue a new one in it's place. */
81 while (bcom_buffer_done(s->bcom_task)) {
82 bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
89dd0842 83
8f159d72 84 s->period_current = (s->period_current+1) % s->runtime->periods;
c4878274 85 s->period_count++;
dbcc3475
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86
87 psc_dma_bcom_enqueue_next_buffer(s);
89dd0842 88 }
dbcc3475 89 spin_unlock(&s->psc_dma->lock);
89dd0842 90
dbcc3475
JS
91 /* If the stream is active, then also inform the PCM middle layer
92 * of the period finished event. */
93 if (s->active)
94 snd_pcm_period_elapsed(s->stream);
95
96 return IRQ_HANDLED;
89dd0842
JS
97}
98
dbcc3475 99static int psc_dma_hw_free(struct snd_pcm_substream *substream)
89dd0842
JS
100{
101 snd_pcm_set_runtime_buffer(substream, NULL);
102 return 0;
103}
104
105/**
cebe7767 106 * psc_dma_trigger: start and stop the DMA transfer.
89dd0842
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107 *
108 * This function is called by ALSA to start, stop, pause, and resume the DMA
109 * transfer of data.
110 */
dbcc3475 111static int psc_dma_trigger(struct snd_pcm_substream *substream, int cmd)
89dd0842
JS
112{
113 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 114 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
89dd0842 115 struct snd_pcm_runtime *runtime = substream->runtime;
1d8222e8 116 struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
cebe7767 117 struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
89dd0842 118 u16 imr;
89dd0842 119 unsigned long flags;
dbcc3475 120 int i;
89dd0842 121
89dd0842
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122 switch (cmd) {
123 case SNDRV_PCM_TRIGGER_START:
c4878274
GL
124 dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n",
125 substream->pstr->stream, runtime->frame_bits,
126 (int)runtime->period_size, runtime->periods);
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127 s->period_bytes = frames_to_bytes(runtime,
128 runtime->period_size);
8f159d72
GL
129 s->period_next = 0;
130 s->period_current = 0;
89dd0842 131 s->active = 1;
c4878274 132 s->period_count = 0;
dbcc3475 133 s->runtime = runtime;
dbcc3475
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134
135 /* Fill up the bestcomm bd queue and enable DMA.
136 * This will begin filling the PSC's fifo.
137 */
138 spin_lock_irqsave(&psc_dma->lock, flags);
139
d56b6eb6 140 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
dbcc3475 141 bcom_gen_bd_rx_reset(s->bcom_task);
d56b6eb6 142 else
dbcc3475 143 bcom_gen_bd_tx_reset(s->bcom_task);
d56b6eb6
GL
144
145 for (i = 0; i < runtime->periods; i++)
146 if (!bcom_queue_full(s->bcom_task))
147 psc_dma_bcom_enqueue_next_buffer(s);
89dd0842 148
89dd0842 149 bcom_enable(s->bcom_task);
cebe7767 150 spin_unlock_irqrestore(&psc_dma->lock, flags);
89dd0842 151
dbcc3475
JS
152 out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
153
89dd0842
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154 break;
155
156 case SNDRV_PCM_TRIGGER_STOP:
c4878274
GL
157 dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n",
158 substream->pstr->stream, s->period_count);
89dd0842 159 s->active = 0;
89dd0842 160
dbcc3475 161 spin_lock_irqsave(&psc_dma->lock, flags);
89dd0842 162 bcom_disable(s->bcom_task);
dbcc3475
JS
163 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
164 bcom_gen_bd_rx_reset(s->bcom_task);
165 else
166 bcom_gen_bd_tx_reset(s->bcom_task);
167 spin_unlock_irqrestore(&psc_dma->lock, flags);
89dd0842
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168
169 break;
170
171 default:
c4878274
GL
172 dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n",
173 substream->pstr->stream, cmd);
89dd0842
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174 return -EINVAL;
175 }
176
177 /* Update interrupt enable settings */
178 imr = 0;
cebe7767 179 if (psc_dma->playback.active)
89dd0842 180 imr |= MPC52xx_PSC_IMR_TXEMP;
cebe7767 181 if (psc_dma->capture.active)
89dd0842 182 imr |= MPC52xx_PSC_IMR_ORERR;
dbcc3475 183 out_be16(&regs->isr_imr.imr, psc_dma->imr | imr);
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184
185 return 0;
186}
187
89dd0842
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188
189/* ---------------------------------------------------------------------
190 * The PSC DMA 'ASoC platform' driver
191 *
192 * Can be referenced by an 'ASoC machine' driver
193 * This driver only deals with the audio bus; it doesn't have any
194 * interaction with the attached codec
195 */
196
dbcc3475 197static const struct snd_pcm_hardware psc_dma_hardware = {
89dd0842
JS
198 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
199 SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
200 SNDRV_PCM_INFO_BATCH,
201 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
dbcc3475 202 SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
89dd0842
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203 .rate_min = 8000,
204 .rate_max = 48000,
dbcc3475 205 .channels_min = 1,
89dd0842
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206 .channels_max = 2,
207 .period_bytes_max = 1024 * 1024,
208 .period_bytes_min = 32,
209 .periods_min = 2,
210 .periods_max = 256,
211 .buffer_bytes_max = 2 * 1024 * 1024,
dbcc3475 212 .fifo_size = 512,
89dd0842
JS
213};
214
dbcc3475 215static int psc_dma_open(struct snd_pcm_substream *substream)
89dd0842 216{
dbcc3475 217 struct snd_pcm_runtime *runtime = substream->runtime;
89dd0842 218 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 219 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
cebe7767 220 struct psc_dma_stream *s;
dbcc3475 221 int rc;
89dd0842 222
dbcc3475 223 dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
89dd0842
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224
225 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 226 s = &psc_dma->capture;
89dd0842 227 else
cebe7767 228 s = &psc_dma->playback;
89dd0842 229
dbcc3475
JS
230 snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
231
232 rc = snd_pcm_hw_constraint_integer(runtime,
233 SNDRV_PCM_HW_PARAM_PERIODS);
234 if (rc < 0) {
235 dev_err(substream->pcm->card->dev, "invalid buffer size\n");
236 return rc;
237 }
89dd0842
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238
239 s->stream = substream;
240 return 0;
241}
242
dbcc3475 243static int psc_dma_close(struct snd_pcm_substream *substream)
89dd0842
JS
244{
245 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 246 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
cebe7767 247 struct psc_dma_stream *s;
89dd0842 248
dbcc3475 249 dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
89dd0842
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250
251 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 252 s = &psc_dma->capture;
89dd0842 253 else
cebe7767 254 s = &psc_dma->playback;
89dd0842 255
dbcc3475
JS
256 if (!psc_dma->playback.active &&
257 !psc_dma->capture.active) {
258
259 /* Disable all interrupts and reset the PSC */
260 out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
261 out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
262 }
89dd0842
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263 s->stream = NULL;
264 return 0;
265}
266
267static snd_pcm_uframes_t
dbcc3475 268psc_dma_pointer(struct snd_pcm_substream *substream)
89dd0842
JS
269{
270 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 271 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
cebe7767 272 struct psc_dma_stream *s;
89dd0842
JS
273 dma_addr_t count;
274
275 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 276 s = &psc_dma->capture;
89dd0842 277 else
cebe7767 278 s = &psc_dma->playback;
89dd0842 279
8f159d72 280 count = s->period_current * s->period_bytes;
89dd0842
JS
281
282 return bytes_to_frames(substream->runtime, count);
283}
284
dbcc3475
JS
285static int
286psc_dma_hw_params(struct snd_pcm_substream *substream,
287 struct snd_pcm_hw_params *params)
288{
289 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
290
291 return 0;
292}
293
294static struct snd_pcm_ops psc_dma_ops = {
295 .open = psc_dma_open,
296 .close = psc_dma_close,
297 .hw_free = psc_dma_hw_free,
89dd0842 298 .ioctl = snd_pcm_lib_ioctl,
dbcc3475
JS
299 .pointer = psc_dma_pointer,
300 .trigger = psc_dma_trigger,
301 .hw_params = psc_dma_hw_params,
89dd0842
JS
302};
303
350e16d5 304static u64 psc_dma_dmamask = DMA_BIT_MASK(32);
552d1ef6 305static int psc_dma_new(struct snd_soc_pcm_runtime *rtd)
89dd0842 306{
552d1ef6
LG
307 struct snd_card *card = rtd->card->snd_card;
308 struct snd_soc_dai *dai = rtd->cpu_dai;
309 struct snd_pcm *pcm = rtd->pcm;
f0fba2ad 310 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
dbcc3475 311 size_t size = psc_dma_hardware.buffer_bytes_max;
89dd0842
JS
312 int rc = 0;
313
f0fba2ad 314 dev_dbg(rtd->platform->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
89dd0842
JS
315 card, dai, pcm);
316
317 if (!card->dev->dma_mask)
dbcc3475 318 card->dev->dma_mask = &psc_dma_dmamask;
89dd0842 319 if (!card->dev->coherent_dma_mask)
350e16d5 320 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
89dd0842 321
6296914c 322 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
dbcc3475 323 rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
6296914c 324 size, &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
89dd0842
JS
325 if (rc)
326 goto playback_alloc_err;
327 }
328
6296914c 329 if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
dbcc3475 330 rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
6296914c 331 size, &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer);
89dd0842
JS
332 if (rc)
333 goto capture_alloc_err;
334 }
335
f0fba2ad
LG
336 if (rtd->codec->ac97)
337 rtd->codec->ac97->private_data = psc_dma;
dbcc3475 338
89dd0842
JS
339 return 0;
340
341 capture_alloc_err:
6296914c
JE
342 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream)
343 snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
dbcc3475 344
89dd0842
JS
345 playback_alloc_err:
346 dev_err(card->dev, "Cannot allocate buffer(s)\n");
dbcc3475 347
89dd0842
JS
348 return -ENOMEM;
349}
350
dbcc3475 351static void psc_dma_free(struct snd_pcm *pcm)
89dd0842
JS
352{
353 struct snd_soc_pcm_runtime *rtd = pcm->private_data;
354 struct snd_pcm_substream *substream;
355 int stream;
356
f0fba2ad 357 dev_dbg(rtd->platform->dev, "psc_dma_free(pcm=%p)\n", pcm);
89dd0842
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358
359 for (stream = 0; stream < 2; stream++) {
360 substream = pcm->streams[stream].substream;
361 if (substream) {
362 snd_dma_free_pages(&substream->dma_buffer);
363 substream->dma_buffer.area = NULL;
364 substream->dma_buffer.addr = 0;
365 }
366 }
367}
368
f0fba2ad
LG
369static struct snd_soc_platform_driver mpc5200_audio_dma_platform = {
370 .ops = &psc_dma_ops,
dbcc3475
JS
371 .pcm_new = &psc_dma_new,
372 .pcm_free = &psc_dma_free,
89dd0842 373};
dbcc3475 374
f515b673 375int mpc5200_audio_dma_create(struct platform_device *op)
dbcc3475
JS
376{
377 phys_addr_t fifo;
378 struct psc_dma *psc_dma;
379 struct resource res;
380 int size, irq, rc;
381 const __be32 *prop;
382 void __iomem *regs;
33d7f778 383 int ret;
dbcc3475
JS
384
385 /* Fetch the registers and IRQ of the PSC */
61c7a080
GL
386 irq = irq_of_parse_and_map(op->dev.of_node, 0);
387 if (of_address_to_resource(op->dev.of_node, 0, &res)) {
dbcc3475
JS
388 dev_err(&op->dev, "Missing reg property\n");
389 return -ENODEV;
390 }
28f65c11 391 regs = ioremap(res.start, resource_size(&res));
dbcc3475
JS
392 if (!regs) {
393 dev_err(&op->dev, "Could not map registers\n");
394 return -ENODEV;
395 }
396
397 /* Allocate and initialize the driver private data */
398 psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
399 if (!psc_dma) {
33d7f778
JL
400 ret = -ENOMEM;
401 goto out_unmap;
dbcc3475
JS
402 }
403
404 /* Get the PSC ID */
61c7a080 405 prop = of_get_property(op->dev.of_node, "cell-index", &size);
33d7f778
JL
406 if (!prop || size < sizeof *prop) {
407 ret = -ENODEV;
408 goto out_free;
409 }
dbcc3475
JS
410
411 spin_lock_init(&psc_dma->lock);
0827d6ba 412 mutex_init(&psc_dma->mutex);
dbcc3475
JS
413 psc_dma->id = be32_to_cpu(*prop);
414 psc_dma->irq = irq;
415 psc_dma->psc_regs = regs;
416 psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
417 psc_dma->dev = &op->dev;
418 psc_dma->playback.psc_dma = psc_dma;
419 psc_dma->capture.psc_dma = psc_dma;
420 snprintf(psc_dma->name, sizeof psc_dma->name, "PSC%u", psc_dma->id);
421
422 /* Find the address of the fifo data registers and setup the
423 * DMA tasks */
424 fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
425 psc_dma->capture.bcom_task =
426 bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
427 psc_dma->playback.bcom_task =
428 bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
429 if (!psc_dma->capture.bcom_task ||
430 !psc_dma->playback.bcom_task) {
431 dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
33d7f778
JL
432 ret = -ENODEV;
433 goto out_free;
dbcc3475
JS
434 }
435
436 /* Disable all interrupts and reset the PSC */
437 out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
438 /* reset receiver */
439 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
440 /* reset transmitter */
441 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
442 /* reset error */
443 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
444 /* reset mode */
445 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
446
447 /* Set up mode register;
448 * First write: RxRdy (FIFO Alarm) generates rx FIFO irq
449 * Second write: register Normal mode for non loopback
450 */
451 out_8(&psc_dma->psc_regs->mode, 0);
452 out_8(&psc_dma->psc_regs->mode, 0);
453
454 /* Set the TX and RX fifo alarm thresholds */
455 out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
456 out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
457 out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
458 out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
459
460 /* Lookup the IRQ numbers */
461 psc_dma->playback.irq =
462 bcom_get_task_irq(psc_dma->playback.bcom_task);
463 psc_dma->capture.irq =
464 bcom_get_task_irq(psc_dma->capture.bcom_task);
465
466 rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
467 "psc-dma-status", psc_dma);
a68cc8da 468 rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED,
dbcc3475 469 "psc-dma-capture", &psc_dma->capture);
a68cc8da 470 rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED,
dbcc3475
JS
471 "psc-dma-playback", &psc_dma->playback);
472 if (rc) {
33d7f778
JL
473 ret = -ENODEV;
474 goto out_irq;
dbcc3475 475 }
89dd0842 476
dbcc3475
JS
477 /* Save what we've done so it can be found again later */
478 dev_set_drvdata(&op->dev, psc_dma);
479
480 /* Tell the ASoC OF helpers about it */
f0fba2ad 481 return snd_soc_register_platform(&op->dev, &mpc5200_audio_dma_platform);
33d7f778
JL
482out_irq:
483 free_irq(psc_dma->irq, psc_dma);
484 free_irq(psc_dma->capture.irq, &psc_dma->capture);
485 free_irq(psc_dma->playback.irq, &psc_dma->playback);
486out_free:
487 kfree(psc_dma);
488out_unmap:
489 iounmap(regs);
490 return ret;
dbcc3475 491}
f515b673 492EXPORT_SYMBOL_GPL(mpc5200_audio_dma_create);
dbcc3475 493
f515b673 494int mpc5200_audio_dma_destroy(struct platform_device *op)
dbcc3475
JS
495{
496 struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
497
498 dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
499
f0fba2ad 500 snd_soc_unregister_platform(&op->dev);
dbcc3475
JS
501
502 bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
503 bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
504
505 /* Release irqs */
506 free_irq(psc_dma->irq, psc_dma);
507 free_irq(psc_dma->capture.irq, &psc_dma->capture);
508 free_irq(psc_dma->playback.irq, &psc_dma->playback);
509
510 iounmap(psc_dma->psc_regs);
511 kfree(psc_dma);
512 dev_set_drvdata(&op->dev, NULL);
513
514 return 0;
515}
f515b673 516EXPORT_SYMBOL_GPL(mpc5200_audio_dma_destroy);
dbcc3475
JS
517
518MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
519MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
520MODULE_LICENSE("GPL");
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