ASoC: imx-audmux: remove null check of audmux_base in audmux_read_file
[deliverable/linux.git] / sound / soc / fsl / mpc5200_dma.c
CommitLineData
89dd0842
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1/*
2 * Freescale MPC5200 PSC DMA
3 * ALSA SoC Platform driver
4 *
5 * Copyright (C) 2008 Secret Lab Technologies Ltd.
dbcc3475 6 * Copyright (C) 2009 Jon Smirl, Digispeaker
89dd0842
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7 */
8
89dd0842 9#include <linux/module.h>
89dd0842 10#include <linux/of_device.h>
07a38b1b 11#include <linux/dma-mapping.h>
5a0e3ad6 12#include <linux/slab.h>
f0fba2ad 13#include <linux/of_platform.h>
89dd0842 14
89dd0842 15#include <sound/soc.h>
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16
17#include <sysdev/bestcomm/bestcomm.h>
18#include <sysdev/bestcomm/gen_bd.h>
19#include <asm/mpc52xx_psc.h>
20
21#include "mpc5200_dma.h"
22
89dd0842
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23/*
24 * Interrupt handlers
25 */
cebe7767 26static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
89dd0842 27{
cebe7767
JS
28 struct psc_dma *psc_dma = _psc_dma;
29 struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
89dd0842
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30 u16 isr;
31
32 isr = in_be16(&regs->mpc52xx_psc_isr);
33
34 /* Playback underrun error */
cebe7767
JS
35 if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
36 psc_dma->stats.underrun_count++;
89dd0842
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37
38 /* Capture overrun error */
cebe7767
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39 if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
40 psc_dma->stats.overrun_count++;
89dd0842 41
dbcc3475 42 out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
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43
44 return IRQ_HANDLED;
45}
46
47/**
cebe7767 48 * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
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49 * @s: pointer to stream private data structure
50 *
51 * Enqueues another audio period buffer into the bestcomm queue.
52 *
53 * Note: The routine must only be called when there is space available in
54 * the queue. Otherwise the enqueue will fail and the audio ring buffer
55 * will get out of sync
56 */
cebe7767 57static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
89dd0842
JS
58{
59 struct bcom_bd *bd;
60
61 /* Prepare and enqueue the next buffer descriptor */
62 bd = bcom_prepare_next_buffer(s->bcom_task);
63 bd->status = s->period_bytes;
8f159d72 64 bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
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65 bcom_submit_next_buffer(s->bcom_task, NULL);
66
67 /* Update for next period */
8f159d72 68 s->period_next = (s->period_next + 1) % s->runtime->periods;
89dd0842
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69}
70
71/* Bestcomm DMA irq handler */
a68cc8da 72static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream)
89dd0842 73{
dbcc3475 74 struct psc_dma_stream *s = _psc_dma_stream;
89dd0842 75
dbcc3475
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76 spin_lock(&s->psc_dma->lock);
77 /* For each finished period, dequeue the completed period buffer
78 * and enqueue a new one in it's place. */
79 while (bcom_buffer_done(s->bcom_task)) {
80 bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
89dd0842 81
8f159d72 82 s->period_current = (s->period_current+1) % s->runtime->periods;
c4878274 83 s->period_count++;
dbcc3475
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84
85 psc_dma_bcom_enqueue_next_buffer(s);
89dd0842 86 }
dbcc3475 87 spin_unlock(&s->psc_dma->lock);
89dd0842 88
dbcc3475
JS
89 /* If the stream is active, then also inform the PCM middle layer
90 * of the period finished event. */
91 if (s->active)
92 snd_pcm_period_elapsed(s->stream);
93
94 return IRQ_HANDLED;
89dd0842
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95}
96
dbcc3475 97static int psc_dma_hw_free(struct snd_pcm_substream *substream)
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98{
99 snd_pcm_set_runtime_buffer(substream, NULL);
100 return 0;
101}
102
103/**
cebe7767 104 * psc_dma_trigger: start and stop the DMA transfer.
89dd0842
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105 *
106 * This function is called by ALSA to start, stop, pause, and resume the DMA
107 * transfer of data.
108 */
dbcc3475 109static int psc_dma_trigger(struct snd_pcm_substream *substream, int cmd)
89dd0842
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110{
111 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 112 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
89dd0842 113 struct snd_pcm_runtime *runtime = substream->runtime;
1d8222e8 114 struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
cebe7767 115 struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
89dd0842 116 u16 imr;
89dd0842 117 unsigned long flags;
dbcc3475 118 int i;
89dd0842 119
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120 switch (cmd) {
121 case SNDRV_PCM_TRIGGER_START:
c4878274
GL
122 dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n",
123 substream->pstr->stream, runtime->frame_bits,
124 (int)runtime->period_size, runtime->periods);
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125 s->period_bytes = frames_to_bytes(runtime,
126 runtime->period_size);
8f159d72
GL
127 s->period_next = 0;
128 s->period_current = 0;
89dd0842 129 s->active = 1;
c4878274 130 s->period_count = 0;
dbcc3475 131 s->runtime = runtime;
dbcc3475
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132
133 /* Fill up the bestcomm bd queue and enable DMA.
134 * This will begin filling the PSC's fifo.
135 */
136 spin_lock_irqsave(&psc_dma->lock, flags);
137
d56b6eb6 138 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
dbcc3475 139 bcom_gen_bd_rx_reset(s->bcom_task);
d56b6eb6 140 else
dbcc3475 141 bcom_gen_bd_tx_reset(s->bcom_task);
d56b6eb6
GL
142
143 for (i = 0; i < runtime->periods; i++)
144 if (!bcom_queue_full(s->bcom_task))
145 psc_dma_bcom_enqueue_next_buffer(s);
89dd0842 146
89dd0842 147 bcom_enable(s->bcom_task);
cebe7767 148 spin_unlock_irqrestore(&psc_dma->lock, flags);
89dd0842 149
dbcc3475
JS
150 out_8(&regs->command, MPC52xx_PSC_RST_ERR_STAT);
151
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152 break;
153
154 case SNDRV_PCM_TRIGGER_STOP:
c4878274
GL
155 dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n",
156 substream->pstr->stream, s->period_count);
89dd0842 157 s->active = 0;
89dd0842 158
dbcc3475 159 spin_lock_irqsave(&psc_dma->lock, flags);
89dd0842 160 bcom_disable(s->bcom_task);
dbcc3475
JS
161 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
162 bcom_gen_bd_rx_reset(s->bcom_task);
163 else
164 bcom_gen_bd_tx_reset(s->bcom_task);
165 spin_unlock_irqrestore(&psc_dma->lock, flags);
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166
167 break;
168
169 default:
c4878274
GL
170 dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n",
171 substream->pstr->stream, cmd);
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172 return -EINVAL;
173 }
174
175 /* Update interrupt enable settings */
176 imr = 0;
cebe7767 177 if (psc_dma->playback.active)
89dd0842 178 imr |= MPC52xx_PSC_IMR_TXEMP;
cebe7767 179 if (psc_dma->capture.active)
89dd0842 180 imr |= MPC52xx_PSC_IMR_ORERR;
dbcc3475 181 out_be16(&regs->isr_imr.imr, psc_dma->imr | imr);
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182
183 return 0;
184}
185
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186
187/* ---------------------------------------------------------------------
188 * The PSC DMA 'ASoC platform' driver
189 *
190 * Can be referenced by an 'ASoC machine' driver
191 * This driver only deals with the audio bus; it doesn't have any
192 * interaction with the attached codec
193 */
194
dbcc3475 195static const struct snd_pcm_hardware psc_dma_hardware = {
89dd0842
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196 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
197 SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
198 SNDRV_PCM_INFO_BATCH,
199 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
dbcc3475 200 SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
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201 .rate_min = 8000,
202 .rate_max = 48000,
dbcc3475 203 .channels_min = 1,
89dd0842
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204 .channels_max = 2,
205 .period_bytes_max = 1024 * 1024,
206 .period_bytes_min = 32,
207 .periods_min = 2,
208 .periods_max = 256,
209 .buffer_bytes_max = 2 * 1024 * 1024,
dbcc3475 210 .fifo_size = 512,
89dd0842
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211};
212
dbcc3475 213static int psc_dma_open(struct snd_pcm_substream *substream)
89dd0842 214{
dbcc3475 215 struct snd_pcm_runtime *runtime = substream->runtime;
89dd0842 216 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 217 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
cebe7767 218 struct psc_dma_stream *s;
dbcc3475 219 int rc;
89dd0842 220
dbcc3475 221 dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
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222
223 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 224 s = &psc_dma->capture;
89dd0842 225 else
cebe7767 226 s = &psc_dma->playback;
89dd0842 227
dbcc3475
JS
228 snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
229
230 rc = snd_pcm_hw_constraint_integer(runtime,
231 SNDRV_PCM_HW_PARAM_PERIODS);
232 if (rc < 0) {
233 dev_err(substream->pcm->card->dev, "invalid buffer size\n");
234 return rc;
235 }
89dd0842
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236
237 s->stream = substream;
238 return 0;
239}
240
dbcc3475 241static int psc_dma_close(struct snd_pcm_substream *substream)
89dd0842
JS
242{
243 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 244 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
cebe7767 245 struct psc_dma_stream *s;
89dd0842 246
dbcc3475 247 dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
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248
249 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 250 s = &psc_dma->capture;
89dd0842 251 else
cebe7767 252 s = &psc_dma->playback;
89dd0842 253
dbcc3475
JS
254 if (!psc_dma->playback.active &&
255 !psc_dma->capture.active) {
256
257 /* Disable all interrupts and reset the PSC */
258 out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
259 out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
260 }
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261 s->stream = NULL;
262 return 0;
263}
264
265static snd_pcm_uframes_t
dbcc3475 266psc_dma_pointer(struct snd_pcm_substream *substream)
89dd0842
JS
267{
268 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 269 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
cebe7767 270 struct psc_dma_stream *s;
89dd0842
JS
271 dma_addr_t count;
272
273 if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
cebe7767 274 s = &psc_dma->capture;
89dd0842 275 else
cebe7767 276 s = &psc_dma->playback;
89dd0842 277
8f159d72 278 count = s->period_current * s->period_bytes;
89dd0842
JS
279
280 return bytes_to_frames(substream->runtime, count);
281}
282
dbcc3475
JS
283static int
284psc_dma_hw_params(struct snd_pcm_substream *substream,
285 struct snd_pcm_hw_params *params)
286{
287 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
288
289 return 0;
290}
291
292static struct snd_pcm_ops psc_dma_ops = {
293 .open = psc_dma_open,
294 .close = psc_dma_close,
295 .hw_free = psc_dma_hw_free,
89dd0842 296 .ioctl = snd_pcm_lib_ioctl,
dbcc3475
JS
297 .pointer = psc_dma_pointer,
298 .trigger = psc_dma_trigger,
299 .hw_params = psc_dma_hw_params,
89dd0842
JS
300};
301
350e16d5 302static u64 psc_dma_dmamask = DMA_BIT_MASK(32);
552d1ef6 303static int psc_dma_new(struct snd_soc_pcm_runtime *rtd)
89dd0842 304{
552d1ef6
LG
305 struct snd_card *card = rtd->card->snd_card;
306 struct snd_soc_dai *dai = rtd->cpu_dai;
307 struct snd_pcm *pcm = rtd->pcm;
f0fba2ad 308 struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai);
dbcc3475 309 size_t size = psc_dma_hardware.buffer_bytes_max;
89dd0842
JS
310 int rc = 0;
311
f0fba2ad 312 dev_dbg(rtd->platform->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
89dd0842
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313 card, dai, pcm);
314
315 if (!card->dev->dma_mask)
dbcc3475 316 card->dev->dma_mask = &psc_dma_dmamask;
89dd0842 317 if (!card->dev->coherent_dma_mask)
350e16d5 318 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
89dd0842 319
6296914c 320 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
dbcc3475 321 rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
6296914c 322 size, &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
89dd0842
JS
323 if (rc)
324 goto playback_alloc_err;
325 }
326
6296914c 327 if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
dbcc3475 328 rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
6296914c 329 size, &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer);
89dd0842
JS
330 if (rc)
331 goto capture_alloc_err;
332 }
333
f0fba2ad
LG
334 if (rtd->codec->ac97)
335 rtd->codec->ac97->private_data = psc_dma;
dbcc3475 336
89dd0842
JS
337 return 0;
338
339 capture_alloc_err:
6296914c
JE
340 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream)
341 snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
dbcc3475 342
89dd0842
JS
343 playback_alloc_err:
344 dev_err(card->dev, "Cannot allocate buffer(s)\n");
dbcc3475 345
89dd0842
JS
346 return -ENOMEM;
347}
348
dbcc3475 349static void psc_dma_free(struct snd_pcm *pcm)
89dd0842
JS
350{
351 struct snd_soc_pcm_runtime *rtd = pcm->private_data;
352 struct snd_pcm_substream *substream;
353 int stream;
354
f0fba2ad 355 dev_dbg(rtd->platform->dev, "psc_dma_free(pcm=%p)\n", pcm);
89dd0842
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356
357 for (stream = 0; stream < 2; stream++) {
358 substream = pcm->streams[stream].substream;
359 if (substream) {
360 snd_dma_free_pages(&substream->dma_buffer);
361 substream->dma_buffer.area = NULL;
362 substream->dma_buffer.addr = 0;
363 }
364 }
365}
366
f0fba2ad
LG
367static struct snd_soc_platform_driver mpc5200_audio_dma_platform = {
368 .ops = &psc_dma_ops,
dbcc3475
JS
369 .pcm_new = &psc_dma_new,
370 .pcm_free = &psc_dma_free,
89dd0842 371};
dbcc3475 372
3bdf28fe 373static int mpc5200_hpcd_probe(struct platform_device *op)
dbcc3475
JS
374{
375 phys_addr_t fifo;
376 struct psc_dma *psc_dma;
377 struct resource res;
378 int size, irq, rc;
379 const __be32 *prop;
380 void __iomem *regs;
33d7f778 381 int ret;
dbcc3475
JS
382
383 /* Fetch the registers and IRQ of the PSC */
61c7a080
GL
384 irq = irq_of_parse_and_map(op->dev.of_node, 0);
385 if (of_address_to_resource(op->dev.of_node, 0, &res)) {
dbcc3475
JS
386 dev_err(&op->dev, "Missing reg property\n");
387 return -ENODEV;
388 }
28f65c11 389 regs = ioremap(res.start, resource_size(&res));
dbcc3475
JS
390 if (!regs) {
391 dev_err(&op->dev, "Could not map registers\n");
392 return -ENODEV;
393 }
394
395 /* Allocate and initialize the driver private data */
396 psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
397 if (!psc_dma) {
33d7f778
JL
398 ret = -ENOMEM;
399 goto out_unmap;
dbcc3475
JS
400 }
401
402 /* Get the PSC ID */
61c7a080 403 prop = of_get_property(op->dev.of_node, "cell-index", &size);
33d7f778
JL
404 if (!prop || size < sizeof *prop) {
405 ret = -ENODEV;
406 goto out_free;
407 }
dbcc3475
JS
408
409 spin_lock_init(&psc_dma->lock);
0827d6ba 410 mutex_init(&psc_dma->mutex);
dbcc3475
JS
411 psc_dma->id = be32_to_cpu(*prop);
412 psc_dma->irq = irq;
413 psc_dma->psc_regs = regs;
414 psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
415 psc_dma->dev = &op->dev;
416 psc_dma->playback.psc_dma = psc_dma;
417 psc_dma->capture.psc_dma = psc_dma;
418 snprintf(psc_dma->name, sizeof psc_dma->name, "PSC%u", psc_dma->id);
419
420 /* Find the address of the fifo data registers and setup the
421 * DMA tasks */
422 fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
423 psc_dma->capture.bcom_task =
424 bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
425 psc_dma->playback.bcom_task =
426 bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
427 if (!psc_dma->capture.bcom_task ||
428 !psc_dma->playback.bcom_task) {
429 dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
33d7f778
JL
430 ret = -ENODEV;
431 goto out_free;
dbcc3475
JS
432 }
433
434 /* Disable all interrupts and reset the PSC */
435 out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
436 /* reset receiver */
437 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
438 /* reset transmitter */
439 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
440 /* reset error */
441 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
442 /* reset mode */
443 out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
444
445 /* Set up mode register;
446 * First write: RxRdy (FIFO Alarm) generates rx FIFO irq
447 * Second write: register Normal mode for non loopback
448 */
449 out_8(&psc_dma->psc_regs->mode, 0);
450 out_8(&psc_dma->psc_regs->mode, 0);
451
452 /* Set the TX and RX fifo alarm thresholds */
453 out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
454 out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
455 out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
456 out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
457
458 /* Lookup the IRQ numbers */
459 psc_dma->playback.irq =
460 bcom_get_task_irq(psc_dma->playback.bcom_task);
461 psc_dma->capture.irq =
462 bcom_get_task_irq(psc_dma->capture.bcom_task);
463
464 rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
465 "psc-dma-status", psc_dma);
a68cc8da 466 rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED,
dbcc3475 467 "psc-dma-capture", &psc_dma->capture);
a68cc8da 468 rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED,
dbcc3475
JS
469 "psc-dma-playback", &psc_dma->playback);
470 if (rc) {
33d7f778
JL
471 ret = -ENODEV;
472 goto out_irq;
dbcc3475 473 }
89dd0842 474
dbcc3475
JS
475 /* Save what we've done so it can be found again later */
476 dev_set_drvdata(&op->dev, psc_dma);
477
478 /* Tell the ASoC OF helpers about it */
f0fba2ad 479 return snd_soc_register_platform(&op->dev, &mpc5200_audio_dma_platform);
33d7f778
JL
480out_irq:
481 free_irq(psc_dma->irq, psc_dma);
482 free_irq(psc_dma->capture.irq, &psc_dma->capture);
483 free_irq(psc_dma->playback.irq, &psc_dma->playback);
484out_free:
485 kfree(psc_dma);
486out_unmap:
487 iounmap(regs);
488 return ret;
dbcc3475 489}
dbcc3475 490
3bdf28fe 491static int mpc5200_hpcd_remove(struct platform_device *op)
dbcc3475
JS
492{
493 struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
494
495 dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
496
f0fba2ad 497 snd_soc_unregister_platform(&op->dev);
dbcc3475
JS
498
499 bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
500 bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
501
502 /* Release irqs */
503 free_irq(psc_dma->irq, psc_dma);
504 free_irq(psc_dma->capture.irq, &psc_dma->capture);
505 free_irq(psc_dma->playback.irq, &psc_dma->playback);
506
507 iounmap(psc_dma->psc_regs);
508 kfree(psc_dma);
509 dev_set_drvdata(&op->dev, NULL);
510
511 return 0;
512}
f0fba2ad
LG
513
514static struct of_device_id mpc5200_hpcd_match[] = {
f07eb223 515 { .compatible = "fsl,mpc5200-pcm", },
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LG
516 {}
517};
518MODULE_DEVICE_TABLE(of, mpc5200_hpcd_match);
519
f07eb223 520static struct platform_driver mpc5200_hpcd_of_driver = {
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521 .probe = mpc5200_hpcd_probe,
522 .remove = mpc5200_hpcd_remove,
3bdf28fe 523 .driver = {
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GL
524 .owner = THIS_MODULE,
525 .name = "mpc5200-pcm-audio",
526 .of_match_table = mpc5200_hpcd_match,
527 }
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528};
529
ba0a7e02 530module_platform_driver(mpc5200_hpcd_of_driver);
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531
532MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
533MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
534MODULE_LICENSE("GPL");
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