[deliverable/linux.git] / sound / soc / fsl / mpc5200_psc_ac97.c

/*
 * linux/sound/mpc5200-ac97.c -- AC97 support for the Freescale MPC52xx chip.
 *
 * Copyright (C) 2009 Jon Smirl, Digispeaker
 * Author: Jon Smirl <jonsmirl@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/delay.h>

#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include <asm/time.h>
#include <asm/delay.h>
#include <asm/mpc52xx.h>
#include <asm/mpc52xx_psc.h>

#include "mpc5200_dma.h"
#include "mpc5200_psc_ac97.h"

#define DRV_NAME "mpc5200-psc-ac97"

/* ALSA only supports a single AC97 device so static is recommend here */
static struct psc_dma *psc_dma;

static unsigned short psc_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
{
	int status;
	unsigned int val;

	mutex_lock(&psc_dma->mutex);

	/* Wait for command send status zero = ready */
	status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
				MPC52xx_PSC_SR_CMDSEND), 100, 0);
	if (status == 0) {
		pr_err("timeout on ac97 bus (rdy)\n");
		mutex_unlock(&psc_dma->mutex);
		return -ENODEV;
	}

	/* Force clear the data valid bit */
	in_be32(&psc_dma->psc_regs->ac97_data);

	/* Send the read */
	out_be32(&psc_dma->psc_regs->ac97_cmd, (1<<31) | ((reg & 0x7f) << 24));

	/* Wait for the answer */
	status = spin_event_timeout((in_be16(&psc_dma->psc_regs->sr_csr.status) &
				MPC52xx_PSC_SR_DATA_VAL), 100, 0);
	if (status == 0) {
		pr_err("timeout on ac97 read (val) %x\n",
				in_be16(&psc_dma->psc_regs->sr_csr.status));
		mutex_unlock(&psc_dma->mutex);
		return -ENODEV;
	}
	/* Get the data */
	val = in_be32(&psc_dma->psc_regs->ac97_data);
	if (((val >> 24) & 0x7f) != reg) {
		pr_err("reg echo error on ac97 read\n");
		mutex_unlock(&psc_dma->mutex);
		return -ENODEV;
	}
	val = (val >> 8) & 0xffff;

	mutex_unlock(&psc_dma->mutex);
	return (unsigned short) val;
}

static void psc_ac97_write(struct snd_ac97 *ac97,
				unsigned short reg, unsigned short val)
{
	int status;

	mutex_lock(&psc_dma->mutex);

	/* Wait for command status zero = ready */
	status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
				MPC52xx_PSC_SR_CMDSEND), 100, 0);
	if (status == 0) {
		pr_err("timeout on ac97 bus (write)\n");
		goto out;
	}
	/* Write data */
	out_be32(&psc_dma->psc_regs->ac97_cmd,
			((reg & 0x7f) << 24) | (val << 8));

 out:
	mutex_unlock(&psc_dma->mutex);
}

static void psc_ac97_warm_reset(struct snd_ac97 *ac97)
{
	struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;

	mutex_lock(&psc_dma->mutex);

	out_be32(&regs->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_AWR);
	udelay(3);
	out_be32(&regs->sicr, psc_dma->sicr);

	mutex_unlock(&psc_dma->mutex);
}

static void psc_ac97_cold_reset(struct snd_ac97 *ac97)
{
	struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;

	mutex_lock(&psc_dma->mutex);
	dev_dbg(psc_dma->dev, "cold reset\n");

	mpc5200_psc_ac97_gpio_reset(psc_dma->id);

	/* Notify the PSC that a reset has occurred */
	out_be32(&regs->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_ACRB);

	/* Re-enable RX and TX */
	out_8(&regs->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);

	mutex_unlock(&psc_dma->mutex);

	msleep(1);
	psc_ac97_warm_reset(ac97);
}

static struct snd_ac97_bus_ops psc_ac97_ops = {
	.read		= psc_ac97_read,
	.write		= psc_ac97_write,
	.reset		= psc_ac97_cold_reset,
	.warm_reset	= psc_ac97_warm_reset,
};

static int psc_ac97_hw_analog_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *cpu_dai)
{
	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
	struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);

	dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i"
		" periods=%i buffer_size=%i  buffer_bytes=%i channels=%i"
		" rate=%i format=%i\n",
		__func__, substream, params_period_size(params),
		params_period_bytes(params), params_periods(params),
		params_buffer_size(params), params_buffer_bytes(params),
		params_channels(params), params_rate(params),
		params_format(params));

	/* Determine the set of enable bits to turn on */
	s->ac97_slot_bits = (params_channels(params) == 1) ? 0x100 : 0x300;
	if (substream->pstr->stream != SNDRV_PCM_STREAM_CAPTURE)
		s->ac97_slot_bits <<= 16;
	return 0;
}

static int psc_ac97_hw_digital_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *cpu_dai)
{
	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);

	dev_dbg(psc_dma->dev, "%s(substream=%p)\n", __func__, substream);

	if (params_channels(params) == 1)
		out_be32(&psc_dma->psc_regs->ac97_slots, 0x01000000);
	else
		out_be32(&psc_dma->psc_regs->ac97_slots, 0x03000000);

	return 0;
}

static int psc_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
							struct snd_soc_dai *dai)
{
	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(dai);
	struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		dev_dbg(psc_dma->dev, "AC97 START: stream=%i\n",
			substream->pstr->stream);

		/* Set the slot enable bits */
		psc_dma->slots |= s->ac97_slot_bits;
		out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
		break;

	case SNDRV_PCM_TRIGGER_STOP:
		dev_dbg(psc_dma->dev, "AC97 STOP: stream=%i\n",
			substream->pstr->stream);

		/* Clear the slot enable bits */
		psc_dma->slots &= ~(s->ac97_slot_bits);
		out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
		break;
	}
	return 0;
}

static int psc_ac97_probe(struct snd_soc_dai *cpu_dai)
{
	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
	struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;

	/* Go */
	out_8(&regs->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
	return 0;
}

/* ---------------------------------------------------------------------
 * ALSA SoC Bindings
 *
 * - Digital Audio Interface (DAI) template
 * - create/destroy dai hooks
 */

/**
 * psc_ac97_dai_template: template CPU Digital Audio Interface
 */
static const struct snd_soc_dai_ops psc_ac97_analog_ops = {
	.hw_params	= psc_ac97_hw_analog_params,
	.trigger	= psc_ac97_trigger,
};

static const struct snd_soc_dai_ops psc_ac97_digital_ops = {
	.hw_params	= psc_ac97_hw_digital_params,
};

static struct snd_soc_dai_driver psc_ac97_dai[] = {
{
	.name = "mpc5200-psc-ac97.0",
	.bus_control = true,
	.probe	= psc_ac97_probe,
	.playback = {
		.stream_name	= "AC97 Playback",
		.channels_min   = 1,
		.channels_max   = 6,
		.rates          = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S32_BE,
	},
	.capture = {
		.stream_name	= "AC97 Capture",
		.channels_min   = 1,
		.channels_max   = 2,
		.rates          = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S32_BE,
	},
	.ops = &psc_ac97_analog_ops,
},
{
	.name = "mpc5200-psc-ac97.1",
	.bus_control = true,
	.playback = {
		.stream_name	= "AC97 SPDIF",
		.channels_min   = 1,
		.channels_max   = 2,
		.rates          = SNDRV_PCM_RATE_32000 | \
			SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
		.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE,
	},
	.ops = &psc_ac97_digital_ops,
} };

static const struct snd_soc_component_driver psc_ac97_component = {
	.name		= DRV_NAME,
};


/* ---------------------------------------------------------------------
 * OF platform bus binding code:
 * - Probe/remove operations
 * - OF device match table
 */
static int psc_ac97_of_probe(struct platform_device *op)
{
	int rc;
	struct mpc52xx_psc __iomem *regs;

	rc = mpc5200_audio_dma_create(op);
	if (rc != 0)
		return rc;

	rc = snd_soc_set_ac97_ops(&psc_ac97_ops);
	if (rc != 0) {
		dev_err(&op->dev, "Failed to set AC'97 ops: %d\n", rc);
		return rc;
	}

	rc = snd_soc_register_component(&op->dev, &psc_ac97_component,
					psc_ac97_dai, ARRAY_SIZE(psc_ac97_dai));
	if (rc != 0) {
		dev_err(&op->dev, "Failed to register DAI\n");
		return rc;
	}

	psc_dma = dev_get_drvdata(&op->dev);
	regs = psc_dma->psc_regs;

	psc_dma->imr = 0;
	out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);

	/* Configure the serial interface mode to AC97 */
	psc_dma->sicr = MPC52xx_PSC_SICR_SIM_AC97 | MPC52xx_PSC_SICR_ENAC97;
	out_be32(&regs->sicr, psc_dma->sicr);

	/* No slots active */
	out_be32(&regs->ac97_slots, 0x00000000);

	return 0;
}

static int psc_ac97_of_remove(struct platform_device *op)
{
	mpc5200_audio_dma_destroy(op);
	snd_soc_unregister_component(&op->dev);
	snd_soc_set_ac97_ops(NULL);
	return 0;
}

/* Match table for of_platform binding */
static const struct of_device_id psc_ac97_match[] = {
	{ .compatible = "fsl,mpc5200-psc-ac97", },
	{ .compatible = "fsl,mpc5200b-psc-ac97", },
	{}
};
MODULE_DEVICE_TABLE(of, psc_ac97_match);

static struct platform_driver psc_ac97_driver = {
	.probe = psc_ac97_of_probe,
	.remove = psc_ac97_of_remove,
	.driver = {
		.name = "mpc5200-psc-ac97",
		.of_match_table = psc_ac97_match,
	},
};

module_platform_driver(psc_ac97_driver);

MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
MODULE_DESCRIPTION("mpc5200 AC97 module");
MODULE_LICENSE("GPL");
Commit	Line	Data
20d0e152 JS	1	/*
	2	* linux/sound/mpc5200-ac97.c -- AC97 support for the Freescale MPC52xx chip.
	3	*
	4	* Copyright (C) 2009 Jon Smirl, Digispeaker
	5	* Author: Jon Smirl <jonsmirl@gmail.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/of_device.h>
	14	#include <linux/of_platform.h>
ed0f19b2	15	#include <linux/delay.h>
20d0e152 JS	16
	17	#include <sound/pcm.h>
	18	#include <sound/pcm_params.h>
	19	#include <sound/soc.h>
	20
	21	#include <asm/time.h>
	22	#include <asm/delay.h>
949ad0a7	23	#include <asm/mpc52xx.h>
20d0e152 JS	24	#include <asm/mpc52xx_psc.h>
	25
	26	#include "mpc5200_dma.h"
	27	#include "mpc5200_psc_ac97.h"
	28
	29	#define DRV_NAME "mpc5200-psc-ac97"
	30
	31	/* ALSA only supports a single AC97 device so static is recommend here */
	32	static struct psc_dma *psc_dma;
	33
	34	static unsigned short psc_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
	35	{
ea8b27ad	36	int status;
20d0e152 JS	37	unsigned int val;
20d0e152 JS	38
0827d6ba GL	39	mutex_lock(&psc_dma->mutex);
0827d6ba GL	40
20d0e152	41	/* Wait for command send status zero = ready */
ea8b27ad JS	42	status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
	43	MPC52xx_PSC_SR_CMDSEND), 100, 0);
	44	if (status == 0) {
20d0e152	45	pr_err("timeout on ac97 bus (rdy)\n");
0827d6ba	46	mutex_unlock(&psc_dma->mutex);
20d0e152 JS	47	return -ENODEV;
20d0e152 JS	48	}
07573534 GL	49
	50	/* Force clear the data valid bit */
	51	in_be32(&psc_dma->psc_regs->ac97_data);
	52
20d0e152 JS	53	/* Send the read */
	54	out_be32(&psc_dma->psc_regs->ac97_cmd, (1<<31) \| ((reg & 0x7f) << 24));
	55
	56	/* Wait for the answer */
ea8b27ad JS	57	status = spin_event_timeout((in_be16(&psc_dma->psc_regs->sr_csr.status) &
	58	MPC52xx_PSC_SR_DATA_VAL), 100, 0);
	59	if (status == 0) {
20d0e152 JS	60	pr_err("timeout on ac97 read (val) %x\n",
20d0e152 JS	61	in_be16(&psc_dma->psc_regs->sr_csr.status));
0827d6ba	62	mutex_unlock(&psc_dma->mutex);
20d0e152 JS	63	return -ENODEV;
	64	}
	65	/* Get the data */
	66	val = in_be32(&psc_dma->psc_regs->ac97_data);
	67	if (((val >> 24) & 0x7f) != reg) {
	68	pr_err("reg echo error on ac97 read\n");
0827d6ba	69	mutex_unlock(&psc_dma->mutex);
20d0e152 JS	70	return -ENODEV;
	71	}
	72	val = (val >> 8) & 0xffff;
	73
0827d6ba	74	mutex_unlock(&psc_dma->mutex);
20d0e152 JS	75	return (unsigned short) val;
	76	}
	77
	78	static void psc_ac97_write(struct snd_ac97 *ac97,
	79	unsigned short reg, unsigned short val)
	80	{
ea8b27ad	81	int status;
20d0e152	82
0827d6ba GL	83	mutex_lock(&psc_dma->mutex);
0827d6ba GL	84
20d0e152	85	/* Wait for command status zero = ready */
ea8b27ad JS	86	status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
	87	MPC52xx_PSC_SR_CMDSEND), 100, 0);
	88	if (status == 0) {
20d0e152	89	pr_err("timeout on ac97 bus (write)\n");
0827d6ba	90	goto out;
20d0e152 JS	91	}
	92	/* Write data */
	93	out_be32(&psc_dma->psc_regs->ac97_cmd,
	94	((reg & 0x7f) << 24) \| (val << 8));
0827d6ba GL	95
	96	out:
	97	mutex_unlock(&psc_dma->mutex);
20d0e152 JS	98	}
	99
	100	static void psc_ac97_warm_reset(struct snd_ac97 *ac97)
	101	{
20d0e152 JS	102	struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
20d0e152 JS	103
949ad0a7 EM	104	mutex_lock(&psc_dma->mutex);
949ad0a7 EM	105
20d0e152	106	out_be32(&regs->sicr, psc_dma->sicr \| MPC52xx_PSC_SICR_AWR);
ea8b27ad	107	udelay(3);
20d0e152	108	out_be32(&regs->sicr, psc_dma->sicr);
949ad0a7 EM	109
949ad0a7 EM	110	mutex_unlock(&psc_dma->mutex);
20d0e152 JS	111	}
	112
	113	static void psc_ac97_cold_reset(struct snd_ac97 *ac97)
	114	{
20d0e152 JS	115	struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
20d0e152 JS	116
949ad0a7 EM	117	mutex_lock(&psc_dma->mutex);
	118	dev_dbg(psc_dma->dev, "cold reset\n");
	119
	120	mpc5200_psc_ac97_gpio_reset(psc_dma->id);
	121
	122	/* Notify the PSC that a reset has occurred */
	123	out_be32(&regs->sicr, psc_dma->sicr \| MPC52xx_PSC_SICR_ACRB);
	124
	125	/* Re-enable RX and TX */
	126	out_8(&regs->command, MPC52xx_PSC_TX_ENABLE \| MPC52xx_PSC_RX_ENABLE);
	127
	128	mutex_unlock(&psc_dma->mutex);
	129
ed0f19b2	130	msleep(1);
20d0e152 JS	131	psc_ac97_warm_reset(ac97);
	132	}
	133
b047e1cc	134	static struct snd_ac97_bus_ops psc_ac97_ops = {
20d0e152 JS	135	.read = psc_ac97_read,
	136	.write = psc_ac97_write,
	137	.reset = psc_ac97_cold_reset,
	138	.warm_reset = psc_ac97_warm_reset,
	139	};
20d0e152 JS	140
	141	static int psc_ac97_hw_analog_params(struct snd_pcm_substream *substream,
	142	struct snd_pcm_hw_params *params,
	143	struct snd_soc_dai *cpu_dai)
	144	{
f0fba2ad	145	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
c939e5c8	146	struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
20d0e152 JS	147
	148	dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i"
	149	" periods=%i buffer_size=%i buffer_bytes=%i channels=%i"
	150	" rate=%i format=%i\n",
	151	__func__, substream, params_period_size(params),
	152	params_period_bytes(params), params_periods(params),
	153	params_buffer_size(params), params_buffer_bytes(params),
	154	params_channels(params), params_rate(params),
	155	params_format(params));
	156
c939e5c8 GL	157	/* Determine the set of enable bits to turn on */
	158	s->ac97_slot_bits = (params_channels(params) == 1) ? 0x100 : 0x300;
	159	if (substream->pstr->stream != SNDRV_PCM_STREAM_CAPTURE)
	160	s->ac97_slot_bits <<= 16;
20d0e152 JS	161	return 0;
	162	}
	163
	164	static int psc_ac97_hw_digital_params(struct snd_pcm_substream *substream,
	165	struct snd_pcm_hw_params *params,
	166	struct snd_soc_dai *cpu_dai)
	167	{
f0fba2ad	168	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
20d0e152	169
c939e5c8 GL	170	dev_dbg(psc_dma->dev, "%s(substream=%p)\n", __func__, substream);
c939e5c8 GL	171
20d0e152 JS	172	if (params_channels(params) == 1)
	173	out_be32(&psc_dma->psc_regs->ac97_slots, 0x01000000);
	174	else
	175	out_be32(&psc_dma->psc_regs->ac97_slots, 0x03000000);
	176
	177	return 0;
	178	}
	179
	180	static int psc_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
	181	struct snd_soc_dai *dai)
	182	{
f0fba2ad	183	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(dai);
c939e5c8	184	struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
20d0e152 JS	185
20d0e152 JS	186	switch (cmd) {
c939e5c8 GL	187	case SNDRV_PCM_TRIGGER_START:
	188	dev_dbg(psc_dma->dev, "AC97 START: stream=%i\n",
	189	substream->pstr->stream);
	190
	191	/* Set the slot enable bits */
	192	psc_dma->slots \|= s->ac97_slot_bits;
	193	out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
	194	break;
	195
20d0e152	196	case SNDRV_PCM_TRIGGER_STOP:
c939e5c8 GL	197	dev_dbg(psc_dma->dev, "AC97 STOP: stream=%i\n",
c939e5c8 GL	198	substream->pstr->stream);
20d0e152	199
c939e5c8 GL	200	/* Clear the slot enable bits */
c939e5c8 GL	201	psc_dma->slots &= ~(s->ac97_slot_bits);
20d0e152 JS	202	out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
	203	break;
	204	}
	205	return 0;
	206	}
	207
f0fba2ad	208	static int psc_ac97_probe(struct snd_soc_dai *cpu_dai)
20d0e152	209	{
f0fba2ad	210	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
20d0e152 JS	211	struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
	212
	213	/* Go */
	214	out_8(&regs->command, MPC52xx_PSC_TX_ENABLE \| MPC52xx_PSC_RX_ENABLE);
	215	return 0;
	216	}
	217
	218	/* ---------------------------------------------------------------------
	219	* ALSA SoC Bindings
	220	*
	221	* - Digital Audio Interface (DAI) template
	222	* - create/destroy dai hooks
	223	*/
	224
	225	/**
	226	* psc_ac97_dai_template: template CPU Digital Audio Interface
	227	*/
85e7652d	228	static const struct snd_soc_dai_ops psc_ac97_analog_ops = {
20d0e152 JS	229	.hw_params = psc_ac97_hw_analog_params,
	230	.trigger = psc_ac97_trigger,
	231	};
	232
85e7652d	233	static const struct snd_soc_dai_ops psc_ac97_digital_ops = {
20d0e152 JS	234	.hw_params = psc_ac97_hw_digital_params,
	235	};
	236
f0fba2ad	237	static struct snd_soc_dai_driver psc_ac97_dai[] = {
20d0e152	238	{
a4f7b70d	239	.name = "mpc5200-psc-ac97.0",
bc263214	240	.bus_control = true,
20d0e152 JS	241	.probe = psc_ac97_probe,
20d0e152 JS	242	.playback = {
a4f7b70d	243	.stream_name = "AC97 Playback",
20d0e152 JS	244	.channels_min = 1,
	245	.channels_max = 6,
	246	.rates = SNDRV_PCM_RATE_8000_48000,
	247	.formats = SNDRV_PCM_FMTBIT_S32_BE,
	248	},
	249	.capture = {
a4f7b70d	250	.stream_name = "AC97 Capture",
20d0e152 JS	251	.channels_min = 1,
	252	.channels_max = 2,
	253	.rates = SNDRV_PCM_RATE_8000_48000,
	254	.formats = SNDRV_PCM_FMTBIT_S32_BE,
	255	},
	256	.ops = &psc_ac97_analog_ops,
	257	},
	258	{
a4f7b70d	259	.name = "mpc5200-psc-ac97.1",
bc263214	260	.bus_control = true,
20d0e152	261	.playback = {
a4f7b70d	262	.stream_name = "AC97 SPDIF",
20d0e152 JS	263	.channels_min = 1,
	264	.channels_max = 2,
	265	.rates = SNDRV_PCM_RATE_32000 \| \
	266	SNDRV_PCM_RATE_44100 \| SNDRV_PCM_RATE_48000,
	267	.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE,
	268	},
	269	.ops = &psc_ac97_digital_ops,
	270	} };
20d0e152	271
f298a0ff KM	272	static const struct snd_soc_component_driver psc_ac97_component = {
	273	.name = DRV_NAME,
	274	};
20d0e152 JS	275
	276
	277	/* ---------------------------------------------------------------------
	278	* OF platform bus binding code:
	279	* - Probe/remove operations
	280	* - OF device match table
	281	*/
a0a3d518	282	static int psc_ac97_of_probe(struct platform_device *op)
20d0e152	283	{
f0fba2ad	284	int rc;
20d0e152 JS	285	struct mpc52xx_psc __iomem *regs;
20d0e152 JS	286
f515b673 EM	287	rc = mpc5200_audio_dma_create(op);
	288	if (rc != 0)
	289	return rc;
	290
b047e1cc MB	291	rc = snd_soc_set_ac97_ops(&psc_ac97_ops);
b047e1cc MB	292	if (rc != 0) {
5af50730	293	dev_err(&op->dev, "Failed to set AC'97 ops: %d\n", rc);
b047e1cc MB	294	return rc;
	295	}
	296
f298a0ff KM	297	rc = snd_soc_register_component(&op->dev, &psc_ac97_component,
f298a0ff KM	298	psc_ac97_dai, ARRAY_SIZE(psc_ac97_dai));
20d0e152 JS	299	if (rc != 0) {
	300	dev_err(&op->dev, "Failed to register DAI\n");
	301	return rc;
	302	}
	303
	304	psc_dma = dev_get_drvdata(&op->dev);
	305	regs = psc_dma->psc_regs;
20d0e152	306
20d0e152 JS	307	psc_dma->imr = 0;
	308	out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
	309
	310	/* Configure the serial interface mode to AC97 */
	311	psc_dma->sicr = MPC52xx_PSC_SICR_SIM_AC97 \| MPC52xx_PSC_SICR_ENAC97;
	312	out_be32(&regs->sicr, psc_dma->sicr);
	313
	314	/* No slots active */
	315	out_be32(&regs->ac97_slots, 0x00000000);
	316
	317	return 0;
	318	}
	319
a0a3d518	320	static int psc_ac97_of_remove(struct platform_device *op)
20d0e152	321	{
f515b673	322	mpc5200_audio_dma_destroy(op);
f298a0ff	323	snd_soc_unregister_component(&op->dev);
b047e1cc	324	snd_soc_set_ac97_ops(NULL);
f0fba2ad	325	return 0;
20d0e152 JS	326	}
	327
	328	/* Match table for of_platform binding */
6ffa84df	329	static const struct of_device_id psc_ac97_match[] = {
20d0e152 JS	330	{ .compatible = "fsl,mpc5200-psc-ac97", },
	331	{ .compatible = "fsl,mpc5200b-psc-ac97", },
	332	{}
	333	};
	334	MODULE_DEVICE_TABLE(of, psc_ac97_match);
	335
f07eb223	336	static struct platform_driver psc_ac97_driver = {
20d0e152	337	.probe = psc_ac97_of_probe,
a0a3d518	338	.remove = psc_ac97_of_remove,
20d0e152 JS	339	.driver = {
20d0e152 JS	340	.name = "mpc5200-psc-ac97",
4018294b	341	.of_match_table = psc_ac97_match,
20d0e152 JS	342	},
	343	};
	344
ba0a7e02	345	module_platform_driver(psc_ac97_driver);
20d0e152 JS	346
	347	MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
	348	MODULE_DESCRIPTION("mpc5200 AC97 module");
	349	MODULE_LICENSE("GPL");
	350