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ASoC: Fix i.MX audio build for i.MX3x
[deliverable/linux.git] / sound / soc / imx / imx-ssi.c
CommitLineData
8380222e
SH		 1/*
2 * imx-ssi.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This code is based on code copyrighted by Freescale,
7 * Liam Girdwood, Javier Martin and probably others.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 *
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developped with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
25 * rate.
26 * Reading and writing AC97 registers is another challange. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
31 *
32 */
33
34#include <linux/clk.h>
35#include <linux/delay.h>
36#include <linux/device.h>
37#include <linux/dma-mapping.h>
38#include <linux/init.h>
39#include <linux/interrupt.h>
40#include <linux/module.h>
41#include <linux/platform_device.h>
42
43#include <sound/core.h>
44#include <sound/initval.h>
45#include <sound/pcm.h>
46#include <sound/pcm_params.h>
47#include <sound/soc.h>
48
49#include <mach/ssi.h>
50#include <mach/hardware.h>
51
52#include "imx-ssi.h"
53
54#define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
55
56/*
57 * SSI Network Mode or TDM slots configuration.
58 * Should only be called when port is inactive (i.e. SSIEN = 0).
59 */
60static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
61 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
62{
63 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
64 u32 sccr;
65
66 sccr = readl(ssi->base + SSI_STCCR);
67 sccr &= ~SSI_STCCR_DC_MASK;
68 sccr |= SSI_STCCR_DC(slots - 1);
69 writel(sccr, ssi->base + SSI_STCCR);
70
71 sccr = readl(ssi->base + SSI_SRCCR);
72 sccr &= ~SSI_STCCR_DC_MASK;
73 sccr |= SSI_STCCR_DC(slots - 1);
74 writel(sccr, ssi->base + SSI_SRCCR);
75
76 writel(tx_mask, ssi->base + SSI_STMSK);
77 writel(rx_mask, ssi->base + SSI_SRMSK);
78
79 return 0;
80}
81
82/*
83 * SSI DAI format configuration.
84 * Should only be called when port is inactive (i.e. SSIEN = 0).
85 * Note: We don't use the I2S modes but instead manually configure the
86 * SSI for I2S because the I2S mode is only a register preset.
87 */
88static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
89{
90 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
91 u32 strcr = 0, scr;
92
93 scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
94
95 /* DAI mode */
96 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
97 case SND_SOC_DAIFMT_I2S:
98 /* data on rising edge of bclk, frame low 1clk before data */
99 strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
100 scr |= SSI_SCR_NET;
101 break;
102 case SND_SOC_DAIFMT_LEFT_J:
103 /* data on rising edge of bclk, frame high with data */
104 strcr |= SSI_STCR_TXBIT0;
105 break;
106 case SND_SOC_DAIFMT_DSP_B:
107 /* data on rising edge of bclk, frame high with data */
108 strcr |= SSI_STCR_TFSL;
109 break;
110 case SND_SOC_DAIFMT_DSP_A:
111 /* data on rising edge of bclk, frame high 1clk before data */
112 strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS;
113 break;
114 }
115
116 /* DAI clock inversion */
117 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
118 case SND_SOC_DAIFMT_IB_IF:
119 strcr |= SSI_STCR_TFSI;
120 strcr &= ~SSI_STCR_TSCKP;
121 break;
122 case SND_SOC_DAIFMT_IB_NF:
123 strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
124 break;
125 case SND_SOC_DAIFMT_NB_IF:
126 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
127 break;
128 case SND_SOC_DAIFMT_NB_NF:
129 strcr &= ~SSI_STCR_TFSI;
130 strcr |= SSI_STCR_TSCKP;
131 break;
132 }
133
134 /* DAI clock master masks */
135 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
136 case SND_SOC_DAIFMT_CBS_CFS:
137 strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
138 break;
139 case SND_SOC_DAIFMT_CBM_CFS:
140 strcr |= SSI_STCR_TFDIR;
141 break;
142 case SND_SOC_DAIFMT_CBS_CFM:
143 strcr |= SSI_STCR_TXDIR;
144 break;
145 }
146
147 strcr |= SSI_STCR_TFEN0;
148
149 writel(strcr, ssi->base + SSI_STCR);
150 writel(strcr, ssi->base + SSI_SRCR);
151 writel(scr, ssi->base + SSI_SCR);
152
153 return 0;
154}
155
156/*
157 * SSI system clock configuration.
158 * Should only be called when port is inactive (i.e. SSIEN = 0).
159 */
160static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
161 int clk_id, unsigned int freq, int dir)
162{
163 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
164 u32 scr;
165
166 scr = readl(ssi->base + SSI_SCR);
167
168 switch (clk_id) {
169 case IMX_SSP_SYS_CLK:
170 if (dir == SND_SOC_CLOCK_OUT)
171 scr |= SSI_SCR_SYS_CLK_EN;
172 else
173 scr &= ~SSI_SCR_SYS_CLK_EN;
174 break;
175 default:
176 return -EINVAL;
177 }
178
179 writel(scr, ssi->base + SSI_SCR);
180
181 return 0;
182}
183
184/*
185 * SSI Clock dividers
186 * Should only be called when port is inactive (i.e. SSIEN = 0).
187 */
188static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
189 int div_id, int div)
190{
191 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
192 u32 stccr, srccr;
193
194 stccr = readl(ssi->base + SSI_STCCR);
195 srccr = readl(ssi->base + SSI_SRCCR);
196
197 switch (div_id) {
198 case IMX_SSI_TX_DIV_2:
199 stccr &= ~SSI_STCCR_DIV2;
200 stccr |= div;
201 break;
202 case IMX_SSI_TX_DIV_PSR:
203 stccr &= ~SSI_STCCR_PSR;
204 stccr |= div;
205 break;
206 case IMX_SSI_TX_DIV_PM:
207 stccr &= ~0xff;
208 stccr |= SSI_STCCR_PM(div);
209 break;
210 case IMX_SSI_RX_DIV_2:
211 stccr &= ~SSI_STCCR_DIV2;
212 stccr |= div;
213 break;
214 case IMX_SSI_RX_DIV_PSR:
215 stccr &= ~SSI_STCCR_PSR;
216 stccr |= div;
217 break;
218 case IMX_SSI_RX_DIV_PM:
219 stccr &= ~0xff;
220 stccr |= SSI_STCCR_PM(div);
221 break;
222 default:
223 return -EINVAL;
224 }
225
226 writel(stccr, ssi->base + SSI_STCCR);
227 writel(srccr, ssi->base + SSI_SRCCR);
228
229 return 0;
230}
231
232/*
233 * Should only be called when port is inactive (i.e. SSIEN = 0),
234 * although can be called multiple times by upper layers.
235 */
236static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
237 struct snd_pcm_hw_params *params,
238 struct snd_soc_dai *cpu_dai)
239{
240 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
241 u32 reg, sccr;
242
243 /* Tx/Rx config */
244 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
245 reg = SSI_STCCR;
246 cpu_dai->dma_data = &ssi->dma_params_tx;
247 } else {
248 reg = SSI_SRCCR;
249 cpu_dai->dma_data = &ssi->dma_params_rx;
250 }
251
252 sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
253
254 /* DAI data (word) size */
255 switch (params_format(params)) {
256 case SNDRV_PCM_FORMAT_S16_LE:
257 sccr |= SSI_SRCCR_WL(16);
258 break;
259 case SNDRV_PCM_FORMAT_S20_3LE:
260 sccr |= SSI_SRCCR_WL(20);
261 break;
262 case SNDRV_PCM_FORMAT_S24_LE:
263 sccr |= SSI_SRCCR_WL(24);
264 break;
265 }
266
267 writel(sccr, ssi->base + reg);
268
269 return 0;
270}
271
272static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
273 struct snd_soc_dai *dai)
274{
275 struct snd_soc_pcm_runtime *rtd = substream->private_data;
276 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
277 struct imx_ssi *ssi = container_of(cpu_dai, struct imx_ssi, dai);
278 unsigned int sier_bits, sier;
279 unsigned int scr;
280
281 scr = readl(ssi->base + SSI_SCR);
282 sier = readl(ssi->base + SSI_SIER);
283
284 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
285 if (ssi->flags & IMX_SSI_DMA)
286 sier_bits = SSI_SIER_TDMAE;
287 else
288 sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
289 } else {
290 if (ssi->flags & IMX_SSI_DMA)
291 sier_bits = SSI_SIER_RDMAE;
292 else
293 sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
294 }
295
296 switch (cmd) {
297 case SNDRV_PCM_TRIGGER_START:
298 case SNDRV_PCM_TRIGGER_RESUME:
299 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
300 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
301 scr |= SSI_SCR_TE;
302 else
303 scr |= SSI_SCR_RE;
304 sier |= sier_bits;
305
306 if (++ssi->enabled == 1)
307 scr |= SSI_SCR_SSIEN;
308
309 break;
310
311 case SNDRV_PCM_TRIGGER_STOP:
312 case SNDRV_PCM_TRIGGER_SUSPEND:
313 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
314 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
315 scr &= ~SSI_SCR_TE;
316 else
317 scr &= ~SSI_SCR_RE;
318 sier &= ~sier_bits;
319
320 if (--ssi->enabled == 0)
321 scr &= ~SSI_SCR_SSIEN;
322
323 break;
324 default:
325 return -EINVAL;
326 }
327
328 if (!(ssi->flags & IMX_SSI_USE_AC97))
329 /* rx/tx are always enabled to access ac97 registers */
330 writel(scr, ssi->base + SSI_SCR);
331
332 writel(sier, ssi->base + SSI_SIER);
333
334 return 0;
335}
336
337static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
338 .hw_params = imx_ssi_hw_params,
339 .set_fmt = imx_ssi_set_dai_fmt,
340 .set_clkdiv = imx_ssi_set_dai_clkdiv,
341 .set_sysclk = imx_ssi_set_dai_sysclk,
342 .set_tdm_slot = imx_ssi_set_dai_tdm_slot,
343 .trigger = imx_ssi_trigger,
344};
345
346static struct snd_soc_dai imx_ssi_dai = {
347 .playback = {
348 .channels_min = 2,
349 .channels_max = 2,
350 .rates = SNDRV_PCM_RATE_8000_96000,
351 .formats = SNDRV_PCM_FMTBIT_S16_LE,
352 },
353 .capture = {
354 .channels_min = 2,
355 .channels_max = 2,
356 .rates = SNDRV_PCM_RATE_8000_96000,
357 .formats = SNDRV_PCM_FMTBIT_S16_LE,
358 },
359 .ops = &imx_ssi_pcm_dai_ops,
360};
361
362int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
363 struct vm_area_struct *vma)
364{
365 struct snd_pcm_runtime *runtime = substream->runtime;
366 int ret;
367
368 ret = dma_mmap_coherent(NULL, vma, runtime->dma_area,
369 runtime->dma_addr, runtime->dma_bytes);
370
371 pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
372 runtime->dma_area,
373 runtime->dma_addr,
374 runtime->dma_bytes);
375 return ret;
376}
377
378static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
379{
380 struct snd_pcm_substream *substream = pcm->streams[stream].substream;
381 struct snd_dma_buffer *buf = &substream->dma_buffer;
382 size_t size = IMX_SSI_DMABUF_SIZE;
383
384 buf->dev.type = SNDRV_DMA_TYPE_DEV;
385 buf->dev.dev = pcm->card->dev;
386 buf->private_data = NULL;
387 buf->area = dma_alloc_writecombine(pcm->card->dev, size,
388 &buf->addr, GFP_KERNEL);
389 if (!buf->area)
390 return -ENOMEM;
391 buf->bytes = size;
392
393 return 0;
394}
395
396static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
397
398int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
399 struct snd_pcm *pcm)
400{
401
402 int ret = 0;
403
404 if (!card->dev->dma_mask)
405 card->dev->dma_mask = &imx_pcm_dmamask;
406 if (!card->dev->coherent_dma_mask)
407 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
408 if (dai->playback.channels_min) {
409 ret = imx_pcm_preallocate_dma_buffer(pcm,
410 SNDRV_PCM_STREAM_PLAYBACK);
411 if (ret)
412 goto out;
413 }
414
415 if (dai->capture.channels_min) {
416 ret = imx_pcm_preallocate_dma_buffer(pcm,
417 SNDRV_PCM_STREAM_CAPTURE);
418 if (ret)
419 goto out;
420 }
421
422out:
423 return ret;
424}
425
426void imx_pcm_free(struct snd_pcm *pcm)
427{
428 struct snd_pcm_substream *substream;
429 struct snd_dma_buffer *buf;
430 int stream;
431
432 for (stream = 0; stream < 2; stream++) {
433 substream = pcm->streams[stream].substream;
434 if (!substream)
435 continue;
436
437 buf = &substream->dma_buffer;
438 if (!buf->area)
439 continue;
440
441 dma_free_writecombine(pcm->card->dev, buf->bytes,
442 buf->area, buf->addr);
443 buf->area = NULL;
444 }
445}
446
447struct snd_soc_platform imx_soc_platform = {
448 .name = "imx-audio",
449};
450EXPORT_SYMBOL_GPL(imx_soc_platform);
451
452static struct snd_soc_dai imx_ac97_dai = {
453 .name = "AC97",
454 .ac97_control = 1,
455 .playback = {
456 .stream_name = "AC97 Playback",
457 .channels_min = 2,
458 .channels_max = 2,
459 .rates = SNDRV_PCM_RATE_48000,
460 .formats = SNDRV_PCM_FMTBIT_S16_LE,
461 },
462 .capture = {
463 .stream_name = "AC97 Capture",
464 .channels_min = 2,
465 .channels_max = 2,
466 .rates = SNDRV_PCM_RATE_48000,
467 .formats = SNDRV_PCM_FMTBIT_S16_LE,
468 },
469 .ops = &imx_ssi_pcm_dai_ops,
470};
471
472static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
473{
474 void __iomem *base = imx_ssi->base;
475
476 writel(0x0, base + SSI_SCR);
477 writel(0x0, base + SSI_STCR);
478 writel(0x0, base + SSI_SRCR);
479
480 writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
481
482 writel(SSI_SFCSR_RFWM0(8) |
483 SSI_SFCSR_TFWM0(8) |
484 SSI_SFCSR_RFWM1(8) |
485 SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
486
487 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
488 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
489
490 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
491 writel(SSI_SOR_WAIT(3), base + SSI_SOR);
492
493 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
494 SSI_SCR_TE | SSI_SCR_RE,
495 base + SSI_SCR);
496
497 writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
498 writel(0xff, base + SSI_SACCDIS);
499 writel(0x300, base + SSI_SACCEN);
500}
501
502static struct imx_ssi *ac97_ssi;
503
504static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
505 unsigned short val)
506{
507 struct imx_ssi *imx_ssi = ac97_ssi;
508 void __iomem *base = imx_ssi->base;
509 unsigned int lreg;
510 unsigned int lval;
511
512 if (reg > 0x7f)
513 return;
514
515 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
516
517 lreg = reg << 12;
518 writel(lreg, base + SSI_SACADD);
519
520 lval = val << 4;
521 writel(lval , base + SSI_SACDAT);
522
523 writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
524 udelay(100);
525}
526
527static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
528 unsigned short reg)
529{
530 struct imx_ssi *imx_ssi = ac97_ssi;
531 void __iomem *base = imx_ssi->base;
532
533 unsigned short val = -1;
534 unsigned int lreg;
535
536 lreg = (reg & 0x7f) << 12 ;
537 writel(lreg, base + SSI_SACADD);
538 writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
539
540 udelay(100);
541
542 val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
543
544 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
545
546 return val;
547}
548
549static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
550{
551 struct imx_ssi *imx_ssi = ac97_ssi;
552
553 if (imx_ssi->ac97_reset)
554 imx_ssi->ac97_reset(ac97);
555}
556
557static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
558{
559 struct imx_ssi *imx_ssi = ac97_ssi;
560
561 if (imx_ssi->ac97_warm_reset)
562 imx_ssi->ac97_warm_reset(ac97);
563}
564
565struct snd_ac97_bus_ops soc_ac97_ops = {
566 .read = imx_ssi_ac97_read,
567 .write = imx_ssi_ac97_write,
568 .reset = imx_ssi_ac97_reset,
569 .warm_reset = imx_ssi_ac97_warm_reset
570};
571EXPORT_SYMBOL_GPL(soc_ac97_ops);
572
573struct snd_soc_dai *imx_ssi_pcm_dai[2];
574EXPORT_SYMBOL_GPL(imx_ssi_pcm_dai);
575
576static int imx_ssi_probe(struct platform_device *pdev)
577{
578 struct resource *res;
579 struct imx_ssi *ssi;
580 struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
581 struct snd_soc_platform *platform;
582 int ret = 0;
583 unsigned int val;
584
585 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
586 if (!ssi)
587 return -ENOMEM;
588
589 if (pdata) {
590 ssi->ac97_reset = pdata->ac97_reset;
591 ssi->ac97_warm_reset = pdata->ac97_warm_reset;
592 ssi->flags = pdata->flags;
593 }
594
595 imx_ssi_pcm_dai[pdev->id] = &ssi->dai;
596
597 ssi->irq = platform_get_irq(pdev, 0);
598
599 ssi->clk = clk_get(&pdev->dev, NULL);
600 if (IS_ERR(ssi->clk)) {
601 ret = PTR_ERR(ssi->clk);
602 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
603 ret);
604 goto failed_clk;
605 }
606 clk_enable(ssi->clk);
607
608 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
609 if (!res) {
610 ret = -ENODEV;
611 goto failed_get_resource;
612 }
613
614 if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
615 dev_err(&pdev->dev, "request_mem_region failed\n");
616 ret = -EBUSY;
617 goto failed_get_resource;
618 }
619
620 ssi->base = ioremap(res->start, resource_size(res));
621 if (!ssi->base) {
622 dev_err(&pdev->dev, "ioremap failed\n");
623 ret = -ENODEV;
624 goto failed_ioremap;
625 }
626
627 if (ssi->flags & IMX_SSI_USE_AC97) {
628 if (ac97_ssi) {
629 ret = -EBUSY;
630 goto failed_ac97;
631 }
632 ac97_ssi = ssi;
633 setup_channel_to_ac97(ssi);
634 memcpy(&ssi->dai, &imx_ac97_dai, sizeof(imx_ac97_dai));
635 } else
636 memcpy(&ssi->dai, &imx_ssi_dai, sizeof(imx_ssi_dai));
637
638 ssi->dai.id = pdev->id;
639 ssi->dai.dev = &pdev->dev;
640 ssi->dai.name = kasprintf(GFP_KERNEL, "imx-ssi.%d", pdev->id);
641
642 writel(0x0, ssi->base + SSI_SIER);
643
644 ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
645 ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;
646
647 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
648 if (res)
649 ssi->dma_params_tx.dma = res->start;
650
651 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
652 if (res)
653 ssi->dma_params_rx.dma = res->start;
654
655 ssi->dai.id = pdev->id;
656 ssi->dai.dev = &pdev->dev;
657 ssi->dai.name = kasprintf(GFP_KERNEL, "imx-ssi.%d", pdev->id);
658
659 if ((cpu_is_mx27() || cpu_is_mx21()) &&
660 !(ssi->flags & IMX_SSI_USE_AC97)) {
661 ssi->flags |= IMX_SSI_DMA;
662 platform = imx_ssi_dma_mx2_init(pdev, ssi);
663 } else
664 platform = imx_ssi_fiq_init(pdev, ssi);
665
666 imx_soc_platform.pcm_ops = platform->pcm_ops;
667 imx_soc_platform.pcm_new = platform->pcm_new;
668 imx_soc_platform.pcm_free = platform->pcm_free;
669
670 val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) |
671 SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
672 writel(val, ssi->base + SSI_SFCSR);
673
674 ret = snd_soc_register_dai(&ssi->dai);
675 if (ret) {
676 dev_err(&pdev->dev, "register DAI failed\n");
677 goto failed_register;
678 }
679
680 platform_set_drvdata(pdev, ssi);
681
682 return 0;
683
684failed_register:
685failed_ac97:
686 iounmap(ssi->base);
687failed_ioremap:
688 release_mem_region(res->start, resource_size(res));
689failed_get_resource:
690 clk_disable(ssi->clk);
691 clk_put(ssi->clk);
692failed_clk:
693 kfree(ssi);
694
695 return ret;
696}
697
698static int __devexit imx_ssi_remove(struct platform_device *pdev)
699{
700 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
701 struct imx_ssi *ssi = platform_get_drvdata(pdev);
702
703 snd_soc_unregister_dai(&ssi->dai);
704
705 if (ssi->flags & IMX_SSI_USE_AC97)
706 ac97_ssi = NULL;
707
708 if (!(ssi->flags & IMX_SSI_DMA))
709 imx_ssi_fiq_exit(pdev, ssi);
710
711 iounmap(ssi->base);
712 release_mem_region(res->start, resource_size(res));
713 clk_disable(ssi->clk);
714 clk_put(ssi->clk);
715 kfree(ssi);
716
717 return 0;
718}
719
720static struct platform_driver imx_ssi_driver = {
721 .probe = imx_ssi_probe,
722 .remove = __devexit_p(imx_ssi_remove),
723
724 .driver = {
725 .name = DRV_NAME,
726 .owner = THIS_MODULE,
727 },
728};
729
730static int __init imx_ssi_init(void)
731{
732 int ret;
733
734 ret = snd_soc_register_platform(&imx_soc_platform);
735 if (ret) {
736 pr_err("failed to register soc platform: %d\n", ret);
737 return ret;
738 }
739
740 ret = platform_driver_register(&imx_ssi_driver);
741 if (ret) {
742 snd_soc_unregister_platform(&imx_soc_platform);
743 return ret;
744 }
745
746 return 0;
747}
748
749static void __exit imx_ssi_exit(void)
750{
751 platform_driver_unregister(&imx_ssi_driver);
752 snd_soc_unregister_platform(&imx_soc_platform);
753}
754
755module_init(imx_ssi_init);
756module_exit(imx_ssi_exit);
757
758/* Module information */
759MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
760MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
761MODULE_LICENSE("GPL");
762
Linux kernel - Deliverables
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