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336cfbb0 VK |
1 | /* |
2 | * sst_acpi.c - SST (LPE) driver init file for ACPI enumeration. | |
3 | * | |
4 | * Copyright (c) 2013, Intel Corporation. | |
5 | * | |
6 | * Authors: Ramesh Babu K V <Ramesh.Babu@intel.com> | |
7 | * Authors: Omair Mohammed Abdullah <omair.m.abdullah@intel.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/fs.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/miscdevice.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/firmware.h> | |
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/pm_qos.h> | |
73a33f6f | 31 | #include <linux/dmi.h> |
336cfbb0 VK |
32 | #include <linux/acpi.h> |
33 | #include <asm/platform_sst_audio.h> | |
34 | #include <sound/core.h> | |
35 | #include <sound/soc.h> | |
36 | #include <sound/compress_driver.h> | |
37 | #include <acpi/acbuffer.h> | |
38 | #include <acpi/platform/acenv.h> | |
39 | #include <acpi/platform/aclinux.h> | |
40 | #include <acpi/actypes.h> | |
41 | #include <acpi/acpi_bus.h> | |
42 | #include "../sst-mfld-platform.h" | |
b97169da | 43 | #include "../../common/sst-dsp.h" |
12cc291b | 44 | #include "../../common/sst-acpi.h" |
336cfbb0 VK |
45 | #include "sst.h" |
46 | ||
336cfbb0 VK |
47 | /* LPE viewpoint addresses */ |
48 | #define SST_BYT_IRAM_PHY_START 0xff2c0000 | |
49 | #define SST_BYT_IRAM_PHY_END 0xff2d4000 | |
50 | #define SST_BYT_DRAM_PHY_START 0xff300000 | |
51 | #define SST_BYT_DRAM_PHY_END 0xff320000 | |
52 | #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */ | |
53 | #define SST_BYT_IMR_VIRT_END 0xc01fffff | |
54 | #define SST_BYT_SHIM_PHY_ADDR 0xff340000 | |
55 | #define SST_BYT_MBOX_PHY_ADDR 0xff344000 | |
56 | #define SST_BYT_DMA0_PHY_ADDR 0xff298000 | |
57 | #define SST_BYT_DMA1_PHY_ADDR 0xff29c000 | |
58 | #define SST_BYT_SSP0_PHY_ADDR 0xff2a0000 | |
59 | #define SST_BYT_SSP2_PHY_ADDR 0xff2a2000 | |
60 | ||
61 | #define BYT_FW_MOD_TABLE_OFFSET 0x80000 | |
62 | #define BYT_FW_MOD_TABLE_SIZE 0x100 | |
63 | #define BYT_FW_MOD_OFFSET (BYT_FW_MOD_TABLE_OFFSET + BYT_FW_MOD_TABLE_SIZE) | |
64 | ||
65 | static const struct sst_info byt_fwparse_info = { | |
66 | .use_elf = false, | |
67 | .max_streams = 25, | |
68 | .iram_start = SST_BYT_IRAM_PHY_START, | |
69 | .iram_end = SST_BYT_IRAM_PHY_END, | |
70 | .iram_use = true, | |
71 | .dram_start = SST_BYT_DRAM_PHY_START, | |
72 | .dram_end = SST_BYT_DRAM_PHY_END, | |
73 | .dram_use = true, | |
74 | .imr_start = SST_BYT_IMR_VIRT_START, | |
75 | .imr_end = SST_BYT_IMR_VIRT_END, | |
76 | .imr_use = true, | |
77 | .mailbox_start = SST_BYT_MBOX_PHY_ADDR, | |
78 | .num_probes = 0, | |
79 | .lpe_viewpt_rqd = true, | |
80 | }; | |
81 | ||
82 | static const struct sst_ipc_info byt_ipc_info = { | |
83 | .ipc_offset = 0, | |
84 | .mbox_recv_off = 0x400, | |
85 | }; | |
86 | ||
87 | static const struct sst_lib_dnld_info byt_lib_dnld_info = { | |
88 | .mod_base = SST_BYT_IMR_VIRT_START, | |
89 | .mod_end = SST_BYT_IMR_VIRT_END, | |
90 | .mod_table_offset = BYT_FW_MOD_TABLE_OFFSET, | |
91 | .mod_table_size = BYT_FW_MOD_TABLE_SIZE, | |
92 | .mod_ddr_dnld = false, | |
93 | }; | |
94 | ||
95 | static const struct sst_res_info byt_rvp_res_info = { | |
96 | .shim_offset = 0x140000, | |
97 | .shim_size = 0x000100, | |
98 | .shim_phy_addr = SST_BYT_SHIM_PHY_ADDR, | |
99 | .ssp0_offset = 0xa0000, | |
100 | .ssp0_size = 0x1000, | |
101 | .dma0_offset = 0x98000, | |
102 | .dma0_size = 0x4000, | |
103 | .dma1_offset = 0x9c000, | |
104 | .dma1_size = 0x4000, | |
105 | .iram_offset = 0x0c0000, | |
106 | .iram_size = 0x14000, | |
107 | .dram_offset = 0x100000, | |
108 | .dram_size = 0x28000, | |
109 | .mbox_offset = 0x144000, | |
110 | .mbox_size = 0x1000, | |
111 | .acpi_lpe_res_index = 0, | |
112 | .acpi_ddr_index = 2, | |
113 | .acpi_ipc_irq_index = 5, | |
114 | }; | |
115 | ||
1a28fc19 | 116 | static struct sst_platform_info byt_rvp_platform_data = { |
336cfbb0 VK |
117 | .probe_data = &byt_fwparse_info, |
118 | .ipc_info = &byt_ipc_info, | |
119 | .lib_info = &byt_lib_dnld_info, | |
120 | .res_info = &byt_rvp_res_info, | |
121 | .platform = "sst-mfld-platform", | |
122 | }; | |
123 | ||
bd01fdc3 ML |
124 | /* Cherryview (Cherrytrail and Braswell) uses same mrfld dpcm fw as Baytrail, |
125 | * so pdata is same as Baytrail. | |
126 | */ | |
14cd7923 | 127 | static struct sst_platform_info chv_platform_data = { |
bd01fdc3 ML |
128 | .probe_data = &byt_fwparse_info, |
129 | .ipc_info = &byt_ipc_info, | |
130 | .lib_info = &byt_lib_dnld_info, | |
131 | .res_info = &byt_rvp_res_info, | |
132 | .platform = "sst-mfld-platform", | |
133 | }; | |
134 | ||
336cfbb0 VK |
135 | static int sst_platform_get_resources(struct intel_sst_drv *ctx) |
136 | { | |
137 | struct resource *rsrc; | |
138 | struct platform_device *pdev = to_platform_device(ctx->dev); | |
139 | ||
140 | /* All ACPI resource request here */ | |
141 | /* Get Shim addr */ | |
142 | rsrc = platform_get_resource(pdev, IORESOURCE_MEM, | |
143 | ctx->pdata->res_info->acpi_lpe_res_index); | |
144 | if (!rsrc) { | |
145 | dev_err(ctx->dev, "Invalid SHIM base from IFWI"); | |
146 | return -EIO; | |
147 | } | |
148 | dev_info(ctx->dev, "LPE base: %#x size:%#x", (unsigned int) rsrc->start, | |
149 | (unsigned int)resource_size(rsrc)); | |
150 | ||
151 | ctx->iram_base = rsrc->start + ctx->pdata->res_info->iram_offset; | |
152 | ctx->iram_end = ctx->iram_base + ctx->pdata->res_info->iram_size - 1; | |
153 | dev_info(ctx->dev, "IRAM base: %#x", ctx->iram_base); | |
154 | ctx->iram = devm_ioremap_nocache(ctx->dev, ctx->iram_base, | |
155 | ctx->pdata->res_info->iram_size); | |
156 | if (!ctx->iram) { | |
157 | dev_err(ctx->dev, "unable to map IRAM"); | |
158 | return -EIO; | |
159 | } | |
160 | ||
161 | ctx->dram_base = rsrc->start + ctx->pdata->res_info->dram_offset; | |
162 | ctx->dram_end = ctx->dram_base + ctx->pdata->res_info->dram_size - 1; | |
163 | dev_info(ctx->dev, "DRAM base: %#x", ctx->dram_base); | |
164 | ctx->dram = devm_ioremap_nocache(ctx->dev, ctx->dram_base, | |
165 | ctx->pdata->res_info->dram_size); | |
166 | if (!ctx->dram) { | |
167 | dev_err(ctx->dev, "unable to map DRAM"); | |
168 | return -EIO; | |
169 | } | |
170 | ||
171 | ctx->shim_phy_add = rsrc->start + ctx->pdata->res_info->shim_offset; | |
172 | dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add); | |
173 | ctx->shim = devm_ioremap_nocache(ctx->dev, ctx->shim_phy_add, | |
174 | ctx->pdata->res_info->shim_size); | |
175 | if (!ctx->shim) { | |
176 | dev_err(ctx->dev, "unable to map SHIM"); | |
177 | return -EIO; | |
178 | } | |
179 | ||
180 | /* reassign physical address to LPE viewpoint address */ | |
181 | ctx->shim_phy_add = ctx->pdata->res_info->shim_phy_addr; | |
182 | ||
183 | /* Get mailbox addr */ | |
184 | ctx->mailbox_add = rsrc->start + ctx->pdata->res_info->mbox_offset; | |
185 | dev_info(ctx->dev, "Mailbox base: %#x", ctx->mailbox_add); | |
186 | ctx->mailbox = devm_ioremap_nocache(ctx->dev, ctx->mailbox_add, | |
187 | ctx->pdata->res_info->mbox_size); | |
188 | if (!ctx->mailbox) { | |
189 | dev_err(ctx->dev, "unable to map mailbox"); | |
190 | return -EIO; | |
191 | } | |
192 | ||
193 | /* reassign physical address to LPE viewpoint address */ | |
194 | ctx->mailbox_add = ctx->info.mailbox_start; | |
195 | ||
196 | rsrc = platform_get_resource(pdev, IORESOURCE_MEM, | |
197 | ctx->pdata->res_info->acpi_ddr_index); | |
198 | if (!rsrc) { | |
199 | dev_err(ctx->dev, "Invalid DDR base from IFWI"); | |
200 | return -EIO; | |
201 | } | |
202 | ctx->ddr_base = rsrc->start; | |
203 | ctx->ddr_end = rsrc->end; | |
204 | dev_info(ctx->dev, "DDR base: %#x", ctx->ddr_base); | |
205 | ctx->ddr = devm_ioremap_nocache(ctx->dev, ctx->ddr_base, | |
206 | resource_size(rsrc)); | |
207 | if (!ctx->ddr) { | |
208 | dev_err(ctx->dev, "unable to map DDR"); | |
209 | return -EIO; | |
210 | } | |
211 | ||
212 | /* Find the IRQ */ | |
213 | ctx->irq_num = platform_get_irq(pdev, | |
214 | ctx->pdata->res_info->acpi_ipc_irq_index); | |
215 | return 0; | |
216 | } | |
217 | ||
5129ad6e | 218 | static int sst_acpi_probe(struct platform_device *pdev) |
336cfbb0 VK |
219 | { |
220 | struct device *dev = &pdev->dev; | |
221 | int ret = 0; | |
222 | struct intel_sst_drv *ctx; | |
223 | const struct acpi_device_id *id; | |
12cc291b | 224 | struct sst_acpi_mach *mach; |
336cfbb0 VK |
225 | struct platform_device *mdev; |
226 | struct platform_device *plat_dev; | |
12cc291b | 227 | struct sst_platform_info *pdata; |
336cfbb0 VK |
228 | unsigned int dev_id; |
229 | ||
230 | id = acpi_match_device(dev->driver->acpi_match_table, dev); | |
231 | if (!id) | |
232 | return -ENODEV; | |
233 | dev_dbg(dev, "for %s", id->id); | |
234 | ||
12cc291b | 235 | mach = (struct sst_acpi_mach *)id->driver_data; |
336cfbb0 VK |
236 | mach = sst_acpi_find_machine(mach); |
237 | if (mach == NULL) { | |
238 | dev_err(dev, "No matching machine driver found\n"); | |
239 | return -ENODEV; | |
240 | } | |
73a33f6f VK |
241 | if (mach->machine_quirk) |
242 | mach = mach->machine_quirk(mach); | |
243 | ||
12cc291b | 244 | pdata = mach->pdata; |
336cfbb0 VK |
245 | |
246 | ret = kstrtouint(id->id, 16, &dev_id); | |
247 | if (ret < 0) { | |
248 | dev_err(dev, "Unique device id conversion error: %d\n", ret); | |
249 | return ret; | |
250 | } | |
251 | ||
252 | dev_dbg(dev, "ACPI device id: %x\n", dev_id); | |
253 | ||
caf94ed8 PLB |
254 | plat_dev = platform_device_register_data(dev, pdata->platform, -1, |
255 | NULL, 0); | |
f5d40b40 | 256 | if (IS_ERR(plat_dev)) { |
caf94ed8 PLB |
257 | dev_err(dev, "Failed to create machine device: %s\n", |
258 | pdata->platform); | |
f5d40b40 | 259 | return PTR_ERR(plat_dev); |
336cfbb0 VK |
260 | } |
261 | ||
caf94ed8 PLB |
262 | /* |
263 | * Create platform device for sst machine driver, | |
264 | * pass machine info as pdata | |
265 | */ | |
266 | mdev = platform_device_register_data(dev, mach->drv_name, -1, | |
267 | (const void *)mach, sizeof(*mach)); | |
f5d40b40 | 268 | if (IS_ERR(mdev)) { |
caf94ed8 PLB |
269 | dev_err(dev, "Failed to create machine device: %s\n", |
270 | mach->drv_name); | |
f5d40b40 | 271 | return PTR_ERR(mdev); |
336cfbb0 VK |
272 | } |
273 | ||
274 | ret = sst_alloc_drv_context(&ctx, dev, dev_id); | |
275 | if (ret < 0) | |
276 | return ret; | |
277 | ||
278 | /* Fill sst platform data */ | |
12cc291b VK |
279 | ctx->pdata = pdata; |
280 | strcpy(ctx->firmware_name, mach->fw_filename); | |
336cfbb0 VK |
281 | |
282 | ret = sst_platform_get_resources(ctx); | |
283 | if (ret) | |
284 | return ret; | |
285 | ||
286 | ret = sst_context_init(ctx); | |
287 | if (ret < 0) | |
288 | return ret; | |
289 | ||
290 | /* need to save shim registers in BYT */ | |
291 | ctx->shim_regs64 = devm_kzalloc(ctx->dev, sizeof(*ctx->shim_regs64), | |
292 | GFP_KERNEL); | |
293 | if (!ctx->shim_regs64) { | |
bdc455b5 | 294 | ret = -ENOMEM; |
336cfbb0 VK |
295 | goto do_sst_cleanup; |
296 | } | |
297 | ||
298 | sst_configure_runtime_pm(ctx); | |
299 | platform_set_drvdata(pdev, ctx); | |
300 | return ret; | |
301 | ||
302 | do_sst_cleanup: | |
303 | sst_context_cleanup(ctx); | |
304 | platform_set_drvdata(pdev, NULL); | |
305 | dev_err(ctx->dev, "failed with %d\n", ret); | |
306 | return ret; | |
307 | } | |
308 | ||
309 | /** | |
310 | * intel_sst_remove - remove function | |
311 | * | |
312 | * @pdev: platform device structure | |
313 | * | |
314 | * This function is called by OS when a device is unloaded | |
315 | * This frees the interrupt etc | |
316 | */ | |
5129ad6e | 317 | static int sst_acpi_remove(struct platform_device *pdev) |
336cfbb0 VK |
318 | { |
319 | struct intel_sst_drv *ctx; | |
320 | ||
321 | ctx = platform_get_drvdata(pdev); | |
322 | sst_context_cleanup(ctx); | |
323 | platform_set_drvdata(pdev, NULL); | |
324 | return 0; | |
325 | } | |
326 | ||
73a33f6f VK |
327 | static unsigned long cht_machine_id; |
328 | ||
329 | #define CHT_SURFACE_MACH 1 | |
330 | ||
331 | static int cht_surface_quirk_cb(const struct dmi_system_id *id) | |
332 | { | |
333 | cht_machine_id = CHT_SURFACE_MACH; | |
334 | return 1; | |
335 | } | |
336 | ||
337 | ||
338 | static const struct dmi_system_id cht_table[] = { | |
339 | { | |
340 | .callback = cht_surface_quirk_cb, | |
341 | .matches = { | |
342 | DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"), | |
343 | DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"), | |
344 | }, | |
345 | }, | |
346 | }; | |
347 | ||
348 | ||
349 | static struct sst_acpi_mach cht_surface_mach = { | |
350 | "10EC5640", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL, | |
351 | &chv_platform_data }; | |
352 | ||
353 | struct sst_acpi_mach *cht_quirk(void *arg) | |
354 | { | |
355 | struct sst_acpi_mach *mach = arg; | |
356 | ||
357 | dmi_check_system(cht_table); | |
358 | ||
359 | if (cht_machine_id == CHT_SURFACE_MACH) | |
360 | return &cht_surface_mach; | |
361 | else | |
362 | return mach; | |
363 | } | |
364 | ||
12cc291b | 365 | static struct sst_acpi_mach sst_acpi_bytcr[] = { |
a2d5563b | 366 | {"10EC5640", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", NULL, |
336cfbb0 | 367 | &byt_rvp_platform_data }, |
7762ef42 PLB |
368 | {"10EC5642", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", NULL, |
369 | &byt_rvp_platform_data }, | |
55fc2056 JFM |
370 | {"INTCCFFD", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", NULL, |
371 | &byt_rvp_platform_data }, | |
2bd5bd15 PLB |
372 | {"10EC5651", "bytcr_rt5651", "intel/fw_sst_0f28.bin", "bytcr_rt5651", NULL, |
373 | &byt_rvp_platform_data }, | |
336cfbb0 VK |
374 | {}, |
375 | }; | |
376 | ||
bd01fdc3 | 377 | /* Cherryview-based platforms: CherryTrail and Braswell */ |
12cc291b VK |
378 | static struct sst_acpi_mach sst_acpi_chv[] = { |
379 | {"10EC5670", "cht-bsw-rt5672", "intel/fw_sst_22a8.bin", "cht-bsw", NULL, | |
380 | &chv_platform_data }, | |
381 | {"10EC5645", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL, | |
bd01fdc3 | 382 | &chv_platform_data }, |
12cc291b | 383 | {"10EC5650", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL, |
bd01fdc3 | 384 | &chv_platform_data }, |
12cc291b | 385 | {"193C9890", "cht-bsw-max98090", "intel/fw_sst_22a8.bin", "cht-bsw", NULL, |
044d9601 | 386 | &chv_platform_data }, |
fdf84193 | 387 | /* some CHT-T platforms rely on RT5640, use Baytrail machine driver */ |
73a33f6f | 388 | {"10EC5640", "bytcr_rt5640", "intel/fw_sst_22a8.bin", "bytcr_rt5640", cht_quirk, |
fdf84193 PLB |
389 | &chv_platform_data }, |
390 | ||
bd01fdc3 ML |
391 | {}, |
392 | }; | |
393 | ||
336cfbb0 VK |
394 | static const struct acpi_device_id sst_acpi_ids[] = { |
395 | { "80860F28", (unsigned long)&sst_acpi_bytcr}, | |
bd01fdc3 | 396 | { "808622A8", (unsigned long) &sst_acpi_chv}, |
336cfbb0 VK |
397 | { }, |
398 | }; | |
399 | ||
eb826a35 ML |
400 | MODULE_DEVICE_TABLE(acpi, sst_acpi_ids); |
401 | ||
336cfbb0 VK |
402 | static struct platform_driver sst_acpi_driver = { |
403 | .driver = { | |
404 | .name = "intel_sst_acpi", | |
336cfbb0 VK |
405 | .acpi_match_table = ACPI_PTR(sst_acpi_ids), |
406 | .pm = &intel_sst_pm, | |
407 | }, | |
408 | .probe = sst_acpi_probe, | |
409 | .remove = sst_acpi_remove, | |
410 | }; | |
411 | ||
412 | module_platform_driver(sst_acpi_driver); | |
413 | ||
414 | MODULE_DESCRIPTION("Intel (R) SST(R) Audio Engine ACPI Driver"); | |
415 | MODULE_AUTHOR("Ramesh Babu K V"); | |
416 | MODULE_AUTHOR("Omair Mohammed Abdullah"); | |
417 | MODULE_LICENSE("GPL v2"); | |
418 | MODULE_ALIAS("sst"); |