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d255b095 JK |
1 | /* |
2 | * skl-message.c - HDA DSP interface for FW registration, Pipe and Module | |
3 | * configurations | |
4 | * | |
5 | * Copyright (C) 2015 Intel Corp | |
6 | * Author:Rafal Redzimski <rafal.f.redzimski@intel.com> | |
7 | * Jeeja KP <jeeja.kp@intel.com> | |
8 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as version 2, as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | */ | |
19 | ||
20 | #include <linux/slab.h> | |
21 | #include <linux/pci.h> | |
22 | #include <sound/core.h> | |
23 | #include <sound/pcm.h> | |
24 | #include "skl-sst-dsp.h" | |
25 | #include "skl-sst-ipc.h" | |
26 | #include "skl.h" | |
27 | #include "../common/sst-dsp.h" | |
28 | #include "../common/sst-dsp-priv.h" | |
23db472b JK |
29 | #include "skl-topology.h" |
30 | #include "skl-tplg-interface.h" | |
d255b095 JK |
31 | |
32 | static int skl_alloc_dma_buf(struct device *dev, | |
33 | struct snd_dma_buffer *dmab, size_t size) | |
34 | { | |
35 | struct hdac_ext_bus *ebus = dev_get_drvdata(dev); | |
36 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
37 | ||
38 | if (!bus) | |
39 | return -ENODEV; | |
40 | ||
41 | return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, size, dmab); | |
42 | } | |
43 | ||
44 | static int skl_free_dma_buf(struct device *dev, struct snd_dma_buffer *dmab) | |
45 | { | |
46 | struct hdac_ext_bus *ebus = dev_get_drvdata(dev); | |
47 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
48 | ||
49 | if (!bus) | |
50 | return -ENODEV; | |
51 | ||
52 | bus->io_ops->dma_free_pages(bus, dmab); | |
53 | ||
54 | return 0; | |
55 | } | |
56 | ||
4e10996b JK |
57 | #define NOTIFICATION_PARAM_ID 3 |
58 | #define NOTIFICATION_MASK 0xf | |
59 | ||
60 | /* disable notfication for underruns/overruns from firmware module */ | |
61 | static void skl_dsp_enable_notification(struct skl_sst *ctx, bool enable) | |
62 | { | |
63 | struct notification_mask mask; | |
64 | struct skl_ipc_large_config_msg msg = {0}; | |
65 | ||
66 | mask.notify = NOTIFICATION_MASK; | |
67 | mask.enable = enable; | |
68 | ||
69 | msg.large_param_id = NOTIFICATION_PARAM_ID; | |
70 | msg.param_data_size = sizeof(mask); | |
71 | ||
72 | skl_ipc_set_large_config(&ctx->ipc, &msg, (u32 *)&mask); | |
73 | } | |
74 | ||
92eb4f62 JK |
75 | static int skl_dsp_setup_spib(struct device *dev, unsigned int size, |
76 | int stream_tag, int enable) | |
77 | { | |
78 | struct hdac_ext_bus *ebus = dev_get_drvdata(dev); | |
79 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
80 | struct hdac_stream *stream = snd_hdac_get_stream(bus, | |
81 | SNDRV_PCM_STREAM_PLAYBACK, stream_tag); | |
82 | struct hdac_ext_stream *estream; | |
83 | ||
84 | if (!stream) | |
85 | return -EINVAL; | |
86 | ||
87 | estream = stream_to_hdac_ext_stream(stream); | |
88 | /* enable/disable SPIB for this hdac stream */ | |
89 | snd_hdac_ext_stream_spbcap_enable(ebus, enable, stream->index); | |
90 | ||
91 | /* set the spib value */ | |
92 | snd_hdac_ext_stream_set_spib(ebus, estream, size); | |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
97 | static int skl_dsp_prepare(struct device *dev, unsigned int format, | |
98 | unsigned int size, struct snd_dma_buffer *dmab) | |
99 | { | |
100 | struct hdac_ext_bus *ebus = dev_get_drvdata(dev); | |
101 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
102 | struct hdac_ext_stream *estream; | |
103 | struct hdac_stream *stream; | |
104 | struct snd_pcm_substream substream; | |
105 | int ret; | |
106 | ||
107 | if (!bus) | |
108 | return -ENODEV; | |
109 | ||
110 | memset(&substream, 0, sizeof(substream)); | |
111 | substream.stream = SNDRV_PCM_STREAM_PLAYBACK; | |
112 | ||
113 | estream = snd_hdac_ext_stream_assign(ebus, &substream, | |
114 | HDAC_EXT_STREAM_TYPE_HOST); | |
115 | if (!estream) | |
116 | return -ENODEV; | |
117 | ||
118 | stream = hdac_stream(estream); | |
119 | ||
120 | /* assign decouple host dma channel */ | |
121 | ret = snd_hdac_dsp_prepare(stream, format, size, dmab); | |
122 | if (ret < 0) | |
123 | return ret; | |
124 | ||
125 | skl_dsp_setup_spib(dev, size, stream->stream_tag, true); | |
126 | ||
127 | return stream->stream_tag; | |
128 | } | |
129 | ||
130 | static int skl_dsp_trigger(struct device *dev, bool start, int stream_tag) | |
131 | { | |
132 | struct hdac_ext_bus *ebus = dev_get_drvdata(dev); | |
133 | struct hdac_stream *stream; | |
134 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
135 | ||
136 | if (!bus) | |
137 | return -ENODEV; | |
138 | ||
139 | stream = snd_hdac_get_stream(bus, | |
140 | SNDRV_PCM_STREAM_PLAYBACK, stream_tag); | |
141 | if (!stream) | |
142 | return -EINVAL; | |
143 | ||
144 | snd_hdac_dsp_trigger(stream, start); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
149 | static int skl_dsp_cleanup(struct device *dev, | |
150 | struct snd_dma_buffer *dmab, int stream_tag) | |
151 | { | |
152 | struct hdac_ext_bus *ebus = dev_get_drvdata(dev); | |
153 | struct hdac_stream *stream; | |
154 | struct hdac_ext_stream *estream; | |
155 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
156 | ||
157 | if (!bus) | |
158 | return -ENODEV; | |
159 | ||
160 | stream = snd_hdac_get_stream(bus, | |
161 | SNDRV_PCM_STREAM_PLAYBACK, stream_tag); | |
162 | if (!stream) | |
163 | return -EINVAL; | |
164 | ||
165 | estream = stream_to_hdac_ext_stream(stream); | |
166 | skl_dsp_setup_spib(dev, 0, stream_tag, false); | |
167 | snd_hdac_ext_stream_release(estream, HDAC_EXT_STREAM_TYPE_HOST); | |
168 | ||
169 | snd_hdac_dsp_cleanup(stream, dmab); | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
bc23ca35 JK |
174 | static struct skl_dsp_loader_ops skl_get_loader_ops(void) |
175 | { | |
176 | struct skl_dsp_loader_ops loader_ops; | |
177 | ||
178 | memset(&loader_ops, 0, sizeof(struct skl_dsp_loader_ops)); | |
179 | ||
180 | loader_ops.alloc_dma_buf = skl_alloc_dma_buf; | |
181 | loader_ops.free_dma_buf = skl_free_dma_buf; | |
182 | ||
183 | return loader_ops; | |
184 | }; | |
185 | ||
92eb4f62 JK |
186 | static struct skl_dsp_loader_ops bxt_get_loader_ops(void) |
187 | { | |
188 | struct skl_dsp_loader_ops loader_ops; | |
189 | ||
190 | memset(&loader_ops, 0, sizeof(loader_ops)); | |
191 | ||
192 | loader_ops.alloc_dma_buf = skl_alloc_dma_buf; | |
193 | loader_ops.free_dma_buf = skl_free_dma_buf; | |
194 | loader_ops.prepare = skl_dsp_prepare; | |
195 | loader_ops.trigger = skl_dsp_trigger; | |
196 | loader_ops.cleanup = skl_dsp_cleanup; | |
197 | ||
198 | return loader_ops; | |
199 | }; | |
200 | ||
bc23ca35 JK |
201 | static const struct skl_dsp_ops dsp_ops[] = { |
202 | { | |
203 | .id = 0x9d70, | |
204 | .loader_ops = skl_get_loader_ops, | |
205 | .init = skl_sst_dsp_init, | |
206 | .cleanup = skl_sst_dsp_cleanup | |
207 | }, | |
451dfb5f VK |
208 | { |
209 | .id = 0x9d71, | |
210 | .loader_ops = skl_get_loader_ops, | |
211 | .init = skl_sst_dsp_init, | |
212 | .cleanup = skl_sst_dsp_cleanup | |
213 | }, | |
92eb4f62 JK |
214 | { |
215 | .id = 0x5a98, | |
216 | .loader_ops = bxt_get_loader_ops, | |
217 | .init = bxt_sst_dsp_init, | |
218 | .cleanup = bxt_sst_dsp_cleanup | |
219 | }, | |
bc23ca35 JK |
220 | }; |
221 | ||
222 | static int skl_get_dsp_ops(int pci_id) | |
223 | { | |
224 | int i; | |
225 | ||
226 | for (i = 0; i < ARRAY_SIZE(dsp_ops); i++) { | |
227 | if (dsp_ops[i].id == pci_id) | |
228 | return i; | |
229 | } | |
230 | ||
231 | return -EINVAL; | |
232 | } | |
233 | ||
d255b095 JK |
234 | int skl_init_dsp(struct skl *skl) |
235 | { | |
236 | void __iomem *mmio_base; | |
237 | struct hdac_ext_bus *ebus = &skl->ebus; | |
238 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
d255b095 | 239 | struct skl_dsp_loader_ops loader_ops; |
bc23ca35 JK |
240 | int irq = bus->irq; |
241 | int ret, index; | |
d255b095 JK |
242 | |
243 | /* enable ppcap interrupt */ | |
244 | snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true); | |
245 | snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true); | |
246 | ||
247 | /* read the BAR of the ADSP MMIO */ | |
248 | mmio_base = pci_ioremap_bar(skl->pci, 4); | |
249 | if (mmio_base == NULL) { | |
250 | dev_err(bus->dev, "ioremap error\n"); | |
251 | return -ENXIO; | |
252 | } | |
253 | ||
bc23ca35 JK |
254 | index = skl_get_dsp_ops(skl->pci->device); |
255 | if (index < 0) | |
256 | return -EINVAL; | |
257 | ||
258 | loader_ops = dsp_ops[index].loader_ops(); | |
259 | ret = dsp_ops[index].init(bus->dev, mmio_base, irq, | |
aecf6fd8 | 260 | skl->fw_name, loader_ops, &skl->skl_sst); |
bc23ca35 | 261 | |
2ac454ff JK |
262 | if (ret < 0) |
263 | return ret; | |
264 | ||
4e10996b | 265 | skl_dsp_enable_notification(skl->skl_sst, false); |
d255b095 JK |
266 | dev_dbg(bus->dev, "dsp registration status=%d\n", ret); |
267 | ||
268 | return ret; | |
269 | } | |
270 | ||
bc23ca35 | 271 | int skl_free_dsp(struct skl *skl) |
d255b095 JK |
272 | { |
273 | struct hdac_ext_bus *ebus = &skl->ebus; | |
274 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
bc23ca35 JK |
275 | struct skl_sst *ctx = skl->skl_sst; |
276 | int index; | |
d255b095 JK |
277 | |
278 | /* disable ppcap interrupt */ | |
279 | snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, false); | |
280 | ||
bc23ca35 JK |
281 | index = skl_get_dsp_ops(skl->pci->device); |
282 | if (index < 0) | |
283 | return -EIO; | |
284 | ||
285 | dsp_ops[index].cleanup(bus->dev, ctx); | |
286 | ||
d255b095 JK |
287 | if (ctx->dsp->addr.lpe) |
288 | iounmap(ctx->dsp->addr.lpe); | |
bc23ca35 JK |
289 | |
290 | return 0; | |
d255b095 JK |
291 | } |
292 | ||
293 | int skl_suspend_dsp(struct skl *skl) | |
294 | { | |
295 | struct skl_sst *ctx = skl->skl_sst; | |
296 | int ret; | |
297 | ||
298 | /* if ppcap is not supported return 0 */ | |
299 | if (!skl->ebus.ppcap) | |
300 | return 0; | |
301 | ||
302 | ret = skl_dsp_sleep(ctx->dsp); | |
303 | if (ret < 0) | |
304 | return ret; | |
305 | ||
306 | /* disable ppcap interrupt */ | |
307 | snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, false); | |
308 | snd_hdac_ext_bus_ppcap_enable(&skl->ebus, false); | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | int skl_resume_dsp(struct skl *skl) | |
314 | { | |
315 | struct skl_sst *ctx = skl->skl_sst; | |
4e10996b | 316 | int ret; |
d255b095 JK |
317 | |
318 | /* if ppcap is not supported return 0 */ | |
319 | if (!skl->ebus.ppcap) | |
320 | return 0; | |
321 | ||
322 | /* enable ppcap interrupt */ | |
323 | snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true); | |
324 | snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true); | |
325 | ||
4e10996b JK |
326 | ret = skl_dsp_wake(ctx->dsp); |
327 | if (ret < 0) | |
328 | return ret; | |
329 | ||
330 | skl_dsp_enable_notification(skl->skl_sst, false); | |
331 | return ret; | |
d255b095 | 332 | } |
23db472b JK |
333 | |
334 | enum skl_bitdepth skl_get_bit_depth(int params) | |
335 | { | |
336 | switch (params) { | |
337 | case 8: | |
338 | return SKL_DEPTH_8BIT; | |
339 | ||
340 | case 16: | |
341 | return SKL_DEPTH_16BIT; | |
342 | ||
343 | case 24: | |
344 | return SKL_DEPTH_24BIT; | |
345 | ||
346 | case 32: | |
347 | return SKL_DEPTH_32BIT; | |
348 | ||
349 | default: | |
350 | return SKL_DEPTH_INVALID; | |
351 | ||
352 | } | |
353 | } | |
354 | ||
23db472b JK |
355 | /* |
356 | * Each module in DSP expects a base module configuration, which consists of | |
357 | * PCM format information, which we calculate in driver and resource values | |
358 | * which are read from widget information passed through topology binary | |
359 | * This is send when we create a module with INIT_INSTANCE IPC msg | |
360 | */ | |
361 | static void skl_set_base_module_format(struct skl_sst *ctx, | |
362 | struct skl_module_cfg *mconfig, | |
363 | struct skl_base_cfg *base_cfg) | |
364 | { | |
4cd9899f | 365 | struct skl_module_fmt *format = &mconfig->in_fmt[0]; |
23db472b JK |
366 | |
367 | base_cfg->audio_fmt.number_of_channels = (u8)format->channels; | |
368 | ||
369 | base_cfg->audio_fmt.s_freq = format->s_freq; | |
370 | base_cfg->audio_fmt.bit_depth = format->bit_depth; | |
371 | base_cfg->audio_fmt.valid_bit_depth = format->valid_bit_depth; | |
372 | base_cfg->audio_fmt.ch_cfg = format->ch_cfg; | |
373 | ||
374 | dev_dbg(ctx->dev, "bit_depth=%x valid_bd=%x ch_config=%x\n", | |
375 | format->bit_depth, format->valid_bit_depth, | |
376 | format->ch_cfg); | |
377 | ||
3e81f1a3 | 378 | base_cfg->audio_fmt.channel_map = format->ch_map; |
23db472b | 379 | |
3e81f1a3 | 380 | base_cfg->audio_fmt.interleaving = format->interleaving_style; |
23db472b JK |
381 | |
382 | base_cfg->cps = mconfig->mcps; | |
383 | base_cfg->ibs = mconfig->ibs; | |
384 | base_cfg->obs = mconfig->obs; | |
b18c458d | 385 | base_cfg->is_pages = mconfig->mem_pages; |
23db472b JK |
386 | } |
387 | ||
388 | /* | |
389 | * Copies copier capabilities into copier module and updates copier module | |
390 | * config size. | |
391 | */ | |
392 | static void skl_copy_copier_caps(struct skl_module_cfg *mconfig, | |
393 | struct skl_cpr_cfg *cpr_mconfig) | |
394 | { | |
395 | if (mconfig->formats_config.caps_size == 0) | |
396 | return; | |
397 | ||
398 | memcpy(cpr_mconfig->gtw_cfg.config_data, | |
399 | mconfig->formats_config.caps, | |
400 | mconfig->formats_config.caps_size); | |
401 | ||
402 | cpr_mconfig->gtw_cfg.config_length = | |
403 | (mconfig->formats_config.caps_size) / 4; | |
404 | } | |
405 | ||
bfa764ac | 406 | #define SKL_NON_GATEWAY_CPR_NODE_ID 0xFFFFFFFF |
23db472b JK |
407 | /* |
408 | * Calculate the gatewat settings required for copier module, type of | |
409 | * gateway and index of gateway to use | |
410 | */ | |
4fdf810f D |
411 | static u32 skl_get_node_id(struct skl_sst *ctx, |
412 | struct skl_module_cfg *mconfig) | |
23db472b JK |
413 | { |
414 | union skl_connector_node_id node_id = {0}; | |
d7b18813 | 415 | union skl_ssp_dma_node ssp_node = {0}; |
23db472b JK |
416 | struct skl_pipe_params *params = mconfig->pipe->p_params; |
417 | ||
418 | switch (mconfig->dev_type) { | |
419 | case SKL_DEVICE_BT: | |
420 | node_id.node.dma_type = | |
421 | (SKL_CONN_SOURCE == mconfig->hw_conn_type) ? | |
422 | SKL_DMA_I2S_LINK_OUTPUT_CLASS : | |
423 | SKL_DMA_I2S_LINK_INPUT_CLASS; | |
424 | node_id.node.vindex = params->host_dma_id + | |
425 | (mconfig->vbus_id << 3); | |
426 | break; | |
427 | ||
428 | case SKL_DEVICE_I2S: | |
429 | node_id.node.dma_type = | |
430 | (SKL_CONN_SOURCE == mconfig->hw_conn_type) ? | |
431 | SKL_DMA_I2S_LINK_OUTPUT_CLASS : | |
432 | SKL_DMA_I2S_LINK_INPUT_CLASS; | |
d7b18813 JK |
433 | ssp_node.dma_node.time_slot_index = mconfig->time_slot; |
434 | ssp_node.dma_node.i2s_instance = mconfig->vbus_id; | |
435 | node_id.node.vindex = ssp_node.val; | |
23db472b JK |
436 | break; |
437 | ||
438 | case SKL_DEVICE_DMIC: | |
439 | node_id.node.dma_type = SKL_DMA_DMIC_LINK_INPUT_CLASS; | |
440 | node_id.node.vindex = mconfig->vbus_id + | |
441 | (mconfig->time_slot); | |
442 | break; | |
443 | ||
444 | case SKL_DEVICE_HDALINK: | |
445 | node_id.node.dma_type = | |
446 | (SKL_CONN_SOURCE == mconfig->hw_conn_type) ? | |
447 | SKL_DMA_HDA_LINK_OUTPUT_CLASS : | |
448 | SKL_DMA_HDA_LINK_INPUT_CLASS; | |
449 | node_id.node.vindex = params->link_dma_id; | |
450 | break; | |
451 | ||
bfa764ac | 452 | case SKL_DEVICE_HDAHOST: |
23db472b JK |
453 | node_id.node.dma_type = |
454 | (SKL_CONN_SOURCE == mconfig->hw_conn_type) ? | |
455 | SKL_DMA_HDA_HOST_OUTPUT_CLASS : | |
456 | SKL_DMA_HDA_HOST_INPUT_CLASS; | |
457 | node_id.node.vindex = params->host_dma_id; | |
458 | break; | |
bfa764ac JK |
459 | |
460 | default: | |
4fdf810f D |
461 | node_id.val = 0xFFFFFFFF; |
462 | break; | |
463 | } | |
464 | ||
465 | return node_id.val; | |
466 | } | |
467 | ||
468 | static void skl_setup_cpr_gateway_cfg(struct skl_sst *ctx, | |
469 | struct skl_module_cfg *mconfig, | |
470 | struct skl_cpr_cfg *cpr_mconfig) | |
471 | { | |
472 | cpr_mconfig->gtw_cfg.node_id = skl_get_node_id(ctx, mconfig); | |
473 | ||
474 | if (cpr_mconfig->gtw_cfg.node_id == SKL_NON_GATEWAY_CPR_NODE_ID) { | |
bfa764ac JK |
475 | cpr_mconfig->cpr_feature_mask = 0; |
476 | return; | |
23db472b JK |
477 | } |
478 | ||
23db472b JK |
479 | if (SKL_CONN_SOURCE == mconfig->hw_conn_type) |
480 | cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * mconfig->obs; | |
481 | else | |
482 | cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * mconfig->ibs; | |
483 | ||
484 | cpr_mconfig->cpr_feature_mask = 0; | |
485 | cpr_mconfig->gtw_cfg.config_length = 0; | |
486 | ||
487 | skl_copy_copier_caps(mconfig, cpr_mconfig); | |
488 | } | |
489 | ||
c115fa5e D |
490 | #define DMA_CONTROL_ID 5 |
491 | ||
492 | int skl_dsp_set_dma_control(struct skl_sst *ctx, struct skl_module_cfg *mconfig) | |
493 | { | |
494 | struct skl_dma_control *dma_ctrl; | |
495 | struct skl_i2s_config_blob config_blob; | |
496 | struct skl_ipc_large_config_msg msg = {0}; | |
497 | int err = 0; | |
498 | ||
499 | ||
500 | /* | |
501 | * if blob size is same as capablity size, then no dma control | |
502 | * present so return | |
503 | */ | |
504 | if (mconfig->formats_config.caps_size == sizeof(config_blob)) | |
505 | return 0; | |
506 | ||
507 | msg.large_param_id = DMA_CONTROL_ID; | |
508 | msg.param_data_size = sizeof(struct skl_dma_control) + | |
509 | mconfig->formats_config.caps_size; | |
510 | ||
511 | dma_ctrl = kzalloc(msg.param_data_size, GFP_KERNEL); | |
512 | if (dma_ctrl == NULL) | |
513 | return -ENOMEM; | |
514 | ||
515 | dma_ctrl->node_id = skl_get_node_id(ctx, mconfig); | |
516 | ||
517 | /* size in dwords */ | |
518 | dma_ctrl->config_length = sizeof(config_blob) / 4; | |
519 | ||
520 | memcpy(dma_ctrl->config_data, mconfig->formats_config.caps, | |
521 | mconfig->formats_config.caps_size); | |
522 | ||
523 | err = skl_ipc_set_large_config(&ctx->ipc, &msg, (u32 *)dma_ctrl); | |
524 | ||
525 | kfree(dma_ctrl); | |
526 | ||
527 | return err; | |
528 | } | |
529 | ||
23db472b JK |
530 | static void skl_setup_out_format(struct skl_sst *ctx, |
531 | struct skl_module_cfg *mconfig, | |
532 | struct skl_audio_data_format *out_fmt) | |
533 | { | |
4cd9899f | 534 | struct skl_module_fmt *format = &mconfig->out_fmt[0]; |
23db472b JK |
535 | |
536 | out_fmt->number_of_channels = (u8)format->channels; | |
537 | out_fmt->s_freq = format->s_freq; | |
538 | out_fmt->bit_depth = format->bit_depth; | |
539 | out_fmt->valid_bit_depth = format->valid_bit_depth; | |
540 | out_fmt->ch_cfg = format->ch_cfg; | |
541 | ||
3e81f1a3 JK |
542 | out_fmt->channel_map = format->ch_map; |
543 | out_fmt->interleaving = format->interleaving_style; | |
544 | out_fmt->sample_type = format->sample_type; | |
23db472b JK |
545 | |
546 | dev_dbg(ctx->dev, "copier out format chan=%d fre=%d bitdepth=%d\n", | |
547 | out_fmt->number_of_channels, format->s_freq, format->bit_depth); | |
548 | } | |
549 | ||
a0ffe48b HS |
550 | /* |
551 | * DSP needs SRC module for frequency conversion, SRC takes base module | |
552 | * configuration and the target frequency as extra parameter passed as src | |
553 | * config | |
554 | */ | |
555 | static void skl_set_src_format(struct skl_sst *ctx, | |
556 | struct skl_module_cfg *mconfig, | |
557 | struct skl_src_module_cfg *src_mconfig) | |
558 | { | |
4cd9899f | 559 | struct skl_module_fmt *fmt = &mconfig->out_fmt[0]; |
a0ffe48b HS |
560 | |
561 | skl_set_base_module_format(ctx, mconfig, | |
562 | (struct skl_base_cfg *)src_mconfig); | |
563 | ||
564 | src_mconfig->src_cfg = fmt->s_freq; | |
565 | } | |
566 | ||
567 | /* | |
568 | * DSP needs updown module to do channel conversion. updown module take base | |
569 | * module configuration and channel configuration | |
570 | * It also take coefficients and now we have defaults applied here | |
571 | */ | |
572 | static void skl_set_updown_mixer_format(struct skl_sst *ctx, | |
573 | struct skl_module_cfg *mconfig, | |
574 | struct skl_up_down_mixer_cfg *mixer_mconfig) | |
575 | { | |
4cd9899f | 576 | struct skl_module_fmt *fmt = &mconfig->out_fmt[0]; |
a0ffe48b HS |
577 | int i = 0; |
578 | ||
579 | skl_set_base_module_format(ctx, mconfig, | |
580 | (struct skl_base_cfg *)mixer_mconfig); | |
581 | mixer_mconfig->out_ch_cfg = fmt->ch_cfg; | |
582 | ||
583 | /* Select F/W default coefficient */ | |
584 | mixer_mconfig->coeff_sel = 0x0; | |
585 | ||
586 | /* User coeff, don't care since we are selecting F/W defaults */ | |
587 | for (i = 0; i < UP_DOWN_MIXER_MAX_COEFF; i++) | |
588 | mixer_mconfig->coeff[i] = 0xDEADBEEF; | |
589 | } | |
590 | ||
23db472b JK |
591 | /* |
592 | * 'copier' is DSP internal module which copies data from Host DMA (HDA host | |
593 | * dma) or link (hda link, SSP, PDM) | |
594 | * Here we calculate the copier module parameters, like PCM format, output | |
595 | * format, gateway settings | |
596 | * copier_module_config is sent as input buffer with INIT_INSTANCE IPC msg | |
597 | */ | |
598 | static void skl_set_copier_format(struct skl_sst *ctx, | |
599 | struct skl_module_cfg *mconfig, | |
600 | struct skl_cpr_cfg *cpr_mconfig) | |
601 | { | |
602 | struct skl_audio_data_format *out_fmt = &cpr_mconfig->out_fmt; | |
603 | struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)cpr_mconfig; | |
604 | ||
605 | skl_set_base_module_format(ctx, mconfig, base_cfg); | |
606 | ||
607 | skl_setup_out_format(ctx, mconfig, out_fmt); | |
608 | skl_setup_cpr_gateway_cfg(ctx, mconfig, cpr_mconfig); | |
609 | } | |
610 | ||
399b210b JK |
611 | /* |
612 | * Algo module are DSP pre processing modules. Algo module take base module | |
613 | * configuration and params | |
614 | */ | |
615 | ||
616 | static void skl_set_algo_format(struct skl_sst *ctx, | |
617 | struct skl_module_cfg *mconfig, | |
618 | struct skl_algo_cfg *algo_mcfg) | |
619 | { | |
620 | struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)algo_mcfg; | |
621 | ||
622 | skl_set_base_module_format(ctx, mconfig, base_cfg); | |
623 | ||
624 | if (mconfig->formats_config.caps_size == 0) | |
625 | return; | |
626 | ||
627 | memcpy(algo_mcfg->params, | |
628 | mconfig->formats_config.caps, | |
629 | mconfig->formats_config.caps_size); | |
630 | ||
631 | } | |
632 | ||
fd18110f D |
633 | /* |
634 | * Mic select module allows selecting one or many input channels, thus | |
635 | * acting as a demux. | |
636 | * | |
637 | * Mic select module take base module configuration and out-format | |
638 | * configuration | |
639 | */ | |
640 | static void skl_set_base_outfmt_format(struct skl_sst *ctx, | |
641 | struct skl_module_cfg *mconfig, | |
642 | struct skl_base_outfmt_cfg *base_outfmt_mcfg) | |
643 | { | |
644 | struct skl_audio_data_format *out_fmt = &base_outfmt_mcfg->out_fmt; | |
645 | struct skl_base_cfg *base_cfg = | |
646 | (struct skl_base_cfg *)base_outfmt_mcfg; | |
647 | ||
648 | skl_set_base_module_format(ctx, mconfig, base_cfg); | |
649 | skl_setup_out_format(ctx, mconfig, out_fmt); | |
650 | } | |
651 | ||
23db472b JK |
652 | static u16 skl_get_module_param_size(struct skl_sst *ctx, |
653 | struct skl_module_cfg *mconfig) | |
654 | { | |
655 | u16 param_size; | |
656 | ||
657 | switch (mconfig->m_type) { | |
658 | case SKL_MODULE_TYPE_COPIER: | |
659 | param_size = sizeof(struct skl_cpr_cfg); | |
660 | param_size += mconfig->formats_config.caps_size; | |
661 | return param_size; | |
662 | ||
a0ffe48b HS |
663 | case SKL_MODULE_TYPE_SRCINT: |
664 | return sizeof(struct skl_src_module_cfg); | |
665 | ||
666 | case SKL_MODULE_TYPE_UPDWMIX: | |
667 | return sizeof(struct skl_up_down_mixer_cfg); | |
668 | ||
399b210b JK |
669 | case SKL_MODULE_TYPE_ALGO: |
670 | param_size = sizeof(struct skl_base_cfg); | |
671 | param_size += mconfig->formats_config.caps_size; | |
672 | return param_size; | |
673 | ||
fd18110f D |
674 | case SKL_MODULE_TYPE_BASE_OUTFMT: |
675 | return sizeof(struct skl_base_outfmt_cfg); | |
676 | ||
23db472b JK |
677 | default: |
678 | /* | |
679 | * return only base cfg when no specific module type is | |
680 | * specified | |
681 | */ | |
682 | return sizeof(struct skl_base_cfg); | |
683 | } | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
688 | /* | |
a0ffe48b HS |
689 | * DSP firmware supports various modules like copier, SRC, updown etc. |
690 | * These modules required various parameters to be calculated and sent for | |
691 | * the module initialization to DSP. By default a generic module needs only | |
692 | * base module format configuration | |
23db472b | 693 | */ |
a0ffe48b | 694 | |
23db472b JK |
695 | static int skl_set_module_format(struct skl_sst *ctx, |
696 | struct skl_module_cfg *module_config, | |
697 | u16 *module_config_size, | |
698 | void **param_data) | |
699 | { | |
700 | u16 param_size; | |
701 | ||
702 | param_size = skl_get_module_param_size(ctx, module_config); | |
703 | ||
704 | *param_data = kzalloc(param_size, GFP_KERNEL); | |
705 | if (NULL == *param_data) | |
706 | return -ENOMEM; | |
707 | ||
708 | *module_config_size = param_size; | |
709 | ||
710 | switch (module_config->m_type) { | |
711 | case SKL_MODULE_TYPE_COPIER: | |
712 | skl_set_copier_format(ctx, module_config, *param_data); | |
713 | break; | |
714 | ||
a0ffe48b HS |
715 | case SKL_MODULE_TYPE_SRCINT: |
716 | skl_set_src_format(ctx, module_config, *param_data); | |
717 | break; | |
718 | ||
719 | case SKL_MODULE_TYPE_UPDWMIX: | |
720 | skl_set_updown_mixer_format(ctx, module_config, *param_data); | |
721 | break; | |
722 | ||
399b210b JK |
723 | case SKL_MODULE_TYPE_ALGO: |
724 | skl_set_algo_format(ctx, module_config, *param_data); | |
725 | break; | |
726 | ||
fd18110f D |
727 | case SKL_MODULE_TYPE_BASE_OUTFMT: |
728 | skl_set_base_outfmt_format(ctx, module_config, *param_data); | |
729 | break; | |
730 | ||
23db472b JK |
731 | default: |
732 | skl_set_base_module_format(ctx, module_config, *param_data); | |
733 | break; | |
734 | ||
735 | } | |
736 | ||
737 | dev_dbg(ctx->dev, "Module type=%d config size: %d bytes\n", | |
738 | module_config->id.module_id, param_size); | |
91c18325 | 739 | print_hex_dump_debug("Module params:", DUMP_PREFIX_OFFSET, 8, 4, |
23db472b JK |
740 | *param_data, param_size, false); |
741 | return 0; | |
742 | } | |
743 | ||
744 | static int skl_get_queue_index(struct skl_module_pin *mpin, | |
745 | struct skl_module_inst_id id, int max) | |
746 | { | |
747 | int i; | |
748 | ||
749 | for (i = 0; i < max; i++) { | |
750 | if (mpin[i].id.module_id == id.module_id && | |
751 | mpin[i].id.instance_id == id.instance_id) | |
752 | return i; | |
753 | } | |
754 | ||
755 | return -EINVAL; | |
756 | } | |
757 | ||
758 | /* | |
759 | * Allocates queue for each module. | |
760 | * if dynamic, the pin_index is allocated 0 to max_pin. | |
761 | * In static, the pin_index is fixed based on module_id and instance id | |
762 | */ | |
763 | static int skl_alloc_queue(struct skl_module_pin *mpin, | |
4f745708 | 764 | struct skl_module_cfg *tgt_cfg, int max) |
23db472b JK |
765 | { |
766 | int i; | |
4f745708 | 767 | struct skl_module_inst_id id = tgt_cfg->id; |
23db472b JK |
768 | /* |
769 | * if pin in dynamic, find first free pin | |
770 | * otherwise find match module and instance id pin as topology will | |
771 | * ensure a unique pin is assigned to this so no need to | |
772 | * allocate/free | |
773 | */ | |
774 | for (i = 0; i < max; i++) { | |
775 | if (mpin[i].is_dynamic) { | |
4f745708 JK |
776 | if (!mpin[i].in_use && |
777 | mpin[i].pin_state == SKL_PIN_UNBIND) { | |
778 | ||
23db472b JK |
779 | mpin[i].in_use = true; |
780 | mpin[i].id.module_id = id.module_id; | |
781 | mpin[i].id.instance_id = id.instance_id; | |
4f745708 | 782 | mpin[i].tgt_mcfg = tgt_cfg; |
23db472b JK |
783 | return i; |
784 | } | |
785 | } else { | |
786 | if (mpin[i].id.module_id == id.module_id && | |
4f745708 JK |
787 | mpin[i].id.instance_id == id.instance_id && |
788 | mpin[i].pin_state == SKL_PIN_UNBIND) { | |
789 | ||
790 | mpin[i].tgt_mcfg = tgt_cfg; | |
23db472b | 791 | return i; |
4f745708 | 792 | } |
23db472b JK |
793 | } |
794 | } | |
795 | ||
796 | return -EINVAL; | |
797 | } | |
798 | ||
799 | static void skl_free_queue(struct skl_module_pin *mpin, int q_index) | |
800 | { | |
801 | if (mpin[q_index].is_dynamic) { | |
802 | mpin[q_index].in_use = false; | |
803 | mpin[q_index].id.module_id = 0; | |
804 | mpin[q_index].id.instance_id = 0; | |
805 | } | |
4f745708 JK |
806 | mpin[q_index].pin_state = SKL_PIN_UNBIND; |
807 | mpin[q_index].tgt_mcfg = NULL; | |
808 | } | |
809 | ||
810 | /* Module state will be set to unint, if all the out pin state is UNBIND */ | |
811 | ||
812 | static void skl_clear_module_state(struct skl_module_pin *mpin, int max, | |
813 | struct skl_module_cfg *mcfg) | |
814 | { | |
815 | int i; | |
816 | bool found = false; | |
817 | ||
818 | for (i = 0; i < max; i++) { | |
819 | if (mpin[i].pin_state == SKL_PIN_UNBIND) | |
820 | continue; | |
821 | found = true; | |
822 | break; | |
823 | } | |
824 | ||
825 | if (!found) | |
826 | mcfg->m_state = SKL_MODULE_UNINIT; | |
827 | return; | |
23db472b | 828 | } |
beb73b26 JK |
829 | |
830 | /* | |
831 | * A module needs to be instanataited in DSP. A mdoule is present in a | |
832 | * collection of module referred as a PIPE. | |
833 | * We first calculate the module format, based on module type and then | |
834 | * invoke the DSP by sending IPC INIT_INSTANCE using ipc helper | |
835 | */ | |
836 | int skl_init_module(struct skl_sst *ctx, | |
9939a9c3 | 837 | struct skl_module_cfg *mconfig) |
beb73b26 JK |
838 | { |
839 | u16 module_config_size = 0; | |
840 | void *param_data = NULL; | |
841 | int ret; | |
842 | struct skl_ipc_init_instance_msg msg; | |
843 | ||
844 | dev_dbg(ctx->dev, "%s: module_id = %d instance=%d\n", __func__, | |
845 | mconfig->id.module_id, mconfig->id.instance_id); | |
846 | ||
847 | if (mconfig->pipe->state != SKL_PIPE_CREATED) { | |
848 | dev_err(ctx->dev, "Pipe not created state= %d pipe_id= %d\n", | |
849 | mconfig->pipe->state, mconfig->pipe->ppl_id); | |
850 | return -EIO; | |
851 | } | |
852 | ||
853 | ret = skl_set_module_format(ctx, mconfig, | |
854 | &module_config_size, ¶m_data); | |
855 | if (ret < 0) { | |
856 | dev_err(ctx->dev, "Failed to set module format ret=%d\n", ret); | |
857 | return ret; | |
858 | } | |
859 | ||
860 | msg.module_id = mconfig->id.module_id; | |
861 | msg.instance_id = mconfig->id.instance_id; | |
862 | msg.ppl_instance_id = mconfig->pipe->ppl_id; | |
863 | msg.param_data_size = module_config_size; | |
864 | msg.core_id = mconfig->core_id; | |
865 | ||
866 | ret = skl_ipc_init_instance(&ctx->ipc, &msg, param_data); | |
867 | if (ret < 0) { | |
868 | dev_err(ctx->dev, "Failed to init instance ret=%d\n", ret); | |
869 | kfree(param_data); | |
870 | return ret; | |
871 | } | |
872 | mconfig->m_state = SKL_MODULE_INIT_DONE; | |
76222d6d | 873 | kfree(param_data); |
beb73b26 JK |
874 | return ret; |
875 | } | |
876 | ||
877 | static void skl_dump_bind_info(struct skl_sst *ctx, struct skl_module_cfg | |
878 | *src_module, struct skl_module_cfg *dst_module) | |
879 | { | |
880 | dev_dbg(ctx->dev, "%s: src module_id = %d src_instance=%d\n", | |
881 | __func__, src_module->id.module_id, src_module->id.instance_id); | |
882 | dev_dbg(ctx->dev, "%s: dst_module=%d dst_instacne=%d\n", __func__, | |
883 | dst_module->id.module_id, dst_module->id.instance_id); | |
884 | ||
885 | dev_dbg(ctx->dev, "src_module state = %d dst module state = %d\n", | |
886 | src_module->m_state, dst_module->m_state); | |
887 | } | |
888 | ||
889 | /* | |
890 | * On module freeup, we need to unbind the module with modules | |
891 | * it is already bind. | |
892 | * Find the pin allocated and unbind then using bind_unbind IPC | |
893 | */ | |
894 | int skl_unbind_modules(struct skl_sst *ctx, | |
895 | struct skl_module_cfg *src_mcfg, | |
896 | struct skl_module_cfg *dst_mcfg) | |
897 | { | |
898 | int ret; | |
899 | struct skl_ipc_bind_unbind_msg msg; | |
900 | struct skl_module_inst_id src_id = src_mcfg->id; | |
901 | struct skl_module_inst_id dst_id = dst_mcfg->id; | |
902 | int in_max = dst_mcfg->max_in_queue; | |
903 | int out_max = src_mcfg->max_out_queue; | |
4f745708 | 904 | int src_index, dst_index, src_pin_state, dst_pin_state; |
beb73b26 JK |
905 | |
906 | skl_dump_bind_info(ctx, src_mcfg, dst_mcfg); | |
907 | ||
beb73b26 JK |
908 | /* get src queue index */ |
909 | src_index = skl_get_queue_index(src_mcfg->m_out_pin, dst_id, out_max); | |
910 | if (src_index < 0) | |
9cf3049e | 911 | return 0; |
beb73b26 | 912 | |
4f745708 | 913 | msg.src_queue = src_index; |
beb73b26 JK |
914 | |
915 | /* get dst queue index */ | |
916 | dst_index = skl_get_queue_index(dst_mcfg->m_in_pin, src_id, in_max); | |
917 | if (dst_index < 0) | |
9cf3049e | 918 | return 0; |
beb73b26 | 919 | |
4f745708 JK |
920 | msg.dst_queue = dst_index; |
921 | ||
922 | src_pin_state = src_mcfg->m_out_pin[src_index].pin_state; | |
923 | dst_pin_state = dst_mcfg->m_in_pin[dst_index].pin_state; | |
924 | ||
925 | if (src_pin_state != SKL_PIN_BIND_DONE || | |
926 | dst_pin_state != SKL_PIN_BIND_DONE) | |
927 | return 0; | |
beb73b26 JK |
928 | |
929 | msg.module_id = src_mcfg->id.module_id; | |
930 | msg.instance_id = src_mcfg->id.instance_id; | |
931 | msg.dst_module_id = dst_mcfg->id.module_id; | |
932 | msg.dst_instance_id = dst_mcfg->id.instance_id; | |
933 | msg.bind = false; | |
934 | ||
935 | ret = skl_ipc_bind_unbind(&ctx->ipc, &msg); | |
936 | if (!ret) { | |
beb73b26 JK |
937 | /* free queue only if unbind is success */ |
938 | skl_free_queue(src_mcfg->m_out_pin, src_index); | |
939 | skl_free_queue(dst_mcfg->m_in_pin, dst_index); | |
4f745708 JK |
940 | |
941 | /* | |
942 | * check only if src module bind state, bind is | |
943 | * always from src -> sink | |
944 | */ | |
945 | skl_clear_module_state(src_mcfg->m_out_pin, out_max, src_mcfg); | |
beb73b26 JK |
946 | } |
947 | ||
948 | return ret; | |
949 | } | |
950 | ||
951 | /* | |
952 | * Once a module is instantiated it need to be 'bind' with other modules in | |
953 | * the pipeline. For binding we need to find the module pins which are bind | |
954 | * together | |
955 | * This function finds the pins and then sends bund_unbind IPC message to | |
956 | * DSP using IPC helper | |
957 | */ | |
958 | int skl_bind_modules(struct skl_sst *ctx, | |
959 | struct skl_module_cfg *src_mcfg, | |
960 | struct skl_module_cfg *dst_mcfg) | |
961 | { | |
962 | int ret; | |
963 | struct skl_ipc_bind_unbind_msg msg; | |
beb73b26 JK |
964 | int in_max = dst_mcfg->max_in_queue; |
965 | int out_max = src_mcfg->max_out_queue; | |
966 | int src_index, dst_index; | |
967 | ||
968 | skl_dump_bind_info(ctx, src_mcfg, dst_mcfg); | |
969 | ||
0c684c48 | 970 | if (src_mcfg->m_state < SKL_MODULE_INIT_DONE || |
beb73b26 JK |
971 | dst_mcfg->m_state < SKL_MODULE_INIT_DONE) |
972 | return 0; | |
973 | ||
4f745708 | 974 | src_index = skl_alloc_queue(src_mcfg->m_out_pin, dst_mcfg, out_max); |
beb73b26 JK |
975 | if (src_index < 0) |
976 | return -EINVAL; | |
977 | ||
4f745708 JK |
978 | msg.src_queue = src_index; |
979 | dst_index = skl_alloc_queue(dst_mcfg->m_in_pin, src_mcfg, in_max); | |
beb73b26 JK |
980 | if (dst_index < 0) { |
981 | skl_free_queue(src_mcfg->m_out_pin, src_index); | |
982 | return -EINVAL; | |
983 | } | |
984 | ||
4f745708 | 985 | msg.dst_queue = dst_index; |
beb73b26 JK |
986 | |
987 | dev_dbg(ctx->dev, "src queue = %d dst queue =%d\n", | |
988 | msg.src_queue, msg.dst_queue); | |
989 | ||
990 | msg.module_id = src_mcfg->id.module_id; | |
991 | msg.instance_id = src_mcfg->id.instance_id; | |
992 | msg.dst_module_id = dst_mcfg->id.module_id; | |
993 | msg.dst_instance_id = dst_mcfg->id.instance_id; | |
994 | msg.bind = true; | |
995 | ||
996 | ret = skl_ipc_bind_unbind(&ctx->ipc, &msg); | |
997 | ||
998 | if (!ret) { | |
999 | src_mcfg->m_state = SKL_MODULE_BIND_DONE; | |
4f745708 JK |
1000 | src_mcfg->m_out_pin[src_index].pin_state = SKL_PIN_BIND_DONE; |
1001 | dst_mcfg->m_in_pin[dst_index].pin_state = SKL_PIN_BIND_DONE; | |
beb73b26 JK |
1002 | } else { |
1003 | /* error case , if IPC fails, clear the queue index */ | |
1004 | skl_free_queue(src_mcfg->m_out_pin, src_index); | |
1005 | skl_free_queue(dst_mcfg->m_in_pin, dst_index); | |
1006 | } | |
1007 | ||
1008 | return ret; | |
1009 | } | |
c9b1e834 JK |
1010 | |
1011 | static int skl_set_pipe_state(struct skl_sst *ctx, struct skl_pipe *pipe, | |
1012 | enum skl_ipc_pipeline_state state) | |
1013 | { | |
1014 | dev_dbg(ctx->dev, "%s: pipe_satate = %d\n", __func__, state); | |
1015 | ||
1016 | return skl_ipc_set_pipeline_state(&ctx->ipc, pipe->ppl_id, state); | |
1017 | } | |
1018 | ||
1019 | /* | |
1020 | * A pipeline is a collection of modules. Before a module in instantiated a | |
1021 | * pipeline needs to be created for it. | |
1022 | * This function creates pipeline, by sending create pipeline IPC messages | |
1023 | * to FW | |
1024 | */ | |
1025 | int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe) | |
1026 | { | |
1027 | int ret; | |
1028 | ||
1029 | dev_dbg(ctx->dev, "%s: pipe_id = %d\n", __func__, pipe->ppl_id); | |
1030 | ||
1031 | ret = skl_ipc_create_pipeline(&ctx->ipc, pipe->memory_pages, | |
1032 | pipe->pipe_priority, pipe->ppl_id); | |
1033 | if (ret < 0) { | |
1034 | dev_err(ctx->dev, "Failed to create pipeline\n"); | |
1035 | return ret; | |
1036 | } | |
1037 | ||
1038 | pipe->state = SKL_PIPE_CREATED; | |
1039 | ||
1040 | return 0; | |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * A pipeline needs to be deleted on cleanup. If a pipeline is running, then | |
1045 | * pause the pipeline first and then delete it | |
1046 | * The pipe delete is done by sending delete pipeline IPC. DSP will stop the | |
1047 | * DMA engines and releases resources | |
1048 | */ | |
1049 | int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe) | |
1050 | { | |
1051 | int ret; | |
1052 | ||
1053 | dev_dbg(ctx->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id); | |
1054 | ||
1ae7ca04 | 1055 | /* If pipe is started, do stop the pipe in FW. */ |
c9b1e834 JK |
1056 | if (pipe->state > SKL_PIPE_STARTED) { |
1057 | ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED); | |
1058 | if (ret < 0) { | |
1059 | dev_err(ctx->dev, "Failed to stop pipeline\n"); | |
1060 | return ret; | |
1061 | } | |
1062 | ||
1063 | pipe->state = SKL_PIPE_PAUSED; | |
1ae7ca04 | 1064 | } |
c9b1e834 | 1065 | |
1ae7ca04 D |
1066 | /* If pipe was not created in FW, do not try to delete it */ |
1067 | if (pipe->state < SKL_PIPE_CREATED) | |
1068 | return 0; | |
d2c7db85 | 1069 | |
1ae7ca04 D |
1070 | ret = skl_ipc_delete_pipeline(&ctx->ipc, pipe->ppl_id); |
1071 | if (ret < 0) { | |
1072 | dev_err(ctx->dev, "Failed to delete pipeline\n"); | |
1073 | return ret; | |
c9b1e834 JK |
1074 | } |
1075 | ||
1ae7ca04 D |
1076 | pipe->state = SKL_PIPE_INVALID; |
1077 | ||
c9b1e834 JK |
1078 | return ret; |
1079 | } | |
1080 | ||
1081 | /* | |
1082 | * A pipeline is also a scheduling entity in DSP which can be run, stopped | |
1083 | * For processing data the pipe need to be run by sending IPC set pipe state | |
1084 | * to DSP | |
1085 | */ | |
1086 | int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe) | |
1087 | { | |
1088 | int ret; | |
1089 | ||
1090 | dev_dbg(ctx->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id); | |
1091 | ||
1092 | /* If pipe was not created in FW, do not try to pause or delete */ | |
1093 | if (pipe->state < SKL_PIPE_CREATED) | |
1094 | return 0; | |
1095 | ||
1096 | /* Pipe has to be paused before it is started */ | |
1097 | ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED); | |
1098 | if (ret < 0) { | |
1099 | dev_err(ctx->dev, "Failed to pause pipe\n"); | |
1100 | return ret; | |
1101 | } | |
1102 | ||
1103 | pipe->state = SKL_PIPE_PAUSED; | |
1104 | ||
1105 | ret = skl_set_pipe_state(ctx, pipe, PPL_RUNNING); | |
1106 | if (ret < 0) { | |
1107 | dev_err(ctx->dev, "Failed to start pipe\n"); | |
1108 | return ret; | |
1109 | } | |
1110 | ||
1111 | pipe->state = SKL_PIPE_STARTED; | |
1112 | ||
1113 | return 0; | |
1114 | } | |
1115 | ||
1116 | /* | |
1117 | * Stop the pipeline by sending set pipe state IPC | |
1118 | * DSP doesnt implement stop so we always send pause message | |
1119 | */ | |
1120 | int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe) | |
1121 | { | |
1122 | int ret; | |
1123 | ||
1124 | dev_dbg(ctx->dev, "In %s pipe=%d\n", __func__, pipe->ppl_id); | |
1125 | ||
1126 | /* If pipe was not created in FW, do not try to pause or delete */ | |
1127 | if (pipe->state < SKL_PIPE_PAUSED) | |
1128 | return 0; | |
1129 | ||
1130 | ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED); | |
1131 | if (ret < 0) { | |
1132 | dev_dbg(ctx->dev, "Failed to stop pipe\n"); | |
1133 | return ret; | |
1134 | } | |
1135 | ||
353f72aa | 1136 | pipe->state = SKL_PIPE_PAUSED; |
c9b1e834 JK |
1137 | |
1138 | return 0; | |
1139 | } | |
9939a9c3 | 1140 | |
2004432f JK |
1141 | /* |
1142 | * Reset the pipeline by sending set pipe state IPC this will reset the DMA | |
1143 | * from the DSP side | |
1144 | */ | |
1145 | int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe) | |
1146 | { | |
1147 | int ret; | |
1148 | ||
1149 | /* If pipe was not created in FW, do not try to pause or delete */ | |
1150 | if (pipe->state < SKL_PIPE_PAUSED) | |
1151 | return 0; | |
1152 | ||
1153 | ret = skl_set_pipe_state(ctx, pipe, PPL_RESET); | |
1154 | if (ret < 0) { | |
1155 | dev_dbg(ctx->dev, "Failed to reset pipe ret=%d\n", ret); | |
1156 | return ret; | |
1157 | } | |
1158 | ||
1159 | pipe->state = SKL_PIPE_RESET; | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
9939a9c3 JK |
1164 | /* Algo parameter set helper function */ |
1165 | int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size, | |
1166 | u32 param_id, struct skl_module_cfg *mcfg) | |
1167 | { | |
1168 | struct skl_ipc_large_config_msg msg; | |
1169 | ||
1170 | msg.module_id = mcfg->id.module_id; | |
1171 | msg.instance_id = mcfg->id.instance_id; | |
1172 | msg.param_data_size = size; | |
1173 | msg.large_param_id = param_id; | |
1174 | ||
1175 | return skl_ipc_set_large_config(&ctx->ipc, &msg, params); | |
1176 | } | |
7d9f2911 OA |
1177 | |
1178 | int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size, | |
1179 | u32 param_id, struct skl_module_cfg *mcfg) | |
1180 | { | |
1181 | struct skl_ipc_large_config_msg msg; | |
1182 | ||
1183 | msg.module_id = mcfg->id.module_id; | |
1184 | msg.instance_id = mcfg->id.instance_id; | |
1185 | msg.param_data_size = size; | |
1186 | msg.large_param_id = param_id; | |
1187 | ||
1188 | return skl_ipc_get_large_config(&ctx->ipc, &msg, params); | |
1189 | } |