[deliverable/linux.git] / sound / soc / intel / skylake / skl-sst-cldma.c

/*
 * skl-sst-cldma.c - Code Loader DMA handler
 *
 * Copyright (C) 2015, Intel Corporation.
 * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */

#include <linux/device.h>
#include <linux/mm.h>
#include <linux/kthread.h>
#include "../common/sst-dsp.h"
#include "../common/sst-dsp-priv.h"

static void skl_cldma_int_enable(struct sst_dsp *ctx)
{
	sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
				SKL_ADSPIC_CL_DMA, SKL_ADSPIC_CL_DMA);
}

void skl_cldma_int_disable(struct sst_dsp *ctx)
{
	sst_dsp_shim_update_bits_unlocked(ctx,
			SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0);
}

/* Code loader helper APIs */
static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
		struct snd_dma_buffer *dmab_data,
		u32 **bdlp, int size, int with_ioc)
{
	u32 *bdl = *bdlp;

	ctx->cl_dev.frags = 0;
	while (size > 0) {
		phys_addr_t addr = virt_to_phys(dmab_data->area +
				(ctx->cl_dev.frags * ctx->cl_dev.bufsize));

		bdl[0] = cpu_to_le32(lower_32_bits(addr));
		bdl[1] = cpu_to_le32(upper_32_bits(addr));

		bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize);

		size -= ctx->cl_dev.bufsize;
		bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);

		bdl += 4;
		ctx->cl_dev.frags++;
	}
}

/*
 * Setup controller
 * Configure the registers to update the dma buffer address and
 * enable interrupts.
 * Note: Using the channel 1 for transfer
 */
static void skl_cldma_setup_controller(struct sst_dsp  *ctx,
		struct snd_dma_buffer *dmab_bdl, unsigned int max_size,
		u32 count)
{
	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
			CL_SD_BDLPLBA(dmab_bdl->addr));
	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
			CL_SD_BDLPUBA(dmab_bdl->addr));

	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);
	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);
	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
			CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(1));
	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
			CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(1));
	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
			CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(1));
	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
			CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(FW_CL_STREAM_NUMBER));
}

static void skl_cldma_setup_spb(struct sst_dsp  *ctx,
		unsigned int size, bool enable)
{
	if (enable)
		sst_dsp_shim_update_bits_unlocked(ctx,
				SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
				CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
				CL_SPBFIFO_SPBFCCTL_SPIBE(1));

	sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);
}

static void skl_cldma_cleanup_spb(struct sst_dsp  *ctx)
{
	sst_dsp_shim_update_bits_unlocked(ctx,
			SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
			CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
			CL_SPBFIFO_SPBFCCTL_SPIBE(0));

	sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
}

static void skl_cldma_trigger(struct sst_dsp  *ctx, bool enable)
{
	if (enable)
		sst_dsp_shim_update_bits_unlocked(ctx,
			SKL_ADSP_REG_CL_SD_CTL,
			CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(1));
	else
		sst_dsp_shim_update_bits_unlocked(ctx,
			SKL_ADSP_REG_CL_SD_CTL,
			CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(0));
}

static void skl_cldma_cleanup(struct sst_dsp  *ctx)
{
	skl_cldma_cleanup_spb(ctx);

	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
				CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
				CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
				CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
				CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));

	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);

	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);

	ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
	ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
}

static int skl_cldma_wait_interruptible(struct sst_dsp *ctx)
{
	int ret = 0;

	if (!wait_event_timeout(ctx->cl_dev.wait_queue,
				ctx->cl_dev.wait_condition,
				msecs_to_jiffies(SKL_WAIT_TIMEOUT))) {
		dev_err(ctx->dev, "%s: Wait timeout\n", __func__);
		ret = -EIO;
		goto cleanup;
	}

	dev_dbg(ctx->dev, "%s: Event wake\n", __func__);
	if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
		dev_err(ctx->dev, "%s: DMA Error\n", __func__);
		ret = -EIO;
	}

cleanup:
	ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
	return ret;
}

static void skl_cldma_stop(struct sst_dsp *ctx)
{
	ctx->cl_dev.ops.cl_trigger(ctx, false);
}

static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
		const void *curr_pos, bool intr_enable, bool trigger)
{
	dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);
	dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",
			ctx->cl_dev.dma_buffer_offset, trigger);
	dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);

	/*
	 * Check if the size exceeds buffer boundary. If it exceeds
	 * max_buffer size, then copy till buffer size and then copy
	 * remaining buffer from the start of ring buffer.
	 */
	if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) {
		unsigned int size_b = ctx->cl_dev.bufsize -
					ctx->cl_dev.dma_buffer_offset;
		memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
			curr_pos, size_b);
		size -= size_b;
		curr_pos += size_b;
		ctx->cl_dev.dma_buffer_offset = 0;
	}

	memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
			curr_pos, size);

	if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
		ctx->cl_dev.dma_buffer_offset = 0;
	else
		ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;

	ctx->cl_dev.wait_condition = false;

	if (intr_enable)
		skl_cldma_int_enable(ctx);

	ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
	if (trigger)
		ctx->cl_dev.ops.cl_trigger(ctx, true);
}

/*
 * The CL dma doesn't have any way to update the transfer status until a BDL
 * buffer is fully transferred
 *
 * So Copying is divided in two parts.
 * 1. Interrupt on buffer done where the size to be transferred is more than
 *    ring buffer size.
 * 2. Polling on fw register to identify if data left to transferred doesn't
 *    fill the ring buffer. Caller takes care of polling the required status
 *    register to identify the transfer status.
 */
static int
skl_cldma_copy_to_buf(struct sst_dsp *ctx, const void *bin, u32 total_size)
{
	int ret = 0;
	bool start = true;
	unsigned int excess_bytes;
	u32 size;
	unsigned int bytes_left = total_size;
	const void *curr_pos = bin;

	if (total_size <= 0)
		return -EINVAL;

	dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left);

	while (bytes_left) {
		if (bytes_left > ctx->cl_dev.bufsize) {

			/*
			 * dma transfers only till the write pointer as
			 * updated in spib
			 */
			if (ctx->cl_dev.curr_spib_pos == 0)
				ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;

			size = ctx->cl_dev.bufsize;
			skl_cldma_fill_buffer(ctx, size, curr_pos, true, start);

			start = false;
			ret = skl_cldma_wait_interruptible(ctx);
			if (ret < 0) {
				skl_cldma_stop(ctx);
				return ret;
			}

		} else {
			skl_cldma_int_disable(ctx);

			if ((ctx->cl_dev.curr_spib_pos + bytes_left)
							<= ctx->cl_dev.bufsize) {
				ctx->cl_dev.curr_spib_pos += bytes_left;
			} else {
				excess_bytes = bytes_left -
					(ctx->cl_dev.bufsize -
					ctx->cl_dev.curr_spib_pos);
				ctx->cl_dev.curr_spib_pos = excess_bytes;
			}

			size = bytes_left;
			skl_cldma_fill_buffer(ctx, size,
					curr_pos, false, start);
		}
		bytes_left -= size;
		curr_pos = curr_pos + size;
	}

	return ret;
}

void skl_cldma_process_intr(struct sst_dsp *ctx)
{
	u8 cl_dma_intr_status;

	cl_dma_intr_status =
		sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS);

	if (!(cl_dma_intr_status & SKL_CL_DMA_SD_INT_COMPLETE))
		ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;
	else
		ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;

	ctx->cl_dev.wait_condition = true;
	wake_up(&ctx->cl_dev.wait_queue);
}

int skl_cldma_prepare(struct sst_dsp *ctx)
{
	int ret;
	u32 *bdl;

	ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;

	/* Allocate cl ops */
	ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;
	ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
	ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
	ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
	ctx->cl_dev.ops.cl_trigger = skl_cldma_trigger;
	ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
	ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
	ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;

	/* Allocate buffer*/
	ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
			&ctx->cl_dev.dmab_data, ctx->cl_dev.bufsize);
	if (ret < 0) {
		dev_err(ctx->dev, "Alloc buffer for base fw failed: %x", ret);
		return ret;
	}
	/* Setup Code loader BDL */
	ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
			&ctx->cl_dev.dmab_bdl, PAGE_SIZE);
	if (ret < 0) {
		dev_err(ctx->dev, "Alloc buffer for blde failed: %x", ret);
		ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
		return ret;
	}
	bdl = (u32 *)ctx->cl_dev.dmab_bdl.area;

	/* Allocate BDLs */
	ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,
			&bdl, ctx->cl_dev.bufsize, 1);
	ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,
			ctx->cl_dev.bufsize, ctx->cl_dev.frags);

	ctx->cl_dev.curr_spib_pos = 0;
	ctx->cl_dev.dma_buffer_offset = 0;
	init_waitqueue_head(&ctx->cl_dev.wait_queue);

	return ret;
}
Commit	Line	Data
914426c8 VK	1	/*
	2	* skl-sst-cldma.c - Code Loader DMA handler
	3	*
	4	* Copyright (C) 2015, Intel Corporation.
	5	* Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
	6	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as version 2, as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*/
	17
	18	#include <linux/device.h>
	19	#include <linux/mm.h>
	20	#include <linux/kthread.h>
	21	#include "../common/sst-dsp.h"
	22	#include "../common/sst-dsp-priv.h"
	23
	24	static void skl_cldma_int_enable(struct sst_dsp *ctx)
	25	{
	26	sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
	27	SKL_ADSPIC_CL_DMA, SKL_ADSPIC_CL_DMA);
	28	}
	29
	30	void skl_cldma_int_disable(struct sst_dsp *ctx)
	31	{
	32	sst_dsp_shim_update_bits_unlocked(ctx,
	33	SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0);
	34	}
	35
	36	/* Code loader helper APIs */
	37	static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
	38	struct snd_dma_buffer *dmab_data,
	39	u32 **bdlp, int size, int with_ioc)
	40	{
	41	u32 bdl = bdlp;
	42
	43	ctx->cl_dev.frags = 0;
	44	while (size > 0) {
	45	phys_addr_t addr = virt_to_phys(dmab_data->area +
	46	(ctx->cl_dev.frags * ctx->cl_dev.bufsize));
	47
	48	bdl[0] = cpu_to_le32(lower_32_bits(addr));
	49	bdl[1] = cpu_to_le32(upper_32_bits(addr));
	50
	51	bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize);
	52
	53	size -= ctx->cl_dev.bufsize;
	54	bdl[3] = (size \|\| !with_ioc) ? 0 : cpu_to_le32(0x01);
	55
	56	bdl += 4;
	57	ctx->cl_dev.frags++;
	58	}
	59	}
	60
	61	/*
	62	* Setup controller
	63	* Configure the registers to update the dma buffer address and
	64	* enable interrupts.
65	* Note: Using the channel 1 for transfer
66	*/
67	static void skl_cldma_setup_controller(struct sst_dsp *ctx,
68	struct snd_dma_buffer *dmab_bdl, unsigned int max_size,
69	u32 count)
70	{
71	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
72	CL_SD_BDLPLBA(dmab_bdl->addr));
73	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
74	CL_SD_BDLPUBA(dmab_bdl->addr));
75
76	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);
77	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);
78	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
79	CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(1));
80	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
81	CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(1));
82	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
83	CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(1));
84	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
85	CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(FW_CL_STREAM_NUMBER));
86	}
87
88	static void skl_cldma_setup_spb(struct sst_dsp *ctx,
89	unsigned int size, bool enable)
90	{
91	if (enable)
92	sst_dsp_shim_update_bits_unlocked(ctx,
93	SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
94	CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
95	CL_SPBFIFO_SPBFCCTL_SPIBE(1));
96
97	sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);
98	}
99
100	static void skl_cldma_cleanup_spb(struct sst_dsp *ctx)
101	{
102	sst_dsp_shim_update_bits_unlocked(ctx,
103	SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
104	CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
105	CL_SPBFIFO_SPBFCCTL_SPIBE(0));
106
107	sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
108	}
109
110	static void skl_cldma_trigger(struct sst_dsp *ctx, bool enable)
111	{
112	if (enable)
113	sst_dsp_shim_update_bits_unlocked(ctx,
114	SKL_ADSP_REG_CL_SD_CTL,
115	CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(1));
116	else
117	sst_dsp_shim_update_bits_unlocked(ctx,
118	SKL_ADSP_REG_CL_SD_CTL,
119	CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(0));
120	}
121
122	static void skl_cldma_cleanup(struct sst_dsp *ctx)
123	{
124	skl_cldma_cleanup_spb(ctx);
125
126	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
127	CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
128	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
129	CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
130	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
131	CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
132	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
133	CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
134
135	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
136	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
137
138	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
139	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
ae395937	140
cd470fae VK	141	ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
cd470fae VK	142	ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
914426c8 VK	143	}
	144
	145	static int skl_cldma_wait_interruptible(struct sst_dsp *ctx)
	146	{
	147	int ret = 0;
	148
	149	if (!wait_event_timeout(ctx->cl_dev.wait_queue,
	150	ctx->cl_dev.wait_condition,
	151	msecs_to_jiffies(SKL_WAIT_TIMEOUT))) {
	152	dev_err(ctx->dev, "%s: Wait timeout\n", __func__);
	153	ret = -EIO;
	154	goto cleanup;
	155	}
	156
	157	dev_dbg(ctx->dev, "%s: Event wake\n", __func__);
	158	if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
	159	dev_err(ctx->dev, "%s: DMA Error\n", __func__);
	160	ret = -EIO;
	161	}
	162
	163	cleanup:
	164	ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
	165	return ret;
	166	}
	167
	168	static void skl_cldma_stop(struct sst_dsp *ctx)
	169	{
	170	ctx->cl_dev.ops.cl_trigger(ctx, false);
	171	}
	172
	173	static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
	174	const void *curr_pos, bool intr_enable, bool trigger)
	175	{
	176	dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);
	177	dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",
	178	ctx->cl_dev.dma_buffer_offset, trigger);
	179	dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);
	180
e797af53 JK	181	/*
	182	* Check if the size exceeds buffer boundary. If it exceeds
	183	* max_buffer size, then copy till buffer size and then copy
	184	* remaining buffer from the start of ring buffer.
	185	*/
	186	if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) {
	187	unsigned int size_b = ctx->cl_dev.bufsize -
	188	ctx->cl_dev.dma_buffer_offset;
	189	memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
	190	curr_pos, size_b);
	191	size -= size_b;
	192	curr_pos += size_b;
	193	ctx->cl_dev.dma_buffer_offset = 0;
	194	}
	195
914426c8 VK	196	memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
	197	curr_pos, size);
	198
	199	if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
	200	ctx->cl_dev.dma_buffer_offset = 0;
	201	else
	202	ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;
	203
	204	ctx->cl_dev.wait_condition = false;
	205
	206	if (intr_enable)
	207	skl_cldma_int_enable(ctx);
	208
	209	ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
	210	if (trigger)
	211	ctx->cl_dev.ops.cl_trigger(ctx, true);
	212	}
3e40a784 VK	213
	214	/*
	215	* The CL dma doesn't have any way to update the transfer status until a BDL
	216	* buffer is fully transferred
	217	*
	218	* So Copying is divided in two parts.
	219	* 1. Interrupt on buffer done where the size to be transferred is more than
	220	* ring buffer size.
	221	* 2. Polling on fw register to identify if data left to transferred doesn't
	222	* fill the ring buffer. Caller takes care of polling the required status
	223	* register to identify the transfer status.
	224	*/
	225	static int
	226	skl_cldma_copy_to_buf(struct sst_dsp ctx, const void bin, u32 total_size)
	227	{
	228	int ret = 0;
	229	bool start = true;
	230	unsigned int excess_bytes;
	231	u32 size;
	232	unsigned int bytes_left = total_size;
	233	const void *curr_pos = bin;
	234
	235	if (total_size <= 0)
	236	return -EINVAL;
	237
	238	dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left);
	239
	240	while (bytes_left) {
	241	if (bytes_left > ctx->cl_dev.bufsize) {
	242
	243	/*
	244	* dma transfers only till the write pointer as
	245	* updated in spib
	246	*/
	247	if (ctx->cl_dev.curr_spib_pos == 0)
	248	ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;
	249
	250	size = ctx->cl_dev.bufsize;
	251	skl_cldma_fill_buffer(ctx, size, curr_pos, true, start);
	252
	253	start = false;
	254	ret = skl_cldma_wait_interruptible(ctx);
	255	if (ret < 0) {
	256	skl_cldma_stop(ctx);
	257	return ret;
	258	}
	259
	260	} else {
	261	skl_cldma_int_disable(ctx);
	262
	263	if ((ctx->cl_dev.curr_spib_pos + bytes_left)
	264	<= ctx->cl_dev.bufsize) {
	265	ctx->cl_dev.curr_spib_pos += bytes_left;
	266	} else {
	267	excess_bytes = bytes_left -
	268	(ctx->cl_dev.bufsize -
	269	ctx->cl_dev.curr_spib_pos);
	270	ctx->cl_dev.curr_spib_pos = excess_bytes;
	271	}
	272
	273	size = bytes_left;
	274	skl_cldma_fill_buffer(ctx, size,
	275	curr_pos, false, start);
	276	}
277	bytes_left -= size;
278	curr_pos = curr_pos + size;
279	}
280
281	return ret;
282	}
283
284	void skl_cldma_process_intr(struct sst_dsp *ctx)
285	{
286	u8 cl_dma_intr_status;
287
288	cl_dma_intr_status =
289	sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS);
290
291	if (!(cl_dma_intr_status & SKL_CL_DMA_SD_INT_COMPLETE))
292	ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;
293	else
294	ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;
295
296	ctx->cl_dev.wait_condition = true;
297	wake_up(&ctx->cl_dev.wait_queue);
298	}
299
300	int skl_cldma_prepare(struct sst_dsp *ctx)
301	{
302	int ret;
303	u32 *bdl;
304
305	ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;
306
307	/* Allocate cl ops */
308	ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;
309	ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
310	ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
311	ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
312	ctx->cl_dev.ops.cl_trigger = skl_cldma_trigger;
313	ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
314	ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
315	ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
316
317	/* Allocate buffer*/
318	ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
319	&ctx->cl_dev.dmab_data, ctx->cl_dev.bufsize);
320	if (ret < 0) {
321	dev_err(ctx->dev, "Alloc buffer for base fw failed: %x", ret);
322	return ret;
323	}
324	/* Setup Code loader BDL */
325	ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
326	&ctx->cl_dev.dmab_bdl, PAGE_SIZE);
327	if (ret < 0) {
328	dev_err(ctx->dev, "Alloc buffer for blde failed: %x", ret);
329	ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
330	return ret;
331	}
332	bdl = (u32 *)ctx->cl_dev.dmab_bdl.area;
333
334	/* Allocate BDLs */
335	ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,
336	&bdl, ctx->cl_dev.bufsize, 1);
337	ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,
338	ctx->cl_dev.bufsize, ctx->cl_dev.frags);
339
340	ctx->cl_dev.curr_spib_pos = 0;
341	ctx->cl_dev.dma_buffer_offset = 0;
342	init_waitqueue_head(&ctx->cl_dev.wait_queue);
343
344	return ret;
345	}