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3582f9ae SP |
1 | /* |
2 | * Skylake SST DSP Support | |
3 | * | |
4 | * Copyright (C) 2014-15, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as version 2, as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | */ | |
15 | ||
16 | #ifndef __SKL_SST_DSP_H__ | |
17 | #define __SKL_SST_DSP_H__ | |
18 | ||
a750ba5f | 19 | #include <linux/interrupt.h> |
b6626802 | 20 | #include <sound/memalloc.h> |
3e40a784 | 21 | #include "skl-sst-cldma.h" |
b6626802 | 22 | |
3e40a784 | 23 | struct sst_dsp; |
a750ba5f | 24 | struct skl_sst; |
e973e31a SP |
25 | struct sst_dsp_device; |
26 | ||
3582f9ae SP |
27 | /* Intel HD Audio General DSP Registers */ |
28 | #define SKL_ADSP_GEN_BASE 0x0 | |
29 | #define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04) | |
30 | #define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08) | |
31 | #define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C) | |
32 | #define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10) | |
33 | #define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14) | |
34 | ||
35 | /* Intel HD Audio Inter-Processor Communication Registers */ | |
36 | #define SKL_ADSP_IPC_BASE 0x40 | |
37 | #define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00) | |
38 | #define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04) | |
39 | #define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08) | |
40 | #define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C) | |
41 | #define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10) | |
42 | ||
43 | /* HIPCI */ | |
44 | #define SKL_ADSP_REG_HIPCI_BUSY BIT(31) | |
45 | ||
46 | /* HIPCIE */ | |
47 | #define SKL_ADSP_REG_HIPCIE_DONE BIT(30) | |
48 | ||
49 | /* HIPCCTL */ | |
50 | #define SKL_ADSP_REG_HIPCCTL_DONE BIT(1) | |
51 | #define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0) | |
52 | ||
53 | /* HIPCT */ | |
54 | #define SKL_ADSP_REG_HIPCT_BUSY BIT(31) | |
55 | ||
39fa37d5 VK |
56 | /* FW base IDs */ |
57 | #define SKL_INSTANCE_ID 0 | |
58 | #define SKL_BASE_FW_MODULE_ID 0 | |
59 | ||
3582f9ae SP |
60 | /* Intel HD Audio SRAM Window 1 */ |
61 | #define SKL_ADSP_SRAM1_BASE 0xA000 | |
62 | ||
63 | #define SKL_ADSP_MMIO_LEN 0x10000 | |
64 | ||
c99b8056 | 65 | #define SKL_ADSP_W0_STAT_SZ 0x1000 |
3582f9ae | 66 | |
c99b8056 | 67 | #define SKL_ADSP_W0_UP_SZ 0x1000 |
3582f9ae SP |
68 | |
69 | #define SKL_ADSP_W1_SZ 0x1000 | |
70 | ||
a750ba5f SP |
71 | #define SKL_FW_STS_MASK 0xf |
72 | ||
73 | #define SKL_FW_INIT 0x1 | |
74 | #define SKL_FW_RFW_START 0xf | |
75 | ||
3582f9ae SP |
76 | #define SKL_ADSPIC_IPC 1 |
77 | #define SKL_ADSPIS_IPC 1 | |
78 | ||
e973e31a SP |
79 | /* ADSPCS - Audio DSP Control & Status */ |
80 | #define SKL_DSP_CORES 1 | |
81 | #define SKL_DSP_CORE0_MASK 1 | |
82 | #define SKL_DSP_CORES_MASK ((1 << SKL_DSP_CORES) - 1) | |
83 | ||
84 | /* Core Reset - asserted high */ | |
85 | #define SKL_ADSPCS_CRST_SHIFT 0 | |
86 | #define SKL_ADSPCS_CRST_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_CRST_SHIFT) | |
87 | #define SKL_ADSPCS_CRST(x) ((x << SKL_ADSPCS_CRST_SHIFT) & SKL_ADSPCS_CRST_MASK) | |
88 | ||
89 | /* Core run/stall - when set to '1' core is stalled */ | |
90 | #define SKL_ADSPCS_CSTALL_SHIFT 8 | |
91 | #define SKL_ADSPCS_CSTALL_MASK (SKL_DSP_CORES_MASK << \ | |
92 | SKL_ADSPCS_CSTALL_SHIFT) | |
93 | #define SKL_ADSPCS_CSTALL(x) ((x << SKL_ADSPCS_CSTALL_SHIFT) & \ | |
94 | SKL_ADSPCS_CSTALL_MASK) | |
95 | ||
96 | /* Set Power Active - when set to '1' turn cores on */ | |
97 | #define SKL_ADSPCS_SPA_SHIFT 16 | |
98 | #define SKL_ADSPCS_SPA_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_SPA_SHIFT) | |
99 | #define SKL_ADSPCS_SPA(x) ((x << SKL_ADSPCS_SPA_SHIFT) & SKL_ADSPCS_SPA_MASK) | |
100 | ||
101 | /* Current Power Active - power status of cores, set by hardware */ | |
102 | #define SKL_ADSPCS_CPA_SHIFT 24 | |
103 | #define SKL_ADSPCS_CPA_MASK (SKL_DSP_CORES_MASK << SKL_ADSPCS_CPA_SHIFT) | |
104 | #define SKL_ADSPCS_CPA(x) ((x << SKL_ADSPCS_CPA_SHIFT) & SKL_ADSPCS_CPA_MASK) | |
105 | ||
106 | #define SST_DSP_POWER_D0 0x0 /* full On */ | |
107 | #define SST_DSP_POWER_D3 0x3 /* Off */ | |
108 | ||
109 | enum skl_dsp_states { | |
110 | SKL_DSP_RUNNING = 1, | |
111 | SKL_DSP_RESET, | |
112 | }; | |
113 | ||
114 | struct skl_dsp_fw_ops { | |
115 | int (*load_fw)(struct sst_dsp *ctx); | |
116 | /* FW module parser/loader */ | |
117 | int (*parse_fw)(struct sst_dsp *ctx); | |
118 | int (*set_state_D0)(struct sst_dsp *ctx); | |
119 | int (*set_state_D3)(struct sst_dsp *ctx); | |
a750ba5f | 120 | unsigned int (*get_fw_errcode)(struct sst_dsp *ctx); |
6c5768b3 D |
121 | int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, char *mod_name); |
122 | int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id); | |
123 | ||
e973e31a SP |
124 | }; |
125 | ||
b6626802 SP |
126 | struct skl_dsp_loader_ops { |
127 | int (*alloc_dma_buf)(struct device *dev, | |
128 | struct snd_dma_buffer *dmab, size_t size); | |
129 | int (*free_dma_buf)(struct device *dev, | |
130 | struct snd_dma_buffer *dmab); | |
131 | }; | |
132 | ||
6c5768b3 D |
133 | struct skl_load_module_info { |
134 | u16 mod_id; | |
135 | const struct firmware *fw; | |
136 | }; | |
137 | ||
138 | struct skl_module_table { | |
139 | struct skl_load_module_info *mod_info; | |
140 | unsigned int usage_cnt; | |
141 | struct list_head list; | |
142 | }; | |
143 | ||
3e40a784 VK |
144 | void skl_cldma_process_intr(struct sst_dsp *ctx); |
145 | void skl_cldma_int_disable(struct sst_dsp *ctx); | |
146 | int skl_cldma_prepare(struct sst_dsp *ctx); | |
147 | ||
e973e31a SP |
148 | void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state); |
149 | struct sst_dsp *skl_dsp_ctx_init(struct device *dev, | |
150 | struct sst_dsp_device *sst_dev, int irq); | |
151 | int skl_dsp_disable_core(struct sst_dsp *ctx); | |
152 | bool is_skl_dsp_running(struct sst_dsp *ctx); | |
153 | irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id); | |
154 | int skl_dsp_wake(struct sst_dsp *ctx); | |
155 | int skl_dsp_sleep(struct sst_dsp *ctx); | |
156 | void skl_dsp_free(struct sst_dsp *dsp); | |
157 | ||
158 | int skl_dsp_boot(struct sst_dsp *ctx); | |
a750ba5f | 159 | int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, |
aecf6fd8 VK |
160 | const char *fw_name, struct skl_dsp_loader_ops dsp_ops, |
161 | struct skl_sst **dsp); | |
a750ba5f | 162 | void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx); |
e973e31a | 163 | |
3582f9ae | 164 | #endif /*__SKL_SST_DSP_H__*/ |