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1 | /* |
2 | * Intel SKL IPC Support | |
3 | * | |
4 | * Copyright (C) 2014-15, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as version 2, as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | */ | |
15 | ||
16 | #ifndef __SKL_IPC_H | |
17 | #define __SKL_IPC_H | |
18 | ||
19 | #include <linux/kthread.h> | |
20 | #include <linux/irqreturn.h> | |
21 | #include "../common/sst-ipc.h" | |
22 | ||
23 | struct sst_dsp; | |
24 | struct skl_sst; | |
25 | struct sst_generic_ipc; | |
26 | ||
27 | enum skl_ipc_pipeline_state { | |
28 | PPL_INVALID_STATE = 0, | |
29 | PPL_UNINITIALIZED = 1, | |
30 | PPL_RESET = 2, | |
31 | PPL_PAUSED = 3, | |
32 | PPL_RUNNING = 4, | |
33 | PPL_ERROR_STOP = 5, | |
34 | PPL_SAVED = 6, | |
35 | PPL_RESTORED = 7 | |
36 | }; | |
37 | ||
38 | struct skl_ipc_dxstate_info { | |
39 | u32 core_mask; | |
40 | u32 dx_mask; | |
41 | }; | |
42 | ||
43 | struct skl_ipc_header { | |
44 | u32 primary; | |
45 | u32 extension; | |
46 | }; | |
47 | ||
48 | struct skl_sst { | |
49 | struct device *dev; | |
50 | struct sst_dsp *dsp; | |
51 | ||
52 | /* boot */ | |
53 | wait_queue_head_t boot_wait; | |
54 | bool boot_complete; | |
55 | ||
56 | /* IPC messaging */ | |
57 | struct sst_generic_ipc ipc; | |
58 | }; | |
59 | ||
60 | struct skl_ipc_init_instance_msg { | |
61 | u32 module_id; | |
62 | u32 instance_id; | |
63 | u16 param_data_size; | |
64 | u8 ppl_instance_id; | |
65 | u8 core_id; | |
66 | }; | |
67 | ||
68 | struct skl_ipc_bind_unbind_msg { | |
69 | u32 module_id; | |
70 | u32 instance_id; | |
71 | u32 dst_module_id; | |
72 | u32 dst_instance_id; | |
73 | u8 src_queue; | |
74 | u8 dst_queue; | |
75 | bool bind; | |
76 | }; | |
77 | ||
78 | struct skl_ipc_large_config_msg { | |
79 | u32 module_id; | |
80 | u32 instance_id; | |
81 | u32 large_param_id; | |
82 | u32 param_data_size; | |
83 | }; | |
84 | ||
85 | #define SKL_IPC_BOOT_MSECS 3000 | |
86 | ||
87 | #define SKL_IPC_D3_MASK 0 | |
88 | #define SKL_IPC_D0_MASK 3 | |
89 | ||
90 | irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context); | |
91 | ||
92 | int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc, | |
93 | u16 ppl_mem_size, u8 ppl_type, u8 instance_id); | |
94 | ||
95 | int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id); | |
96 | ||
97 | int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc, | |
98 | u8 instance_id, enum skl_ipc_pipeline_state state); | |
99 | ||
100 | int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc, | |
101 | u8 instance_id, int dma_id); | |
102 | ||
103 | int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id); | |
104 | ||
105 | int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc, | |
106 | struct skl_ipc_init_instance_msg *msg, void *param_data); | |
107 | ||
108 | int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc, | |
109 | struct skl_ipc_bind_unbind_msg *msg); | |
110 | ||
111 | int skl_ipc_set_dx(struct sst_generic_ipc *ipc, | |
112 | u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx); | |
113 | ||
114 | int skl_ipc_set_large_config(struct sst_generic_ipc *ipc, | |
115 | struct skl_ipc_large_config_msg *msg, u32 *param); | |
116 | ||
117 | void skl_ipc_int_enable(struct sst_dsp *dsp); | |
118 | void skl_ipc_op_int_enable(struct sst_dsp *ctx); | |
84c9e283 | 119 | void skl_ipc_op_int_disable(struct sst_dsp *ctx); |
b81fd263 SP |
120 | void skl_ipc_int_disable(struct sst_dsp *dsp); |
121 | ||
122 | bool skl_ipc_int_status(struct sst_dsp *dsp); | |
123 | void skl_ipc_free(struct sst_generic_ipc *ipc); | |
124 | int skl_ipc_init(struct device *dev, struct skl_sst *skl); | |
125 | ||
126 | #endif /* __SKL_IPC_H */ |