[deliverable/linux.git] / sound / soc / intel / skylake / skl-sst-ipc.h

/*
 * Intel SKL IPC Support
 *
 * Copyright (C) 2014-15, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */

#ifndef __SKL_IPC_H
#define __SKL_IPC_H

#include <linux/kthread.h>
#include <linux/irqreturn.h>
#include "../common/sst-ipc.h"

struct sst_dsp;
struct skl_sst;
struct sst_generic_ipc;

enum skl_ipc_pipeline_state {
	PPL_INVALID_STATE =	0,
	PPL_UNINITIALIZED =	1,
	PPL_RESET =		2,
	PPL_PAUSED =		3,
	PPL_RUNNING =		4,
	PPL_ERROR_STOP =	5,
	PPL_SAVED =		6,
	PPL_RESTORED =		7
};

struct skl_ipc_dxstate_info {
	u32 core_mask;
	u32 dx_mask;
};

struct skl_ipc_header {
	u32 primary;
	u32 extension;
};

#define SKL_DSP_CORES_MAX  2

struct skl_dsp_cores {
	unsigned int count;
	enum skl_dsp_states state[SKL_DSP_CORES_MAX];
	int usage_count[SKL_DSP_CORES_MAX];
};

struct skl_sst {
	struct device *dev;
	struct sst_dsp *dsp;

	/* boot */
	wait_queue_head_t boot_wait;
	bool boot_complete;

	/* IPC messaging */
	struct sst_generic_ipc ipc;

	/* callback for miscbdge */
	void (*enable_miscbdcge)(struct device *dev, bool enable);
	/*Is CGCTL.MISCBDCGE disabled*/
	bool miscbdcg_disabled;

	/* Populate module information */
	struct list_head uuid_list;

	/* Is firmware loaded */
	bool fw_loaded;

	/* first boot ? */
	bool is_first_boot;

	/* multi-core */
	struct skl_dsp_cores cores;
};

struct skl_ipc_init_instance_msg {
	u32 module_id;
	u32 instance_id;
	u16 param_data_size;
	u8 ppl_instance_id;
	u8 core_id;
};

struct skl_ipc_bind_unbind_msg {
	u32 module_id;
	u32 instance_id;
	u32 dst_module_id;
	u32 dst_instance_id;
	u8 src_queue;
	u8 dst_queue;
	bool bind;
};

struct skl_ipc_large_config_msg {
	u32 module_id;
	u32 instance_id;
	u32 large_param_id;
	u32 param_data_size;
};

#define SKL_IPC_BOOT_MSECS		3000

#define SKL_IPC_D3_MASK	0
#define SKL_IPC_D0_MASK	3

irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context);

int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc,
		u16 ppl_mem_size, u8 ppl_type, u8 instance_id);

int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id);

int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc,
		u8 instance_id,	enum skl_ipc_pipeline_state state);

int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc,
		u8 instance_id, int dma_id);

int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id);

int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc,
		struct skl_ipc_init_instance_msg *msg, void *param_data);

int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc,
		struct skl_ipc_bind_unbind_msg *msg);

int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
				u8 module_cnt, void *data);

int skl_ipc_unload_modules(struct sst_generic_ipc *ipc,
				u8 module_cnt, void *data);

int skl_ipc_set_dx(struct sst_generic_ipc *ipc,
		u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx);

int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
		struct skl_ipc_large_config_msg *msg, u32 *param);

int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
		struct skl_ipc_large_config_msg *msg, u32 *param);

void skl_ipc_int_enable(struct sst_dsp *dsp);
void skl_ipc_op_int_enable(struct sst_dsp *ctx);
void skl_ipc_op_int_disable(struct sst_dsp *ctx);
void skl_ipc_int_disable(struct sst_dsp *dsp);

bool skl_ipc_int_status(struct sst_dsp *dsp);
void skl_ipc_free(struct sst_generic_ipc *ipc);
int skl_ipc_init(struct device *dev, struct skl_sst *skl);
void skl_clear_module_cnt(struct sst_dsp *ctx);

#endif /* __SKL_IPC_H */
Commit	Line	Data
b81fd263 SP	1	/*
	2	* Intel SKL IPC Support
	3	*
	4	* Copyright (C) 2014-15, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as version 2, as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* General Public License for more details.
	14	*/
	15
	16	#ifndef __SKL_IPC_H
	17	#define __SKL_IPC_H
	18
	19	#include <linux/kthread.h>
	20	#include <linux/irqreturn.h>
	21	#include "../common/sst-ipc.h"
	22
	23	struct sst_dsp;
	24	struct skl_sst;
	25	struct sst_generic_ipc;
	26
	27	enum skl_ipc_pipeline_state {
	28	PPL_INVALID_STATE = 0,
	29	PPL_UNINITIALIZED = 1,
	30	PPL_RESET = 2,
	31	PPL_PAUSED = 3,
	32	PPL_RUNNING = 4,
	33	PPL_ERROR_STOP = 5,
	34	PPL_SAVED = 6,
	35	PPL_RESTORED = 7
	36	};
	37
	38	struct skl_ipc_dxstate_info {
	39	u32 core_mask;
	40	u32 dx_mask;
	41	};
	42
	43	struct skl_ipc_header {
	44	u32 primary;
	45	u32 extension;
	46	};
	47
052f103c J	48	#define SKL_DSP_CORES_MAX 2
	49
	50	struct skl_dsp_cores {
	51	unsigned int count;
	52	enum skl_dsp_states state[SKL_DSP_CORES_MAX];
	53	int usage_count[SKL_DSP_CORES_MAX];
	54	};
	55
b81fd263 SP	56	struct skl_sst {
	57	struct device *dev;
	58	struct sst_dsp *dsp;
	59
	60	/* boot */
	61	wait_queue_head_t boot_wait;
	62	bool boot_complete;
	63
	64	/* IPC messaging */
	65	struct sst_generic_ipc ipc;
0c8ba9d2 J	66
	67	/* callback for miscbdge */
	68	void (enable_miscbdcge)(struct device dev, bool enable);
	69	/Is CGCTL.MISCBDCGE disabled/
	70	bool miscbdcg_disabled;
ea6b3e94 SN	71
	72	/* Populate module information */
	73	struct list_head uuid_list;
1665c177 J	74
	75	/* Is firmware loaded */
	76	bool fw_loaded;
052f103c	77
78cdbbda VK	78	/* first boot ? */
	79	bool is_first_boot;
	80
052f103c J	81	/* multi-core */
052f103c J	82	struct skl_dsp_cores cores;
b81fd263 SP	83	};
	84
	85	struct skl_ipc_init_instance_msg {
	86	u32 module_id;
	87	u32 instance_id;
	88	u16 param_data_size;
	89	u8 ppl_instance_id;
	90	u8 core_id;
	91	};
	92
	93	struct skl_ipc_bind_unbind_msg {
	94	u32 module_id;
	95	u32 instance_id;
	96	u32 dst_module_id;
	97	u32 dst_instance_id;
	98	u8 src_queue;
	99	u8 dst_queue;
	100	bool bind;
	101	};
	102
	103	struct skl_ipc_large_config_msg {
	104	u32 module_id;
	105	u32 instance_id;
	106	u32 large_param_id;
	107	u32 param_data_size;
	108	};
	109
	110	#define SKL_IPC_BOOT_MSECS 3000
	111
	112	#define SKL_IPC_D3_MASK 0
	113	#define SKL_IPC_D0_MASK 3
	114
	115	irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context);
	116
	117	int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc,
	118	u16 ppl_mem_size, u8 ppl_type, u8 instance_id);
	119
	120	int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id);
	121
	122	int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc,
	123	u8 instance_id, enum skl_ipc_pipeline_state state);
	124
	125	int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc,
	126	u8 instance_id, int dma_id);
	127
	128	int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id);
	129
	130	int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc,
	131	struct skl_ipc_init_instance_msg msg, void param_data);
	132
	133	int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc,
	134	struct skl_ipc_bind_unbind_msg *msg);
	135
6c5768b3 D	136	int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
	137	u8 module_cnt, void *data);
	138
	139	int skl_ipc_unload_modules(struct sst_generic_ipc *ipc,
	140	u8 module_cnt, void *data);
	141
b81fd263 SP	142	int skl_ipc_set_dx(struct sst_generic_ipc *ipc,
	143	u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx);
	144
	145	int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
	146	struct skl_ipc_large_config_msg msg, u32 param);
	147
cce1c7f3 MJ	148	int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
	149	struct skl_ipc_large_config_msg msg, u32 param);
	150
b81fd263 SP	151	void skl_ipc_int_enable(struct sst_dsp *dsp);
b81fd263 SP	152	void skl_ipc_op_int_enable(struct sst_dsp *ctx);
84c9e283	153	void skl_ipc_op_int_disable(struct sst_dsp *ctx);
b81fd263 SP	154	void skl_ipc_int_disable(struct sst_dsp *dsp);
	155
	156	bool skl_ipc_int_status(struct sst_dsp *dsp);
	157	void skl_ipc_free(struct sst_generic_ipc *ipc);
	158	int skl_ipc_init(struct device dev, struct skl_sst skl);
fe3f4442	159	void skl_clear_module_cnt(struct sst_dsp *ctx);
b81fd263 SP	160
b81fd263 SP	161	#endif /* __SKL_IPC_H */