Commit | Line | Data |
---|---|---|
b81fd263 SP |
1 | /* |
2 | * Intel SKL IPC Support | |
3 | * | |
4 | * Copyright (C) 2014-15, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as version 2, as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | */ | |
15 | ||
16 | #ifndef __SKL_IPC_H | |
17 | #define __SKL_IPC_H | |
18 | ||
19 | #include <linux/kthread.h> | |
20 | #include <linux/irqreturn.h> | |
21 | #include "../common/sst-ipc.h" | |
22 | ||
23 | struct sst_dsp; | |
24 | struct skl_sst; | |
25 | struct sst_generic_ipc; | |
26 | ||
27 | enum skl_ipc_pipeline_state { | |
28 | PPL_INVALID_STATE = 0, | |
29 | PPL_UNINITIALIZED = 1, | |
30 | PPL_RESET = 2, | |
31 | PPL_PAUSED = 3, | |
32 | PPL_RUNNING = 4, | |
33 | PPL_ERROR_STOP = 5, | |
34 | PPL_SAVED = 6, | |
35 | PPL_RESTORED = 7 | |
36 | }; | |
37 | ||
38 | struct skl_ipc_dxstate_info { | |
39 | u32 core_mask; | |
40 | u32 dx_mask; | |
41 | }; | |
42 | ||
43 | struct skl_ipc_header { | |
44 | u32 primary; | |
45 | u32 extension; | |
46 | }; | |
47 | ||
052f103c J |
48 | #define SKL_DSP_CORES_MAX 2 |
49 | ||
50 | struct skl_dsp_cores { | |
51 | unsigned int count; | |
52 | enum skl_dsp_states state[SKL_DSP_CORES_MAX]; | |
53 | int usage_count[SKL_DSP_CORES_MAX]; | |
54 | }; | |
55 | ||
b81fd263 SP |
56 | struct skl_sst { |
57 | struct device *dev; | |
58 | struct sst_dsp *dsp; | |
59 | ||
60 | /* boot */ | |
61 | wait_queue_head_t boot_wait; | |
62 | bool boot_complete; | |
63 | ||
64 | /* IPC messaging */ | |
65 | struct sst_generic_ipc ipc; | |
0c8ba9d2 J |
66 | |
67 | /* callback for miscbdge */ | |
68 | void (*enable_miscbdcge)(struct device *dev, bool enable); | |
69 | /*Is CGCTL.MISCBDCGE disabled*/ | |
70 | bool miscbdcg_disabled; | |
ea6b3e94 SN |
71 | |
72 | /* Populate module information */ | |
73 | struct list_head uuid_list; | |
1665c177 J |
74 | |
75 | /* Is firmware loaded */ | |
76 | bool fw_loaded; | |
052f103c J |
77 | |
78 | /* multi-core */ | |
79 | struct skl_dsp_cores cores; | |
b81fd263 SP |
80 | }; |
81 | ||
82 | struct skl_ipc_init_instance_msg { | |
83 | u32 module_id; | |
84 | u32 instance_id; | |
85 | u16 param_data_size; | |
86 | u8 ppl_instance_id; | |
87 | u8 core_id; | |
88 | }; | |
89 | ||
90 | struct skl_ipc_bind_unbind_msg { | |
91 | u32 module_id; | |
92 | u32 instance_id; | |
93 | u32 dst_module_id; | |
94 | u32 dst_instance_id; | |
95 | u8 src_queue; | |
96 | u8 dst_queue; | |
97 | bool bind; | |
98 | }; | |
99 | ||
100 | struct skl_ipc_large_config_msg { | |
101 | u32 module_id; | |
102 | u32 instance_id; | |
103 | u32 large_param_id; | |
104 | u32 param_data_size; | |
105 | }; | |
106 | ||
107 | #define SKL_IPC_BOOT_MSECS 3000 | |
108 | ||
109 | #define SKL_IPC_D3_MASK 0 | |
110 | #define SKL_IPC_D0_MASK 3 | |
111 | ||
112 | irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context); | |
113 | ||
114 | int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc, | |
115 | u16 ppl_mem_size, u8 ppl_type, u8 instance_id); | |
116 | ||
117 | int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id); | |
118 | ||
119 | int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc, | |
120 | u8 instance_id, enum skl_ipc_pipeline_state state); | |
121 | ||
122 | int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc, | |
123 | u8 instance_id, int dma_id); | |
124 | ||
125 | int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id); | |
126 | ||
127 | int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc, | |
128 | struct skl_ipc_init_instance_msg *msg, void *param_data); | |
129 | ||
130 | int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc, | |
131 | struct skl_ipc_bind_unbind_msg *msg); | |
132 | ||
6c5768b3 D |
133 | int skl_ipc_load_modules(struct sst_generic_ipc *ipc, |
134 | u8 module_cnt, void *data); | |
135 | ||
136 | int skl_ipc_unload_modules(struct sst_generic_ipc *ipc, | |
137 | u8 module_cnt, void *data); | |
138 | ||
b81fd263 SP |
139 | int skl_ipc_set_dx(struct sst_generic_ipc *ipc, |
140 | u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx); | |
141 | ||
142 | int skl_ipc_set_large_config(struct sst_generic_ipc *ipc, | |
143 | struct skl_ipc_large_config_msg *msg, u32 *param); | |
144 | ||
cce1c7f3 MJ |
145 | int skl_ipc_get_large_config(struct sst_generic_ipc *ipc, |
146 | struct skl_ipc_large_config_msg *msg, u32 *param); | |
147 | ||
b81fd263 SP |
148 | void skl_ipc_int_enable(struct sst_dsp *dsp); |
149 | void skl_ipc_op_int_enable(struct sst_dsp *ctx); | |
84c9e283 | 150 | void skl_ipc_op_int_disable(struct sst_dsp *ctx); |
b81fd263 SP |
151 | void skl_ipc_int_disable(struct sst_dsp *dsp); |
152 | ||
153 | bool skl_ipc_int_status(struct sst_dsp *dsp); | |
154 | void skl_ipc_free(struct sst_generic_ipc *ipc); | |
155 | int skl_ipc_init(struct device *dev, struct skl_sst *skl); | |
fe3f4442 | 156 | void skl_clear_module_cnt(struct sst_dsp *ctx); |
b81fd263 SP |
157 | |
158 | #endif /* __SKL_IPC_H */ |