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d8c2dab8 JK |
1 | /* |
2 | * skl.c - Implementation of ASoC Intel SKL HD Audio driver | |
3 | * | |
4 | * Copyright (C) 2014-2015 Intel Corp | |
5 | * Author: Jeeja KP <jeeja.kp@intel.com> | |
6 | * | |
7 | * Derived mostly from Intel HDA driver with following copyrights: | |
8 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
9 | * PeiSen Hou <pshou@realtek.com.tw> | |
10 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; version 2 of the License. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/platform_device.h> | |
d8018361 | 28 | #include <linux/firmware.h> |
d8c2dab8 | 29 | #include <sound/pcm.h> |
cc18c5fd | 30 | #include "../common/sst-acpi.h" |
6980c057 VK |
31 | #include <sound/hda_register.h> |
32 | #include <sound/hdaudio.h> | |
33 | #include <sound/hda_i915.h> | |
d8c2dab8 | 34 | #include "skl.h" |
0c8ba9d2 J |
35 | #include "skl-sst-dsp.h" |
36 | #include "skl-sst-ipc.h" | |
d8c2dab8 | 37 | |
f65cf7d6 YZ |
38 | static struct skl_machine_pdata skl_dmic_data; |
39 | ||
d8c2dab8 JK |
40 | /* |
41 | * initialize the PCI registers | |
42 | */ | |
43 | static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, | |
44 | unsigned char mask, unsigned char val) | |
45 | { | |
46 | unsigned char data; | |
47 | ||
48 | pci_read_config_byte(pci, reg, &data); | |
49 | data &= ~mask; | |
50 | data |= (val & mask); | |
51 | pci_write_config_byte(pci, reg, data); | |
52 | } | |
53 | ||
54 | static void skl_init_pci(struct skl *skl) | |
55 | { | |
56 | struct hdac_ext_bus *ebus = &skl->ebus; | |
57 | ||
58 | /* | |
59 | * Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | |
60 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
61 | * Ensuring these bits are 0 clears playback static on some HD Audio | |
62 | * codecs. | |
63 | * The PCI register TCSEL is defined in the Intel manuals. | |
64 | */ | |
65 | dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n"); | |
66 | skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0); | |
67 | } | |
68 | ||
0c8ba9d2 J |
69 | static void update_pci_dword(struct pci_dev *pci, |
70 | unsigned int reg, u32 mask, u32 val) | |
71 | { | |
72 | u32 data = 0; | |
73 | ||
74 | pci_read_config_dword(pci, reg, &data); | |
75 | data &= ~mask; | |
76 | data |= (val & mask); | |
77 | pci_write_config_dword(pci, reg, data); | |
78 | } | |
79 | ||
80 | /* | |
81 | * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits | |
82 | * | |
83 | * @dev: device pointer | |
84 | * @enable: enable/disable flag | |
85 | */ | |
86 | static void skl_enable_miscbdcge(struct device *dev, bool enable) | |
87 | { | |
88 | struct pci_dev *pci = to_pci_dev(dev); | |
89 | u32 val; | |
90 | ||
91 | val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; | |
92 | ||
93 | update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); | |
94 | } | |
95 | ||
96 | /* | |
97 | * While performing reset, controller may not come back properly causing | |
98 | * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset | |
99 | * (init chip) and then again set CGCTL.MISCBDCGE to 1 | |
100 | */ | |
101 | static int skl_init_chip(struct hdac_bus *bus, bool full_reset) | |
102 | { | |
103 | int ret; | |
104 | ||
105 | skl_enable_miscbdcge(bus->dev, false); | |
106 | ret = snd_hdac_bus_init_chip(bus, full_reset); | |
107 | skl_enable_miscbdcge(bus->dev, true); | |
108 | ||
109 | return ret; | |
110 | } | |
111 | ||
d8c2dab8 JK |
112 | /* called from IRQ */ |
113 | static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr) | |
114 | { | |
115 | snd_pcm_period_elapsed(hstr->substream); | |
116 | } | |
117 | ||
118 | static irqreturn_t skl_interrupt(int irq, void *dev_id) | |
119 | { | |
120 | struct hdac_ext_bus *ebus = dev_id; | |
121 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
122 | u32 status; | |
123 | ||
124 | if (!pm_runtime_active(bus->dev)) | |
125 | return IRQ_NONE; | |
126 | ||
127 | spin_lock(&bus->reg_lock); | |
128 | ||
129 | status = snd_hdac_chip_readl(bus, INTSTS); | |
130 | if (status == 0 || status == 0xffffffff) { | |
131 | spin_unlock(&bus->reg_lock); | |
132 | return IRQ_NONE; | |
133 | } | |
134 | ||
135 | /* clear rirb int */ | |
136 | status = snd_hdac_chip_readb(bus, RIRBSTS); | |
137 | if (status & RIRB_INT_MASK) { | |
138 | if (status & RIRB_INT_RESPONSE) | |
139 | snd_hdac_bus_update_rirb(bus); | |
140 | snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); | |
141 | } | |
142 | ||
143 | spin_unlock(&bus->reg_lock); | |
144 | ||
145 | return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED; | |
146 | } | |
147 | ||
148 | static irqreturn_t skl_threaded_handler(int irq, void *dev_id) | |
149 | { | |
150 | struct hdac_ext_bus *ebus = dev_id; | |
151 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
152 | u32 status; | |
153 | ||
154 | status = snd_hdac_chip_readl(bus, INTSTS); | |
155 | ||
156 | snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update); | |
157 | ||
158 | return IRQ_HANDLED; | |
159 | } | |
160 | ||
161 | static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect) | |
162 | { | |
163 | struct skl *skl = ebus_to_skl(ebus); | |
164 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
165 | int ret; | |
166 | ||
167 | ret = request_threaded_irq(skl->pci->irq, skl_interrupt, | |
168 | skl_threaded_handler, | |
169 | IRQF_SHARED, | |
170 | KBUILD_MODNAME, ebus); | |
171 | if (ret) { | |
172 | dev_err(bus->dev, | |
173 | "unable to grab IRQ %d, disabling device\n", | |
174 | skl->pci->irq); | |
175 | return ret; | |
176 | } | |
177 | ||
178 | bus->irq = skl->pci->irq; | |
179 | pci_intx(skl->pci, 1); | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
61722f44 JK |
184 | #ifdef CONFIG_PM |
185 | static int _skl_suspend(struct hdac_ext_bus *ebus) | |
186 | { | |
187 | struct skl *skl = ebus_to_skl(ebus); | |
188 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
189 | int ret; | |
190 | ||
191 | snd_hdac_ext_bus_link_power_down_all(ebus); | |
192 | ||
193 | ret = skl_suspend_dsp(skl); | |
194 | if (ret < 0) | |
195 | return ret; | |
196 | ||
197 | snd_hdac_bus_stop_chip(bus); | |
0c8ba9d2 | 198 | skl_enable_miscbdcge(bus->dev, false); |
61722f44 | 199 | snd_hdac_bus_enter_link_reset(bus); |
0c8ba9d2 | 200 | skl_enable_miscbdcge(bus->dev, true); |
61722f44 JK |
201 | |
202 | return 0; | |
203 | } | |
204 | ||
205 | static int _skl_resume(struct hdac_ext_bus *ebus) | |
206 | { | |
207 | struct skl *skl = ebus_to_skl(ebus); | |
208 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
209 | ||
210 | skl_init_pci(skl); | |
0c8ba9d2 | 211 | skl_init_chip(bus, true); |
61722f44 JK |
212 | |
213 | return skl_resume_dsp(skl); | |
214 | } | |
215 | #endif | |
216 | ||
d8c2dab8 JK |
217 | #ifdef CONFIG_PM_SLEEP |
218 | /* | |
219 | * power management | |
220 | */ | |
221 | static int skl_suspend(struct device *dev) | |
222 | { | |
223 | struct pci_dev *pci = to_pci_dev(dev); | |
224 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
4557c305 | 225 | struct skl *skl = ebus_to_skl(ebus); |
1f4956fd | 226 | struct hdac_bus *bus = ebus_to_hbus(ebus); |
af037412 | 227 | int ret = 0; |
d8c2dab8 | 228 | |
4557c305 JK |
229 | /* |
230 | * Do not suspend if streams which are marked ignore suspend are | |
231 | * running, we need to save the state for these and continue | |
232 | */ | |
233 | if (skl->supend_active) { | |
cce6c149 | 234 | /* turn off the links and stop the CORB/RIRB DMA if it is On */ |
c2e20cd8 | 235 | snd_hdac_ext_bus_link_power_down_all(ebus); |
cce6c149 VK |
236 | |
237 | if (ebus->cmd_dma_state) | |
238 | snd_hdac_bus_stop_cmd_io(&ebus->bus); | |
239 | ||
1f4956fd | 240 | enable_irq_wake(bus->irq); |
4557c305 JK |
241 | pci_save_state(pci); |
242 | pci_disable_device(pci); | |
4557c305 | 243 | } else { |
af037412 SP |
244 | ret = _skl_suspend(ebus); |
245 | if (ret < 0) | |
246 | return ret; | |
4557c305 | 247 | } |
af037412 SP |
248 | |
249 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { | |
250 | ret = snd_hdac_display_power(bus, false); | |
251 | if (ret < 0) | |
252 | dev_err(bus->dev, | |
253 | "Cannot turn OFF display power on i915\n"); | |
254 | } | |
255 | ||
256 | return ret; | |
d8c2dab8 JK |
257 | } |
258 | ||
259 | static int skl_resume(struct device *dev) | |
260 | { | |
261 | struct pci_dev *pci = to_pci_dev(dev); | |
262 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
4557c305 | 263 | struct skl *skl = ebus_to_skl(ebus); |
1f4956fd | 264 | struct hdac_bus *bus = ebus_to_hbus(ebus); |
cce6c149 | 265 | struct hdac_ext_link *hlink = NULL; |
4557c305 JK |
266 | int ret; |
267 | ||
6980c057 VK |
268 | /* Turned OFF in HDMI codec driver after codec reconfiguration */ |
269 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { | |
270 | ret = snd_hdac_display_power(bus, true); | |
271 | if (ret < 0) { | |
272 | dev_err(bus->dev, | |
273 | "Cannot turn on display power on i915\n"); | |
274 | return ret; | |
275 | } | |
276 | } | |
277 | ||
4557c305 JK |
278 | /* |
279 | * resume only when we are not in suspend active, otherwise need to | |
280 | * restore the device | |
281 | */ | |
282 | if (skl->supend_active) { | |
283 | pci_restore_state(pci); | |
284 | ret = pci_enable_device(pci); | |
c2e20cd8 | 285 | snd_hdac_ext_bus_link_power_up_all(ebus); |
1f4956fd | 286 | disable_irq_wake(bus->irq); |
cce6c149 VK |
287 | /* |
288 | * turn On the links which are On before active suspend | |
289 | * and start the CORB/RIRB DMA if On before | |
290 | * active suspend. | |
291 | */ | |
292 | list_for_each_entry(hlink, &ebus->hlink_list, list) { | |
293 | if (hlink->ref_count) | |
294 | snd_hdac_ext_bus_link_power_up(hlink); | |
295 | } | |
296 | ||
297 | if (ebus->cmd_dma_state) | |
298 | snd_hdac_bus_init_cmd_io(&ebus->bus); | |
4557c305 JK |
299 | } else { |
300 | ret = _skl_resume(ebus); | |
cce6c149 VK |
301 | |
302 | /* turn off the links which are off before suspend */ | |
303 | list_for_each_entry(hlink, &ebus->hlink_list, list) { | |
304 | if (!hlink->ref_count) | |
305 | snd_hdac_ext_bus_link_power_down(hlink); | |
306 | } | |
307 | ||
308 | if (!ebus->cmd_dma_state) | |
309 | snd_hdac_bus_stop_cmd_io(&ebus->bus); | |
4557c305 | 310 | } |
d8c2dab8 | 311 | |
4557c305 | 312 | return ret; |
d8c2dab8 JK |
313 | } |
314 | #endif /* CONFIG_PM_SLEEP */ | |
315 | ||
316 | #ifdef CONFIG_PM | |
317 | static int skl_runtime_suspend(struct device *dev) | |
318 | { | |
319 | struct pci_dev *pci = to_pci_dev(dev); | |
320 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
321 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
322 | ||
323 | dev_dbg(bus->dev, "in %s\n", __func__); | |
324 | ||
61722f44 | 325 | return _skl_suspend(ebus); |
d8c2dab8 JK |
326 | } |
327 | ||
328 | static int skl_runtime_resume(struct device *dev) | |
329 | { | |
330 | struct pci_dev *pci = to_pci_dev(dev); | |
331 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
332 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
d8c2dab8 JK |
333 | |
334 | dev_dbg(bus->dev, "in %s\n", __func__); | |
335 | ||
61722f44 | 336 | return _skl_resume(ebus); |
d8c2dab8 JK |
337 | } |
338 | #endif /* CONFIG_PM */ | |
339 | ||
340 | static const struct dev_pm_ops skl_pm = { | |
341 | SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume) | |
342 | SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL) | |
343 | }; | |
344 | ||
345 | /* | |
346 | * destructor | |
347 | */ | |
348 | static int skl_free(struct hdac_ext_bus *ebus) | |
349 | { | |
350 | struct skl *skl = ebus_to_skl(ebus); | |
351 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
352 | ||
353 | skl->init_failed = 1; /* to be sure */ | |
354 | ||
355 | snd_hdac_ext_stop_streams(ebus); | |
356 | ||
357 | if (bus->irq >= 0) | |
358 | free_irq(bus->irq, (void *)bus); | |
d8c2dab8 JK |
359 | snd_hdac_bus_free_stream_pages(bus); |
360 | snd_hdac_stream_free_all(ebus); | |
361 | snd_hdac_link_free_all(ebus); | |
077411e5 VK |
362 | |
363 | if (bus->remap_addr) | |
364 | iounmap(bus->remap_addr); | |
365 | ||
d8c2dab8 JK |
366 | pci_release_regions(skl->pci); |
367 | pci_disable_device(skl->pci); | |
368 | ||
369 | snd_hdac_ext_bus_exit(ebus); | |
370 | ||
5b2fe898 VK |
371 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) |
372 | snd_hdac_i915_exit(&ebus->bus); | |
d8c2dab8 JK |
373 | return 0; |
374 | } | |
375 | ||
cc18c5fd VK |
376 | static int skl_machine_device_register(struct skl *skl, void *driver_data) |
377 | { | |
378 | struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); | |
379 | struct platform_device *pdev; | |
380 | struct sst_acpi_mach *mach = driver_data; | |
381 | int ret; | |
382 | ||
383 | mach = sst_acpi_find_machine(mach); | |
384 | if (mach == NULL) { | |
385 | dev_err(bus->dev, "No matching machine driver found\n"); | |
386 | return -ENODEV; | |
387 | } | |
aecf6fd8 | 388 | skl->fw_name = mach->fw_filename; |
cc18c5fd VK |
389 | |
390 | pdev = platform_device_alloc(mach->drv_name, -1); | |
391 | if (pdev == NULL) { | |
392 | dev_err(bus->dev, "platform device alloc failed\n"); | |
393 | return -EIO; | |
394 | } | |
395 | ||
396 | ret = platform_device_add(pdev); | |
397 | if (ret) { | |
398 | dev_err(bus->dev, "failed to add machine device\n"); | |
399 | platform_device_put(pdev); | |
400 | return -EIO; | |
401 | } | |
f65cf7d6 YZ |
402 | |
403 | if (mach->pdata) | |
404 | dev_set_drvdata(&pdev->dev, mach->pdata); | |
405 | ||
cc18c5fd VK |
406 | skl->i2s_dev = pdev; |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
411 | static void skl_machine_device_unregister(struct skl *skl) | |
412 | { | |
413 | if (skl->i2s_dev) | |
414 | platform_device_unregister(skl->i2s_dev); | |
415 | } | |
416 | ||
d8c2dab8 JK |
417 | static int skl_dmic_device_register(struct skl *skl) |
418 | { | |
419 | struct hdac_bus *bus = ebus_to_hbus(&skl->ebus); | |
420 | struct platform_device *pdev; | |
421 | int ret; | |
422 | ||
423 | /* SKL has one dmic port, so allocate dmic device for this */ | |
424 | pdev = platform_device_alloc("dmic-codec", -1); | |
425 | if (!pdev) { | |
426 | dev_err(bus->dev, "failed to allocate dmic device\n"); | |
427 | return -ENOMEM; | |
428 | } | |
429 | ||
430 | ret = platform_device_add(pdev); | |
431 | if (ret) { | |
432 | dev_err(bus->dev, "failed to add dmic device: %d\n", ret); | |
433 | platform_device_put(pdev); | |
434 | return ret; | |
435 | } | |
436 | skl->dmic_dev = pdev; | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | static void skl_dmic_device_unregister(struct skl *skl) | |
442 | { | |
443 | if (skl->dmic_dev) | |
444 | platform_device_unregister(skl->dmic_dev); | |
445 | } | |
446 | ||
447 | /* | |
448 | * Probe the given codec address | |
449 | */ | |
450 | static int probe_codec(struct hdac_ext_bus *ebus, int addr) | |
451 | { | |
452 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
453 | unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | | |
454 | (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; | |
455 | unsigned int res; | |
456 | ||
457 | mutex_lock(&bus->cmd_mutex); | |
458 | snd_hdac_bus_send_cmd(bus, cmd); | |
459 | snd_hdac_bus_get_response(bus, addr, &res); | |
460 | mutex_unlock(&bus->cmd_mutex); | |
461 | if (res == -1) | |
462 | return -EIO; | |
463 | dev_dbg(bus->dev, "codec #%d probed OK\n", addr); | |
464 | ||
465 | return snd_hdac_ext_bus_device_init(ebus, addr); | |
466 | } | |
467 | ||
468 | /* Codec initialization */ | |
469 | static int skl_codec_create(struct hdac_ext_bus *ebus) | |
470 | { | |
471 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
472 | int c, max_slots; | |
473 | ||
474 | max_slots = HDA_MAX_CODECS; | |
475 | ||
476 | /* First try to probe all given codec slots */ | |
477 | for (c = 0; c < max_slots; c++) { | |
478 | if ((bus->codec_mask & (1 << c))) { | |
479 | if (probe_codec(ebus, c) < 0) { | |
480 | /* | |
481 | * Some BIOSen give you wrong codec addresses | |
482 | * that don't exist | |
483 | */ | |
484 | dev_warn(bus->dev, | |
485 | "Codec #%d probe error; disabling it...\n", c); | |
486 | bus->codec_mask &= ~(1 << c); | |
487 | /* | |
488 | * More badly, accessing to a non-existing | |
489 | * codec often screws up the controller bus, | |
490 | * and disturbs the further communications. | |
491 | * Thus if an error occurs during probing, | |
492 | * better to reset the controller bus to get | |
493 | * back to the sanity state. | |
494 | */ | |
495 | snd_hdac_bus_stop_chip(bus); | |
0c8ba9d2 | 496 | skl_init_chip(bus, true); |
d8c2dab8 JK |
497 | } |
498 | } | |
499 | } | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
504 | static const struct hdac_bus_ops bus_core_ops = { | |
505 | .command = snd_hdac_bus_send_cmd, | |
506 | .get_response = snd_hdac_bus_get_response, | |
507 | }; | |
508 | ||
509 | /* | |
510 | * constructor | |
511 | */ | |
512 | static int skl_create(struct pci_dev *pci, | |
513 | const struct hdac_io_ops *io_ops, | |
514 | struct skl **rskl) | |
515 | { | |
516 | struct skl *skl; | |
517 | struct hdac_ext_bus *ebus; | |
518 | ||
519 | int err; | |
520 | ||
521 | *rskl = NULL; | |
522 | ||
523 | err = pci_enable_device(pci); | |
524 | if (err < 0) | |
525 | return err; | |
526 | ||
527 | skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL); | |
528 | if (!skl) { | |
529 | pci_disable_device(pci); | |
530 | return -ENOMEM; | |
531 | } | |
532 | ebus = &skl->ebus; | |
533 | snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops); | |
534 | ebus->bus.use_posbuf = 1; | |
535 | skl->pci = pci; | |
536 | ||
537 | ebus->bus.bdl_pos_adj = 0; | |
538 | ||
539 | *rskl = skl; | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
6980c057 VK |
544 | static int skl_i915_init(struct hdac_bus *bus) |
545 | { | |
546 | int err; | |
547 | ||
548 | /* | |
549 | * The HDMI codec is in GPU so we need to ensure that it is powered | |
550 | * up and ready for probe | |
551 | */ | |
552 | err = snd_hdac_i915_init(bus); | |
553 | if (err < 0) | |
554 | return err; | |
555 | ||
556 | err = snd_hdac_display_power(bus, true); | |
557 | if (err < 0) { | |
558 | dev_err(bus->dev, "Cannot turn on display power on i915\n"); | |
559 | return err; | |
560 | } | |
561 | ||
562 | return err; | |
563 | } | |
564 | ||
d8c2dab8 JK |
565 | static int skl_first_init(struct hdac_ext_bus *ebus) |
566 | { | |
567 | struct skl *skl = ebus_to_skl(ebus); | |
568 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
569 | struct pci_dev *pci = skl->pci; | |
570 | int err; | |
571 | unsigned short gcap; | |
572 | int cp_streams, pb_streams, start_idx; | |
573 | ||
574 | err = pci_request_regions(pci, "Skylake HD audio"); | |
575 | if (err < 0) | |
576 | return err; | |
577 | ||
578 | bus->addr = pci_resource_start(pci, 0); | |
579 | bus->remap_addr = pci_ioremap_bar(pci, 0); | |
580 | if (bus->remap_addr == NULL) { | |
581 | dev_err(bus->dev, "ioremap error\n"); | |
582 | return -ENXIO; | |
583 | } | |
584 | ||
05057001 JK |
585 | snd_hdac_ext_bus_parse_capabilities(ebus); |
586 | ||
d8c2dab8 JK |
587 | if (skl_acquire_irq(ebus, 0) < 0) |
588 | return -EBUSY; | |
589 | ||
590 | pci_set_master(pci); | |
591 | synchronize_irq(bus->irq); | |
592 | ||
593 | gcap = snd_hdac_chip_readw(bus, GCAP); | |
594 | dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap); | |
595 | ||
596 | /* allow 64bit DMA address if supported by H/W */ | |
597 | if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) { | |
598 | dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64)); | |
599 | } else { | |
600 | dma_set_mask(bus->dev, DMA_BIT_MASK(32)); | |
601 | dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32)); | |
602 | } | |
603 | ||
604 | /* read number of streams from GCAP register */ | |
605 | cp_streams = (gcap >> 8) & 0x0f; | |
606 | pb_streams = (gcap >> 12) & 0x0f; | |
607 | ||
608 | if (!pb_streams && !cp_streams) | |
609 | return -EIO; | |
610 | ||
611 | ebus->num_streams = cp_streams + pb_streams; | |
612 | ||
613 | /* initialize streams */ | |
614 | snd_hdac_ext_stream_init_all | |
615 | (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); | |
616 | start_idx = cp_streams; | |
617 | snd_hdac_ext_stream_init_all | |
618 | (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); | |
619 | ||
620 | err = snd_hdac_bus_alloc_stream_pages(bus); | |
621 | if (err < 0) | |
622 | return err; | |
623 | ||
624 | /* initialize chip */ | |
625 | skl_init_pci(skl); | |
626 | ||
6980c057 VK |
627 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { |
628 | err = skl_i915_init(bus); | |
629 | if (err < 0) | |
630 | return err; | |
631 | } | |
632 | ||
0c8ba9d2 | 633 | skl_init_chip(bus, true); |
d8c2dab8 JK |
634 | |
635 | /* codec detection */ | |
636 | if (!bus->codec_mask) { | |
029890c6 | 637 | dev_info(bus->dev, "no hda codecs found!\n"); |
d8c2dab8 JK |
638 | } |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | static int skl_probe(struct pci_dev *pci, | |
644 | const struct pci_device_id *pci_id) | |
645 | { | |
646 | struct skl *skl; | |
647 | struct hdac_ext_bus *ebus = NULL; | |
648 | struct hdac_bus *bus = NULL; | |
cce6c149 | 649 | struct hdac_ext_link *hlink = NULL; |
d8c2dab8 JK |
650 | int err; |
651 | ||
652 | /* we use ext core ops, so provide NULL for ops here */ | |
653 | err = skl_create(pci, NULL, &skl); | |
654 | if (err < 0) | |
655 | return err; | |
656 | ||
657 | ebus = &skl->ebus; | |
658 | bus = ebus_to_hbus(ebus); | |
659 | ||
660 | err = skl_first_init(ebus); | |
661 | if (err < 0) | |
662 | goto out_free; | |
663 | ||
4b235c43 VK |
664 | skl->pci_id = pci->device; |
665 | ||
87b2bdf0 JK |
666 | skl->nhlt = skl_nhlt_init(bus->dev); |
667 | ||
668 | if (skl->nhlt == NULL) | |
669 | goto out_free; | |
670 | ||
4b235c43 VK |
671 | skl_nhlt_update_topology_bin(skl); |
672 | ||
d8c2dab8 JK |
673 | pci_set_drvdata(skl->pci, ebus); |
674 | ||
f65cf7d6 YZ |
675 | skl_dmic_data.dmic_num = skl_get_dmic_geo(skl); |
676 | ||
05057001 JK |
677 | /* check if dsp is there */ |
678 | if (ebus->ppcap) { | |
cc18c5fd VK |
679 | err = skl_machine_device_register(skl, |
680 | (void *)pci_id->driver_data); | |
681 | if (err < 0) | |
c286b3f9 | 682 | goto out_nhlt_free; |
cc18c5fd | 683 | |
2a29b200 JK |
684 | err = skl_init_dsp(skl); |
685 | if (err < 0) { | |
686 | dev_dbg(bus->dev, "error failed to register dsp\n"); | |
cc18c5fd | 687 | goto out_mach_free; |
2a29b200 | 688 | } |
0c8ba9d2 J |
689 | skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge; |
690 | ||
05057001 | 691 | } |
05057001 JK |
692 | if (ebus->mlcap) |
693 | snd_hdac_ext_bus_get_ml_capabilities(ebus); | |
694 | ||
d8c2dab8 JK |
695 | /* create device for soc dmic */ |
696 | err = skl_dmic_device_register(skl); | |
697 | if (err < 0) | |
2a29b200 | 698 | goto out_dsp_free; |
d8c2dab8 JK |
699 | |
700 | /* register platform dai and controls */ | |
701 | err = skl_platform_register(bus->dev); | |
702 | if (err < 0) | |
703 | goto out_dmic_free; | |
704 | ||
705 | /* create codec instances */ | |
706 | err = skl_codec_create(ebus); | |
707 | if (err < 0) | |
708 | goto out_unregister; | |
709 | ||
6980c057 VK |
710 | if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) { |
711 | err = snd_hdac_display_power(bus, false); | |
712 | if (err < 0) { | |
713 | dev_err(bus->dev, "Cannot turn off display power on i915\n"); | |
714 | return err; | |
715 | } | |
716 | } | |
717 | ||
cce6c149 VK |
718 | /* |
719 | * we are done probling so decrement link counts | |
720 | */ | |
721 | list_for_each_entry(hlink, &ebus->hlink_list, list) | |
722 | snd_hdac_ext_bus_link_put(ebus, hlink); | |
723 | ||
d8c2dab8 | 724 | /*configure PM */ |
d8c2dab8 JK |
725 | pm_runtime_put_noidle(bus->dev); |
726 | pm_runtime_allow(bus->dev); | |
727 | ||
728 | return 0; | |
729 | ||
730 | out_unregister: | |
731 | skl_platform_unregister(bus->dev); | |
732 | out_dmic_free: | |
733 | skl_dmic_device_unregister(skl); | |
2a29b200 JK |
734 | out_dsp_free: |
735 | skl_free_dsp(skl); | |
cc18c5fd VK |
736 | out_mach_free: |
737 | skl_machine_device_unregister(skl); | |
c286b3f9 JK |
738 | out_nhlt_free: |
739 | skl_nhlt_free(skl->nhlt); | |
d8c2dab8 JK |
740 | out_free: |
741 | skl->init_failed = 1; | |
742 | skl_free(ebus); | |
743 | ||
744 | return err; | |
745 | } | |
746 | ||
c5a76a24 JK |
747 | static void skl_shutdown(struct pci_dev *pci) |
748 | { | |
749 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
750 | struct hdac_bus *bus = ebus_to_hbus(ebus); | |
751 | struct hdac_stream *s; | |
752 | struct hdac_ext_stream *stream; | |
753 | struct skl *skl; | |
754 | ||
755 | if (ebus == NULL) | |
756 | return; | |
757 | ||
758 | skl = ebus_to_skl(ebus); | |
759 | ||
760 | if (skl->init_failed) | |
761 | return; | |
762 | ||
763 | snd_hdac_ext_stop_streams(ebus); | |
764 | list_for_each_entry(s, &bus->stream_list, list) { | |
765 | stream = stream_to_hdac_ext_stream(s); | |
766 | snd_hdac_ext_stream_decouple(ebus, stream, false); | |
767 | } | |
768 | ||
769 | snd_hdac_bus_stop_chip(bus); | |
770 | } | |
771 | ||
d8c2dab8 JK |
772 | static void skl_remove(struct pci_dev *pci) |
773 | { | |
774 | struct hdac_ext_bus *ebus = pci_get_drvdata(pci); | |
775 | struct skl *skl = ebus_to_skl(ebus); | |
776 | ||
d8018361 VK |
777 | if (skl->tplg) |
778 | release_firmware(skl->tplg); | |
779 | ||
d8c2dab8 JK |
780 | if (pci_dev_run_wake(pci)) |
781 | pm_runtime_get_noresume(&pci->dev); | |
7373f481 VK |
782 | |
783 | /* codec removal, invoke bus_device_remove */ | |
784 | snd_hdac_ext_bus_device_remove(ebus); | |
785 | ||
d8c2dab8 | 786 | skl_platform_unregister(&pci->dev); |
2a29b200 | 787 | skl_free_dsp(skl); |
cc18c5fd | 788 | skl_machine_device_unregister(skl); |
d8c2dab8 | 789 | skl_dmic_device_unregister(skl); |
c286b3f9 | 790 | skl_nhlt_free(skl->nhlt); |
d8c2dab8 JK |
791 | skl_free(ebus); |
792 | dev_set_drvdata(&pci->dev, NULL); | |
793 | } | |
794 | ||
cc18c5fd VK |
795 | static struct sst_acpi_mach sst_skl_devdata[] = { |
796 | { "INT343A", "skl_alc286s_i2s", "intel/dsp_fw_release.bin", NULL, NULL, NULL }, | |
02cc2355 | 797 | { "INT343B", "skl_nau88l25_ssm4567_i2s", "intel/dsp_fw_release.bin", |
f65cf7d6 | 798 | NULL, NULL, &skl_dmic_data }, |
69b7f9c4 | 799 | { "MX98357A", "skl_nau88l25_max98357a_i2s", "intel/dsp_fw_release.bin", |
f65cf7d6 | 800 | NULL, NULL, &skl_dmic_data }, |
cc18c5fd VK |
801 | {} |
802 | }; | |
803 | ||
b379b1fa SV |
804 | static struct sst_acpi_mach sst_bxtp_devdata[] = { |
805 | { "INT343A", "bxt_alc298s_i2s", "intel/dsp_fw_bxtn.bin", NULL, NULL, NULL }, | |
806 | }; | |
807 | ||
d8c2dab8 JK |
808 | /* PCI IDs */ |
809 | static const struct pci_device_id skl_ids[] = { | |
810 | /* Sunrise Point-LP */ | |
cc18c5fd VK |
811 | { PCI_DEVICE(0x8086, 0x9d70), |
812 | .driver_data = (unsigned long)&sst_skl_devdata}, | |
b379b1fa SV |
813 | /* BXT-P */ |
814 | { PCI_DEVICE(0x8086, 0x5a98), | |
815 | .driver_data = (unsigned long)&sst_bxtp_devdata}, | |
d8c2dab8 JK |
816 | { 0, } |
817 | }; | |
818 | MODULE_DEVICE_TABLE(pci, skl_ids); | |
819 | ||
820 | /* pci_driver definition */ | |
821 | static struct pci_driver skl_driver = { | |
822 | .name = KBUILD_MODNAME, | |
823 | .id_table = skl_ids, | |
824 | .probe = skl_probe, | |
825 | .remove = skl_remove, | |
c5a76a24 | 826 | .shutdown = skl_shutdown, |
d8c2dab8 JK |
827 | .driver = { |
828 | .pm = &skl_pm, | |
829 | }, | |
830 | }; | |
831 | module_pci_driver(skl_driver); | |
832 | ||
833 | MODULE_LICENSE("GPL v2"); | |
834 | MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver"); |