projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a40e693c JK |
1 | /* |
| 2 | * skl.h - HD Audio skylake defintions. | |
| 3 | * | |
| 4 | * Copyright (C) 2015 Intel Corp | |
| 5 | * Author: Jeeja KP <jeeja.kp@intel.com> | |
| 6 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License as published by | |
| 10 | * the Free Software Foundation; version 2 of the License. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, but | |
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | * General Public License for more details. | |
| 16 | * | |
| 17 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
| 18 | * | |
| 19 | */ | |
| 20 | ||
| 21 | #ifndef __SOUND_SOC_SKL_H | |
| 22 | #define __SOUND_SOC_SKL_H | |
| 23 | ||
| 24 | #include <sound/hda_register.h> | |
| 25 | #include <sound/hdaudio_ext.h> | |
| 473eb87a | 26 | #include "skl-nhlt.h" |
| a40e693c JK |
27 | |
| 28 | #define SKL_SUSPEND_DELAY 2000 | |
| 29 | ||
| 30 | /* Vendor Specific Registers */ | |
| 31 | #define AZX_REG_VS_EM1 0x1000 | |
| 32 | #define AZX_REG_VS_INRC 0x1004 | |
| 33 | #define AZX_REG_VS_OUTRC 0x1008 | |
| 34 | #define AZX_REG_VS_FIFOTRK 0x100C | |
| 35 | #define AZX_REG_VS_FIFOTRK2 0x1010 | |
| 36 | #define AZX_REG_VS_EM2 0x1030 | |
| 37 | #define AZX_REG_VS_EM3L 0x1038 | |
| 38 | #define AZX_REG_VS_EM3U 0x103C | |
| 39 | #define AZX_REG_VS_EM4L 0x1040 | |
| 40 | #define AZX_REG_VS_EM4U 0x1044 | |
| 41 | #define AZX_REG_VS_LTRC 0x1048 | |
| 42 | #define AZX_REG_VS_D0I3C 0x104A | |
| 43 | #define AZX_REG_VS_PCE 0x104B | |
| 44 | #define AZX_REG_VS_L2MAGC 0x1050 | |
| 45 | #define AZX_REG_VS_L2LAHPT 0x1054 | |
| 46 | #define AZX_REG_VS_SDXDPIB_XBASE 0x1084 | |
| 47 | #define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20 | |
| 48 | #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 | |
| 49 | #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 | |
| 50 | ||
| e4e2d2f4 JK |
51 | struct skl_dsp_resource { |
| 52 | u32 max_mcps; | |
| 53 | u32 max_mem; | |
| 54 | u32 mcps; | |
| 55 | u32 mem; | |
| 56 | }; | |
| 57 | ||
| a40e693c JK |
58 | struct skl { |
| 59 | struct hdac_ext_bus ebus; | |
| 60 | struct pci_dev *pci; | |
| 61 | ||
| 62 | unsigned int init_failed:1; /* delayed init failed */ | |
| 63 | struct platform_device *dmic_dev; | |
| 473eb87a | 64 | |
| ba40a854 | 65 | void *nhlt; /* nhlt ptr */ |
| d255b095 | 66 | struct skl_sst *skl_sst; /* sst skl ctx */ |
| e4e2d2f4 JK |
67 | |
| 68 | struct skl_dsp_resource resource; | |
| 69 | struct list_head ppl_list; | |
| a40e693c JK |
70 | }; |
| 71 | ||
| 72 | #define skl_to_ebus(s) (&(s)->ebus) | |
| 73 | #define ebus_to_skl(sbus) \ | |
| 74 | container_of(sbus, struct skl, sbus) | |
| 75 | ||
| 76 | /* to pass dai dma data */ | |
| 77 | struct skl_dma_params { | |
| 78 | u32 format; | |
| 79 | u8 stream_tag; | |
| 80 | }; | |
| 81 | ||
| 82 | int skl_platform_unregister(struct device *dev); | |
| 83 | int skl_platform_register(struct device *dev); | |
| 84 | ||
| ba40a854 DW |
85 | void *skl_nhlt_init(struct device *dev); |
| 86 | void skl_nhlt_free(void *addr); | |
| 473eb87a JK |
87 | struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance, |
| 88 | u8 link_type, u8 s_fmt, u8 no_ch, u32 s_rate, u8 dirn); | |
| d255b095 JK |
89 | |
| 90 | int skl_init_dsp(struct skl *skl); | |
| 91 | void skl_free_dsp(struct skl *skl); | |
| 92 | int skl_suspend_dsp(struct skl *skl); | |
| 93 | int skl_resume_dsp(struct skl *skl); | |
| a40e693c | 94 | #endif /* __SOUND_SOC_SKL_H */ |