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1 | /* |
2 | * Intel Smart Sound Technology (SST) Core | |
3 | * | |
4 | * Copyright (C) 2013, Intel Corporation. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License version | |
8 | * 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef __SOUND_SOC_SST_DSP_H | |
18 | #define __SOUND_SOC_SST_DSP_H | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/types.h> | |
22 | #include <linux/interrupt.h> | |
23 | ||
24 | /* SST Device IDs */ | |
25 | #define SST_DEV_ID_LYNX_POINT 0x33C8 | |
26 | #define SST_DEV_ID_WILDCAT_POINT 0x3438 | |
27 | #define SST_DEV_ID_BYT 0x0F28 | |
28 | ||
29 | /* Supported SST DMA Devices */ | |
30 | #define SST_DMA_TYPE_DW 1 | |
31 | #define SST_DMA_TYPE_MID 2 | |
32 | ||
33 | /* SST Shim register map | |
34 | * The register naming can differ between products. Some products also | |
35 | * contain extra functionality. | |
36 | */ | |
37 | #define SST_CSR 0x00 | |
38 | #define SST_PISR 0x08 | |
39 | #define SST_PIMR 0x10 | |
40 | #define SST_ISRX 0x18 | |
41 | #define SST_ISRD 0x20 | |
42 | #define SST_IMRX 0x28 | |
43 | #define SST_IMRD 0x30 | |
44 | #define SST_IPCX 0x38 /* IPC IA -> SST */ | |
45 | #define SST_IPCD 0x40 /* IPC SST -> IA */ | |
46 | #define SST_ISRSC 0x48 | |
47 | #define SST_ISRLPESC 0x50 | |
48 | #define SST_IMRSC 0x58 | |
49 | #define SST_IMRLPESC 0x60 | |
50 | #define SST_IPCSC 0x68 | |
51 | #define SST_IPCLPESC 0x70 | |
52 | #define SST_CLKCTL 0x78 | |
53 | #define SST_CSR2 0x80 | |
54 | #define SST_LTRC 0xE0 | |
55 | #define SST_HDMC 0xE8 | |
56 | #define SST_DBGO 0xF0 | |
57 | ||
58 | #define SST_SHIM_SIZE 0x100 | |
59 | #define SST_PWMCTRL 0x1000 | |
60 | ||
61 | /* SST Shim Register bits | |
62 | * The register bit naming can differ between products. Some products also | |
63 | * contain extra functionality. | |
64 | */ | |
65 | ||
66 | /* CSR / CS */ | |
67 | #define SST_CSR_RST (0x1 << 1) | |
68 | #define SST_CSR_SBCS0 (0x1 << 2) | |
69 | #define SST_CSR_SBCS1 (0x1 << 3) | |
70 | #define SST_CSR_DCS(x) (x << 4) | |
71 | #define SST_CSR_DCS_MASK (0x7 << 4) | |
72 | #define SST_CSR_STALL (0x1 << 10) | |
73 | #define SST_CSR_S0IOCS (0x1 << 21) | |
74 | #define SST_CSR_S1IOCS (0x1 << 23) | |
75 | #define SST_CSR_LPCS (0x1 << 31) | |
76 | #define SST_BYT_CSR_RST (0x1 << 0) | |
77 | #define SST_BYT_CSR_VECTOR_SEL (0x1 << 1) | |
78 | #define SST_BYT_CSR_STALL (0x1 << 2) | |
79 | #define SST_BYT_CSR_PWAITMODE (0x1 << 3) | |
80 | ||
81 | /* ISRX / ISC */ | |
82 | #define SST_ISRX_BUSY (0x1 << 1) | |
83 | #define SST_ISRX_DONE (0x1 << 0) | |
84 | #define SST_BYT_ISRX_REQUEST (0x1 << 1) | |
85 | ||
86 | /* ISRD / ISD */ | |
87 | #define SST_ISRD_BUSY (0x1 << 1) | |
88 | #define SST_ISRD_DONE (0x1 << 0) | |
89 | ||
90 | /* IMRX / IMC */ | |
91 | #define SST_IMRX_BUSY (0x1 << 1) | |
92 | #define SST_IMRX_DONE (0x1 << 0) | |
93 | #define SST_BYT_IMRX_REQUEST (0x1 << 1) | |
94 | ||
95 | /* IPCX / IPCC */ | |
96 | #define SST_IPCX_DONE (0x1 << 30) | |
97 | #define SST_IPCX_BUSY (0x1 << 31) | |
98 | #define SST_BYT_IPCX_DONE ((u64)0x1 << 62) | |
99 | #define SST_BYT_IPCX_BUSY ((u64)0x1 << 63) | |
100 | ||
101 | /* IPCD */ | |
102 | #define SST_IPCD_DONE (0x1 << 30) | |
103 | #define SST_IPCD_BUSY (0x1 << 31) | |
104 | #define SST_BYT_IPCD_DONE ((u64)0x1 << 62) | |
105 | #define SST_BYT_IPCD_BUSY ((u64)0x1 << 63) | |
106 | ||
107 | /* CLKCTL */ | |
108 | #define SST_CLKCTL_SMOS(x) (x << 24) | |
109 | #define SST_CLKCTL_MASK (3 << 24) | |
110 | #define SST_CLKCTL_DCPLCG (1 << 18) | |
111 | #define SST_CLKCTL_SCOE1 (1 << 17) | |
112 | #define SST_CLKCTL_SCOE0 (1 << 16) | |
113 | ||
114 | /* CSR2 / CS2 */ | |
115 | #define SST_CSR2_SDFD_SSP0 (1 << 1) | |
116 | #define SST_CSR2_SDFD_SSP1 (1 << 2) | |
117 | ||
118 | /* LTRC */ | |
119 | #define SST_LTRC_VAL(x) (x << 0) | |
120 | ||
121 | /* HDMC */ | |
122 | #define SST_HDMC_HDDA0(x) (x << 0) | |
123 | #define SST_HDMC_HDDA1(x) (x << 7) | |
124 | ||
125 | ||
126 | /* SST Vendor Defined Registers and bits */ | |
127 | #define SST_VDRTCTL0 0xa0 | |
128 | #define SST_VDRTCTL1 0xa4 | |
129 | #define SST_VDRTCTL2 0xa8 | |
130 | #define SST_VDRTCTL3 0xaC | |
131 | ||
132 | /* VDRTCTL0 */ | |
133 | #define SST_VDRTCL0_DSRAMPGE_SHIFT 16 | |
134 | #define SST_VDRTCL0_DSRAMPGE_MASK (0xffff << SST_VDRTCL0_DSRAMPGE_SHIFT) | |
135 | #define SST_VDRTCL0_ISRAMPGE_SHIFT 6 | |
136 | #define SST_VDRTCL0_ISRAMPGE_MASK (0x3ff << SST_VDRTCL0_ISRAMPGE_SHIFT) | |
137 | ||
138 | struct sst_dsp; | |
139 | ||
140 | /* | |
141 | * SST Device. | |
142 | * | |
143 | * This structure is populated by the SST core driver. | |
144 | */ | |
145 | struct sst_dsp_device { | |
146 | /* Mandatory fields */ | |
147 | struct sst_ops *ops; | |
148 | irqreturn_t (*thread)(int irq, void *context); | |
149 | void *thread_context; | |
150 | }; | |
151 | ||
152 | /* | |
153 | * SST Platform Data. | |
154 | */ | |
155 | struct sst_pdata { | |
156 | /* ACPI data */ | |
157 | u32 lpe_base; | |
158 | u32 lpe_size; | |
159 | u32 pcicfg_base; | |
160 | u32 pcicfg_size; | |
161 | u32 fw_base; | |
162 | u32 fw_size; | |
163 | int irq; | |
164 | ||
165 | /* Firmware */ | |
166 | const struct firmware *fw; | |
167 | ||
168 | /* DMA */ | |
169 | u32 dma_base; | |
170 | u32 dma_size; | |
171 | int dma_engine; | |
10df3509 | 172 | struct device *dma_dev; |
a4b12990 MB |
173 | |
174 | /* DSP */ | |
175 | u32 id; | |
176 | void *dsp; | |
177 | }; | |
178 | ||
179 | /* Initialization */ | |
180 | struct sst_dsp *sst_dsp_new(struct device *dev, | |
181 | struct sst_dsp_device *sst_dev, struct sst_pdata *pdata); | |
182 | void sst_dsp_free(struct sst_dsp *sst); | |
183 | ||
184 | /* SHIM Read / Write */ | |
185 | void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value); | |
186 | u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset); | |
187 | int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset, | |
188 | u32 mask, u32 value); | |
189 | void sst_dsp_shim_write64(struct sst_dsp *sst, u32 offset, u64 value); | |
190 | u64 sst_dsp_shim_read64(struct sst_dsp *sst, u32 offset); | |
191 | int sst_dsp_shim_update_bits64(struct sst_dsp *sst, u32 offset, | |
192 | u64 mask, u64 value); | |
193 | ||
194 | /* SHIM Read / Write Unlocked for callers already holding sst lock */ | |
195 | void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value); | |
196 | u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset); | |
197 | int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset, | |
198 | u32 mask, u32 value); | |
199 | void sst_dsp_shim_write64_unlocked(struct sst_dsp *sst, u32 offset, u64 value); | |
200 | u64 sst_dsp_shim_read64_unlocked(struct sst_dsp *sst, u32 offset); | |
201 | int sst_dsp_shim_update_bits64_unlocked(struct sst_dsp *sst, u32 offset, | |
202 | u64 mask, u64 value); | |
203 | ||
204 | /* Internal generic low-level SST IO functions - can be overidden */ | |
205 | void sst_shim32_write(void __iomem *addr, u32 offset, u32 value); | |
206 | u32 sst_shim32_read(void __iomem *addr, u32 offset); | |
207 | void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value); | |
208 | u64 sst_shim32_read64(void __iomem *addr, u32 offset); | |
209 | void sst_memcpy_toio_32(struct sst_dsp *sst, | |
210 | void __iomem *dest, void *src, size_t bytes); | |
211 | void sst_memcpy_fromio_32(struct sst_dsp *sst, | |
212 | void *dest, void __iomem *src, size_t bytes); | |
213 | ||
214 | /* DSP reset & boot */ | |
215 | void sst_dsp_reset(struct sst_dsp *sst); | |
216 | int sst_dsp_boot(struct sst_dsp *sst); | |
217 | ||
218 | /* Msg IO */ | |
219 | void sst_dsp_ipc_msg_tx(struct sst_dsp *dsp, u32 msg); | |
220 | u32 sst_dsp_ipc_msg_rx(struct sst_dsp *dsp); | |
221 | ||
222 | /* Mailbox management */ | |
223 | int sst_dsp_mailbox_init(struct sst_dsp *dsp, u32 inbox_offset, | |
224 | size_t inbox_size, u32 outbox_offset, size_t outbox_size); | |
225 | void sst_dsp_inbox_write(struct sst_dsp *dsp, void *message, size_t bytes); | |
226 | void sst_dsp_inbox_read(struct sst_dsp *dsp, void *message, size_t bytes); | |
227 | void sst_dsp_outbox_write(struct sst_dsp *dsp, void *message, size_t bytes); | |
228 | void sst_dsp_outbox_read(struct sst_dsp *dsp, void *message, size_t bytes); | |
229 | void sst_dsp_mailbox_dump(struct sst_dsp *dsp, size_t bytes); | |
230 | ||
231 | /* Debug */ | |
232 | void sst_dsp_dump(struct sst_dsp *sst); | |
233 | ||
234 | #endif |