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Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / sound / soc / intel / sst-haswell-dsp.c
CommitLineData
a4b12990
MB		 1/*
2 * Intel Haswell SST DSP driver
3 *
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/delay.h>
18#include <linux/fs.h>
19#include <linux/slab.h>
20#include <linux/device.h>
21#include <linux/sched.h>
22#include <linux/export.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
27#include <linux/pci.h>
28#include <linux/firmware.h>
29#include <linux/pm_runtime.h>
30
a4b12990
MB		 31#include "sst-dsp.h"
32#include "sst-dsp-priv.h"
33#include "sst-haswell-ipc.h"
34
35#include <trace/events/hswadsp.h>
36
37#define SST_HSW_FW_SIGNATURE_SIZE 4
38#define SST_HSW_FW_SIGN "$SST"
39#define SST_HSW_FW_LIB_SIGN "$LIB"
40
41#define SST_WPT_SHIM_OFFSET 0xFB000
42#define SST_LP_SHIM_OFFSET 0xE7000
43#define SST_WPT_IRAM_OFFSET 0xA0000
44#define SST_LP_IRAM_OFFSET 0x80000
e9600bc1
LG		 45#define SST_WPT_DSP_DRAM_OFFSET 0x400000
46#define SST_WPT_DSP_IRAM_OFFSET 0x00000
47#define SST_LPT_DSP_DRAM_OFFSET 0x400000
48#define SST_LPT_DSP_IRAM_OFFSET 0x00000
a4b12990
MB		 49
50#define SST_SHIM_PM_REG 0x84
51
52#define SST_HSW_IRAM 1
53#define SST_HSW_DRAM 2
54#define SST_HSW_REGS 3
55
56struct dma_block_info {
57 __le32 type; /* IRAM/DRAM */
58 __le32 size; /* Bytes */
59 __le32 ram_offset; /* Offset in I/DRAM */
60 __le32 rsvd; /* Reserved field */
61} __attribute__((packed));
62
63struct fw_module_info {
64 __le32 persistent_size;
65 __le32 scratch_size;
66} __attribute__((packed));
67
68struct fw_header {
69 unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* FW signature */
70 __le32 file_size; /* size of fw minus this header */
71 __le32 modules; /* # of modules */
72 __le32 file_format; /* version of header format */
73 __le32 reserved[4];
74} __attribute__((packed));
75
76struct fw_module_header {
77 unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* module signature */
78 __le32 mod_size; /* size of module */
79 __le32 blocks; /* # of blocks */
80 __le16 padding;
81 __le16 type; /* codec type, pp lib */
82 __le32 entry_point;
83 struct fw_module_info info;
84} __attribute__((packed));
85
86static void hsw_free(struct sst_dsp *sst);
87
88static int hsw_parse_module(struct sst_dsp *dsp, struct sst_fw *fw,
89 struct fw_module_header *module)
90{
91 struct dma_block_info *block;
92 struct sst_module *mod;
a4b12990 93 struct sst_module_template template;
e9600bc1 94 int count, ret;
a4b12990
MB		 95 void __iomem *ram;
96
97 /* TODO: allowed module types need to be configurable */
98 if (module->type != SST_HSW_MODULE_BASE_FW
99 && module->type != SST_HSW_MODULE_PCM_SYSTEM
100 && module->type != SST_HSW_MODULE_PCM
101 && module->type != SST_HSW_MODULE_PCM_REFERENCE
102 && module->type != SST_HSW_MODULE_PCM_CAPTURE
103 && module->type != SST_HSW_MODULE_LPAL)
104 return 0;
105
106 dev_dbg(dsp->dev, "new module sign 0x%s size 0x%x blocks 0x%x type 0x%x\n",
107 module->signature, module->mod_size,
108 module->blocks, module->type);
109 dev_dbg(dsp->dev, " entrypoint 0x%x\n", module->entry_point);
110 dev_dbg(dsp->dev, " persistent 0x%x scratch 0x%x\n",
111 module->info.persistent_size, module->info.scratch_size);
112
113 memset(&template, 0, sizeof(template));
114 template.id = module->type;
e9600bc1
LG		 115 template.entry = module->entry_point - 4;
116 template.persistent_size = module->info.persistent_size;
117 template.scratch_size = module->info.scratch_size;
a4b12990
MB		 118
119 mod = sst_module_new(fw, &template, NULL);
120 if (mod == NULL)
121 return -ENOMEM;
122
123 block = (void *)module + sizeof(*module);
124
125 for (count = 0; count < module->blocks; count++) {
126
127 if (block->size <= 0) {
128 dev_err(dsp->dev,
129 "error: block %d size invalid\n", count);
130 sst_module_free(mod);
131 return -EINVAL;
132 }
133
134 switch (block->type) {
135 case SST_HSW_IRAM:
136 ram = dsp->addr.lpe;
e9600bc1 137 mod->offset =
a4b12990 138 block->ram_offset + dsp->addr.iram_offset;
e9600bc1 139 mod->type = SST_MEM_IRAM;
a4b12990
MB		 140 break;
141 case SST_HSW_DRAM:
142 ram = dsp->addr.lpe;
e9600bc1
LG		 143 mod->offset = block->ram_offset;
144 mod->type = SST_MEM_DRAM;
a4b12990
MB		 145 break;
146 default:
147 dev_err(dsp->dev, "error: bad type 0x%x for block 0x%x\n",
148 block->type, count);
149 sst_module_free(mod);
150 return -EINVAL;
151 }
152
e9600bc1
LG		 153 mod->size = block->size;
154 mod->data = (void *)block + sizeof(*block);
155 mod->data_offset = mod->data - fw->dma_buf;
a4b12990 156
e9600bc1 157 dev_dbg(dsp->dev, "module block %d type 0x%x "
a4b12990 158 "size 0x%x ==> ram %p offset 0x%x\n",
e9600bc1 159 count, mod->type, block->size, ram,
a4b12990
MB		 160 block->ram_offset);
161
e9600bc1
LG		 162 ret = sst_module_alloc_blocks(mod);
163 if (ret < 0) {
164 dev_err(dsp->dev, "error: could not allocate blocks for module %d\n",
165 count);
166 sst_module_free(mod);
167 return ret;
168 }
a4b12990
MB		 169
170 block = (void *)block + sizeof(*block) + block->size;
171 }
e9600bc1 172
a4b12990
MB		 173 return 0;
174}
175
176static int hsw_parse_fw_image(struct sst_fw *sst_fw)
177{
178 struct fw_header *header;
a4b12990
MB		 179 struct fw_module_header *module;
180 struct sst_dsp *dsp = sst_fw->dsp;
a4b12990
MB		 181 int ret, count;
182
183 /* Read the header information from the data pointer */
184 header = (struct fw_header *)sst_fw->dma_buf;
185
186 /* verify FW */
187 if ((strncmp(header->signature, SST_HSW_FW_SIGN, 4) != 0) ||
188 (sst_fw->size != header->file_size + sizeof(*header))) {
189 dev_err(dsp->dev, "error: invalid fw sign/filesize mismatch\n");
190 return -EINVAL;
191 }
192
193 dev_dbg(dsp->dev, "header size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
194 header->file_size, header->modules,
195 header->file_format, sizeof(*header));
196
197 /* parse each module */
198 module = (void *)sst_fw->dma_buf + sizeof(*header);
199 for (count = 0; count < header->modules; count++) {
200
201 /* module */
202 ret = hsw_parse_module(dsp, sst_fw, module);
203 if (ret < 0) {
204 dev_err(dsp->dev, "error: invalid module %d\n", count);
205 return ret;
206 }
207 module = (void *)module + sizeof(*module) + module->mod_size;
208 }
209
a4b12990
MB		 210 return 0;
211}
212
213static irqreturn_t hsw_irq(int irq, void *context)
214{
215 struct sst_dsp *sst = (struct sst_dsp *) context;
216 u32 isr;
217 int ret = IRQ_NONE;
218
219 spin_lock(&sst->spinlock);
220
221 /* Interrupt arrived, check src */
222 isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
223 if (isr & SST_ISRX_DONE) {
224 trace_sst_irq_done(isr,
225 sst_dsp_shim_read_unlocked(sst, SST_IMRX));
226
227 /* Mask Done interrupt before return */
228 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
229 SST_IMRX_DONE, SST_IMRX_DONE);
230 ret = IRQ_WAKE_THREAD;
231 }
232
233 if (isr & SST_ISRX_BUSY) {
234 trace_sst_irq_busy(isr,
235 sst_dsp_shim_read_unlocked(sst, SST_IMRX));
236
237 /* Mask Busy interrupt before return */
238 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
239 SST_IMRX_BUSY, SST_IMRX_BUSY);
240 ret = IRQ_WAKE_THREAD;
241 }
242
243 spin_unlock(&sst->spinlock);
244 return ret;
245}
246
6b7b4b89
LG		 247static void hsw_set_dsp_D3(struct sst_dsp *sst)
248{
249 u32 val;
0d2135ec
JY		 250 u32 reg;
251
252 /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
253 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
254 reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
255 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
6b7b4b89 256
0d2135ec 257 /* enable power gating and switch off DRAM & IRAM blocks */
6b7b4b89 258 val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
0d2135ec 259 val |= SST_VDRTCL0_DSRAMPGE_MASK |
6b7b4b89 260 SST_VDRTCL0_ISRAMPGE_MASK;
0d2135ec 261 val &= ~(SST_VDRTCL0_D3PGD | SST_VDRTCL0_D3SRAMPGD);
6b7b4b89
LG		 262 writel(val, sst->addr.pci_cfg + SST_VDRTCTL0);
263
0d2135ec
JY		 264 /* switch off audio PLL */
265 val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
266 val |= SST_VDRTCL2_APLLSE_MASK;
267 writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
268
269 /* disable MCLK(clkctl.smos = 0) */
270 sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
271 SST_CLKCTL_MASK, 0);
272
273 /* Set D3 state, delay 50 us */
6b7b4b89
LG		 274 val = readl(sst->addr.pci_cfg + SST_PMCS);
275 val |= SST_PMCS_PS_MASK;
276 writel(val, sst->addr.pci_cfg + SST_PMCS);
0d2135ec
JY		 277 udelay(50);
278
279 /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
280 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
281 reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
282 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
283
284 udelay(50);
285
6b7b4b89
LG		 286}
287
288static void hsw_reset(struct sst_dsp *sst)
289{
290 /* put DSP into reset and stall */
291 sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
292 SST_CSR_RST | SST_CSR_STALL,
293 SST_CSR_RST | SST_CSR_STALL);
294
295 /* keep in reset for 10ms */
296 mdelay(10);
297
298 /* take DSP out of reset and keep stalled for FW loading */
299 sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
300 SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL);
301}
302
303static int hsw_set_dsp_D0(struct sst_dsp *sst)
a4b12990 304{
6b7b4b89 305 int tries = 10;
69067f9d 306 u32 reg, fw_dump_bit;
6b7b4b89 307
0d2135ec
JY		 308 /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
309 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
310 reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
311 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
312
313 /* Disable D3PG (VDRTCTL0.D3PGD = 1) */
314 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
315 reg |= SST_VDRTCL0_D3PGD;
316 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0);
317
6b7b4b89
LG		 318 /* Set D0 state */
319 reg = readl(sst->addr.pci_cfg + SST_PMCS);
320 reg &= ~SST_PMCS_PS_MASK;
321 writel(reg, sst->addr.pci_cfg + SST_PMCS);
322
323 /* check that ADSP shim is enabled */
324 while (tries--) {
325 reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK;
326 if (reg == 0)
327 goto finish;
328
329 msleep(1);
330 }
331
332 return -ENODEV;
333
334finish:
a4b12990
MB		 335 /* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */
336 sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
337 SST_CSR_S1IOCS | SST_CSR_SBCS1 | SST_CSR_LPCS, 0x0);
338
339 /* stall DSP core, set clk to 192/96Mhz */
340 sst_dsp_shim_update_bits_unlocked(sst,
341 SST_CSR, SST_CSR_STALL | SST_CSR_DCS_MASK,
342 SST_CSR_STALL | SST_CSR_DCS(4));
343
344 /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
345 sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
346 SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0,
347 SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0);
348
0d2135ec
JY		 349 /* Stall and reset core, set CSR */
350 hsw_reset(sst);
351
352 /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
353 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
354 reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
355 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
356
357 udelay(50);
358
359 /* switch on audio PLL */
360 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
361 reg &= ~SST_VDRTCL2_APLLSE_MASK;
362 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
363
364 /* set default power gating control, enable power gating control for all blocks. that is,
365 can't be accessed, please enable each block before accessing. */
366 reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
367 reg |= SST_VDRTCL0_DSRAMPGE_MASK | SST_VDRTCL0_ISRAMPGE_MASK;
69067f9d
JY		 368 /* for D0, always enable the block(DSRAM[0]) used for FW dump */
369 fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT;
370 writel(reg & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0);
0d2135ec
JY		 371
372
a4b12990
MB		 373 /* disable DMA finish function for SSP0 & SSP1 */
374 sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,
375 SST_CSR2_SDFD_SSP1);
376
6b7b4b89
LG		 377 /* set on-demond mode on engine 0,1 for all channels */
378 sst_dsp_shim_update_bits(sst, SST_HMDC,
379 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
380 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
381
382 /* Enable Interrupt from both sides */
383 sst_dsp_shim_update_bits(sst, SST_IMRX, (SST_IMRX_BUSY | SST_IMRX_DONE),
384 0x0);
385 sst_dsp_shim_update_bits(sst, SST_IMRD, (SST_IMRD_DONE | SST_IMRD_BUSY |
386 SST_IMRD_SSP0 | SST_IMRD_DMAC), 0x0);
387
388 /* clear IPC registers */
389 sst_dsp_shim_write(sst, SST_IPCX, 0x0);
390 sst_dsp_shim_write(sst, SST_IPCD, 0x0);
391 sst_dsp_shim_write(sst, 0x80, 0x6);
392 sst_dsp_shim_write(sst, 0xe0, 0x300a);
a4b12990 393
6b7b4b89
LG		 394 return 0;
395}
396
397static void hsw_boot(struct sst_dsp *sst)
398{
399 /* set oportunistic mode on engine 0,1 for all channels */
400 sst_dsp_shim_update_bits(sst, SST_HMDC,
401 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH, 0);
402
a4b12990
MB		 403 /* set DSP to RUN */
404 sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_STALL, 0x0);
405}
406
6b7b4b89 407static void hsw_stall(struct sst_dsp *sst)
a4b12990 408{
6b7b4b89
LG		 409 /* stall DSP */
410 sst_dsp_shim_update_bits(sst, SST_CSR,
411 SST_CSR_24MHZ_LPCS | SST_CSR_STALL,
412 SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
413}
414
415static void hsw_sleep(struct sst_dsp *sst)
416{
417 dev_dbg(sst->dev, "HSW_PM dsp runtime suspend\n");
418
a4b12990 419 /* put DSP into reset and stall */
6b7b4b89
LG		 420 sst_dsp_shim_update_bits(sst, SST_CSR,
421 SST_CSR_24MHZ_LPCS | SST_CSR_RST | SST_CSR_STALL,
422 SST_CSR_RST | SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
a4b12990 423
6b7b4b89
LG		 424 hsw_set_dsp_D3(sst);
425 dev_dbg(sst->dev, "HSW_PM dsp runtime suspend exit\n");
426}
a4b12990 427
6b7b4b89
LG		 428static int hsw_wake(struct sst_dsp *sst)
429{
430 int ret;
431
432 dev_dbg(sst->dev, "HSW_PM dsp runtime resume\n");
433
434 ret = hsw_set_dsp_D0(sst);
435 if (ret < 0)
436 return ret;
437
438 dev_dbg(sst->dev, "HSW_PM dsp runtime resume exit\n");
439
440 return 0;
a4b12990
MB		 441}
442
443struct sst_adsp_memregion {
444 u32 start;
445 u32 end;
446 int blocks;
447 enum sst_mem_type type;
448};
449
450/* lynx point ADSP mem regions */
451static const struct sst_adsp_memregion lp_region[] = {
452 {0x00000, 0x40000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
453 {0x40000, 0x80000, 8, SST_MEM_DRAM}, /* D-SRAM1 - 8 * 32kB */
454 {0x80000, 0xE0000, 12, SST_MEM_IRAM}, /* I-SRAM - 12 * 32kB */
455};
456
457/* wild cat point ADSP mem regions */
458static const struct sst_adsp_memregion wpt_region[] = {
15446c0b 459 {0x00000, 0xA0000, 20, SST_MEM_DRAM}, /* D-SRAM0,D-SRAM1,D-SRAM2 - 20 * 32kB */
a4b12990
MB		 460 {0xA0000, 0xF0000, 10, SST_MEM_IRAM}, /* I-SRAM - 10 * 32kB */
461};
462
463static int hsw_acpi_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)
464{
465 /* ADSP DRAM & IRAM */
466 sst->addr.lpe_base = pdata->lpe_base;
467 sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
468 if (!sst->addr.lpe)
469 return -ENODEV;
470
471 /* ADSP PCI MMIO config space */
472 sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
473 if (!sst->addr.pci_cfg) {
474 iounmap(sst->addr.lpe);
475 return -ENODEV;
476 }
477
478 /* SST Shim */
479 sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
480 return 0;
481}
482
54879323
JY		 483struct sst_sram_shift {
484 u32 dev_id; /* SST Device IDs */
485 u32 iram_shift;
486 u32 dram_shift;
487};
488
489static const struct sst_sram_shift sram_shift[] = {
490 {SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */
491 {SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */
492};
69067f9d 493
a4b12990
MB		 494static u32 hsw_block_get_bit(struct sst_mem_block *block)
495{
54879323
JY		 496 u32 bit = 0, shift = 0, index;
497 struct sst_dsp *sst = block->dsp;
a4b12990 498
54879323
JY		 499 for (index = 0; index < ARRAY_SIZE(sram_shift); index++) {
500 if (sram_shift[index].dev_id == sst->id)
501 break;
a4b12990
MB		 502 }
503
54879323
JY		 504 if (index < ARRAY_SIZE(sram_shift)) {
505 switch (block->type) {
506 case SST_MEM_DRAM:
507 shift = sram_shift[index].dram_shift;
508 break;
509 case SST_MEM_IRAM:
510 shift = sram_shift[index].iram_shift;
511 break;
512 default:
513 shift = 0;
514 }
515 } else
516 shift = 0;
517
a4b12990
MB		 518 bit = 1 << (block->index + shift);
519
520 return bit;
521}
522
c761b583
JY		 523/*dummy read a SRAM block.*/
524static void sst_mem_block_dummy_read(struct sst_mem_block *block)
525{
526 u32 size;
527 u8 tmp_buf[4];
528 struct sst_dsp *sst = block->dsp;
529
530 size = block->size > 4 ? 4 : block->size;
531 memcpy_fromio(tmp_buf, sst->addr.lpe + block->offset, size);
532}
533
a4b12990
MB		 534/* enable 32kB memory block - locks held by caller */
535static int hsw_block_enable(struct sst_mem_block *block)
536{
537 struct sst_dsp *sst = block->dsp;
538 u32 bit, val;
539
540 if (block->users++ > 0)
541 return 0;
542
543 dev_dbg(block->dsp->dev, " enabled block %d:%d at offset 0x%x\n",
544 block->type, block->index, block->offset);
545
0d2135ec
JY		 546 /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
547 val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
548 val &= ~SST_VDRTCL2_DCLCGE;
549 writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
550
a4b12990
MB		 551 val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
552 bit = hsw_block_get_bit(block);
553 writel(val & ~bit, sst->addr.pci_cfg + SST_VDRTCTL0);
554
555 /* wait 18 DSP clock ticks */
556 udelay(10);
557
0d2135ec
JY		 558 /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
559 val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
560 val |= SST_VDRTCL2_DCLCGE;
561 writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
562
563 udelay(50);
564
c761b583
JY		 565 /*add a dummy read before the SRAM block is written, otherwise the writing may miss bytes sometimes.*/
566 sst_mem_block_dummy_read(block);
a4b12990
MB		 567 return 0;
568}
569
570/* disable 32kB memory block - locks held by caller */
571static int hsw_block_disable(struct sst_mem_block *block)
572{
573 struct sst_dsp *sst = block->dsp;
574 u32 bit, val;
575
576 if (--block->users > 0)
577 return 0;
578
579 dev_dbg(block->dsp->dev, " disabled block %d:%d at offset 0x%x\n",
580 block->type, block->index, block->offset);
581
0d2135ec
JY		 582 /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
583 val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
584 val &= ~SST_VDRTCL2_DCLCGE;
585 writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
586
587
a4b12990
MB		 588 val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
589 bit = hsw_block_get_bit(block);
69067f9d
JY		 590 /* don't disable DSRAM[0], keep it always enable for FW dump*/
591 if (bit != (1 << SST_VDRTCL0_DSRAMPGE_SHIFT))
592 writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0);
a4b12990 593
0d2135ec
JY		 594 /* wait 18 DSP clock ticks */
595 udelay(10);
596
597 /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
598 val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
599 val |= SST_VDRTCL2_DCLCGE;
600 writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
601
602 udelay(50);
603
a4b12990
MB		 604 return 0;
605}
606
607static struct sst_block_ops sst_hsw_ops = {
608 .enable = hsw_block_enable,
609 .disable = hsw_block_disable,
610};
611
a4b12990
MB		 612static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)
613{
614 const struct sst_adsp_memregion *region;
615 struct device *dev;
616 int ret = -ENODEV, i, j, region_count;
69067f9d 617 u32 offset, size, fw_dump_bit;
a4b12990 618
10df3509 619 dev = sst->dma_dev;
a4b12990
MB		 620
621 switch (sst->id) {
622 case SST_DEV_ID_LYNX_POINT:
623 region = lp_region;
624 region_count = ARRAY_SIZE(lp_region);
625 sst->addr.iram_offset = SST_LP_IRAM_OFFSET;
e9600bc1
LG		 626 sst->addr.dsp_iram_offset = SST_LPT_DSP_IRAM_OFFSET;
627 sst->addr.dsp_dram_offset = SST_LPT_DSP_DRAM_OFFSET;
a4b12990
MB		 628 sst->addr.shim_offset = SST_LP_SHIM_OFFSET;
629 break;
630 case SST_DEV_ID_WILDCAT_POINT:
631 region = wpt_region;
632 region_count = ARRAY_SIZE(wpt_region);
633 sst->addr.iram_offset = SST_WPT_IRAM_OFFSET;
e9600bc1
LG		 634 sst->addr.dsp_iram_offset = SST_WPT_DSP_IRAM_OFFSET;
635 sst->addr.dsp_dram_offset = SST_WPT_DSP_DRAM_OFFSET;
a4b12990
MB		 636 sst->addr.shim_offset = SST_WPT_SHIM_OFFSET;
637 break;
638 default:
639 dev_err(dev, "error: failed to get mem resources\n");
640 return ret;
641 }
642
643 ret = hsw_acpi_resource_map(sst, pdata);
644 if (ret < 0) {
645 dev_err(dev, "error: failed to map resources\n");
646 return ret;
647 }
648
649 /* enable the DSP SHIM */
6b7b4b89 650 ret = hsw_set_dsp_D0(sst);
a4b12990
MB		 651 if (ret < 0) {
652 dev_err(dev, "error: failed to set DSP D0 and reset SHIM\n");
653 return ret;
654 }
655
10df3509 656 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(31));
a4b12990
MB		 657 if (ret)
658 return ret;
659
a4b12990
MB		 660
661 /* register DSP memory blocks - ideally we should get this from ACPI */
662 for (i = 0; i < region_count; i++) {
663 offset = region[i].start;
664 size = (region[i].end - region[i].start) / region[i].blocks;
665
666 /* register individual memory blocks */
667 for (j = 0; j < region[i].blocks; j++) {
668 sst_mem_block_register(sst, offset, size,
669 region[i].type, &sst_hsw_ops, j, sst);
670 offset += size;
671 }
672 }
673
69067f9d
JY		 674 /* always enable the block(DSRAM[0]) used for FW dump */
675 fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT;
85e63007
JY		 676 /* set default power gating control, enable power gating control for all blocks. that is,
677 can't be accessed, please enable each block before accessing. */
69067f9d 678 writel(0xffffffff & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0);
a4b12990
MB		 679
680 return 0;
681}
682
683static void hsw_free(struct sst_dsp *sst)
684{
685 sst_mem_block_unregister_all(sst);
686 iounmap(sst->addr.lpe);
687 iounmap(sst->addr.pci_cfg);
688}
689
690struct sst_ops haswell_ops = {
691 .reset = hsw_reset,
692 .boot = hsw_boot,
6b7b4b89
LG		 693 .stall = hsw_stall,
694 .wake = hsw_wake,
695 .sleep = hsw_sleep,
a4b12990
MB		 696 .write = sst_shim32_write,
697 .read = sst_shim32_read,
698 .write64 = sst_shim32_write64,
699 .read64 = sst_shim32_read64,
700 .ram_read = sst_memcpy_fromio_32,
701 .ram_write = sst_memcpy_toio_32,
702 .irq_handler = hsw_irq,
703 .init = hsw_init,
704 .free = hsw_free,
705 .parse_fw = hsw_parse_fw_image,
706};
Linux kernel - Deliverables
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