[deliverable/linux.git] / sound / soc / intel / sst-haswell-dsp.c

/*
 * Intel Haswell SST DSP driver
 *
 * Copyright (C) 2013, Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/sched.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/firmware.h>
#include <linux/pm_runtime.h>

#include "sst-dsp.h"
#include "sst-dsp-priv.h"
#include "sst-haswell-ipc.h"

#include <trace/events/hswadsp.h>

#define SST_HSW_FW_SIGNATURE_SIZE	4
#define SST_HSW_FW_SIGN			"$SST"
#define SST_HSW_FW_LIB_SIGN		"$LIB"

#define SST_WPT_SHIM_OFFSET	0xFB000
#define SST_LP_SHIM_OFFSET	0xE7000
#define SST_WPT_IRAM_OFFSET	0xA0000
#define SST_LP_IRAM_OFFSET	0x80000

#define SST_SHIM_PM_REG		0x84

#define SST_HSW_IRAM	1
#define SST_HSW_DRAM	2
#define SST_HSW_REGS	3

struct dma_block_info {
	__le32 type;		/* IRAM/DRAM */
	__le32 size;		/* Bytes */
	__le32 ram_offset;	/* Offset in I/DRAM */
	__le32 rsvd;		/* Reserved field */
} __attribute__((packed));

struct fw_module_info {
	__le32 persistent_size;
	__le32 scratch_size;
} __attribute__((packed));

struct fw_header {
	unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* FW signature */
	__le32 file_size;		/* size of fw minus this header */
	__le32 modules;		/*  # of modules */
	__le32 file_format;	/* version of header format */
	__le32 reserved[4];
} __attribute__((packed));

struct fw_module_header {
	unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* module signature */
	__le32 mod_size;	/* size of module */
	__le32 blocks;	/* # of blocks */
	__le16 padding;
	__le16 type;	/* codec type, pp lib */
	__le32 entry_point;
	struct fw_module_info info;
} __attribute__((packed));

static void hsw_free(struct sst_dsp *sst);

static int hsw_parse_module(struct sst_dsp *dsp, struct sst_fw *fw,
	struct fw_module_header *module)
{
	struct dma_block_info *block;
	struct sst_module *mod;
	struct sst_module_data block_data;
	struct sst_module_template template;
	int count;
	void __iomem *ram;

	/* TODO: allowed module types need to be configurable */
	if (module->type != SST_HSW_MODULE_BASE_FW
		&& module->type != SST_HSW_MODULE_PCM_SYSTEM
		&& module->type != SST_HSW_MODULE_PCM
		&& module->type != SST_HSW_MODULE_PCM_REFERENCE
		&& module->type != SST_HSW_MODULE_PCM_CAPTURE
		&& module->type != SST_HSW_MODULE_LPAL)
		return 0;

	dev_dbg(dsp->dev, "new module sign 0x%s size 0x%x blocks 0x%x type 0x%x\n",
		module->signature, module->mod_size,
		module->blocks, module->type);
	dev_dbg(dsp->dev, " entrypoint 0x%x\n", module->entry_point);
	dev_dbg(dsp->dev, " persistent 0x%x scratch 0x%x\n",
		module->info.persistent_size, module->info.scratch_size);

	memset(&template, 0, sizeof(template));
	template.id = module->type;
	template.entry = module->entry_point;
	template.p.size = module->info.persistent_size;
	template.p.type = SST_MEM_DRAM;
	template.p.data_type = SST_DATA_P;
	template.s.size = module->info.scratch_size;
	template.s.type = SST_MEM_DRAM;
	template.s.data_type = SST_DATA_S;

	mod = sst_module_new(fw, &template, NULL);
	if (mod == NULL)
		return -ENOMEM;

	block = (void *)module + sizeof(*module);

	for (count = 0; count < module->blocks; count++) {

		if (block->size <= 0) {
			dev_err(dsp->dev,
				"error: block %d size invalid\n", count);
			sst_module_free(mod);
			return -EINVAL;
		}

		switch (block->type) {
		case SST_HSW_IRAM:
			ram = dsp->addr.lpe;
			block_data.offset =
				block->ram_offset + dsp->addr.iram_offset;
			block_data.type = SST_MEM_IRAM;
			break;
		case SST_HSW_DRAM:
			ram = dsp->addr.lpe;
			block_data.offset = block->ram_offset;
			block_data.type = SST_MEM_DRAM;
			break;
		default:
			dev_err(dsp->dev, "error: bad type 0x%x for block 0x%x\n",
				block->type, count);
			sst_module_free(mod);
			return -EINVAL;
		}

		block_data.size = block->size;
		block_data.data_type = SST_DATA_M;
		block_data.data = (void *)block + sizeof(*block);
		block_data.data_offset = block_data.data - fw->dma_buf;

		dev_dbg(dsp->dev, "copy firmware block %d type 0x%x "
			"size 0x%x ==> ram %p offset 0x%x\n",
			count, block->type, block->size, ram,
			block->ram_offset);

		sst_module_insert_fixed_block(mod, &block_data);

		block = (void *)block + sizeof(*block) + block->size;
	}
	return 0;
}

static int hsw_parse_fw_image(struct sst_fw *sst_fw)
{
	struct fw_header *header;
	struct sst_module *scratch;
	struct fw_module_header *module;
	struct sst_dsp *dsp = sst_fw->dsp;
	struct sst_hsw *hsw = sst_fw->private;
	int ret, count;

	/* Read the header information from the data pointer */
	header = (struct fw_header *)sst_fw->dma_buf;

	/* verify FW */
	if ((strncmp(header->signature, SST_HSW_FW_SIGN, 4) != 0) ||
		(sst_fw->size != header->file_size + sizeof(*header))) {
		dev_err(dsp->dev, "error: invalid fw sign/filesize mismatch\n");
		return -EINVAL;
	}

	dev_dbg(dsp->dev, "header size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
		header->file_size, header->modules,
		header->file_format, sizeof(*header));

	/* parse each module */
	module = (void *)sst_fw->dma_buf + sizeof(*header);
	for (count = 0; count < header->modules; count++) {

		/* module */
		ret = hsw_parse_module(dsp, sst_fw, module);
		if (ret < 0) {
			dev_err(dsp->dev, "error: invalid module %d\n", count);
			return ret;
		}
		module = (void *)module + sizeof(*module) + module->mod_size;
	}

	/* allocate persistent/scratch mem regions */
	scratch = sst_mem_block_alloc_scratch(dsp);
	if (scratch == NULL)
		return -ENOMEM;

	sst_hsw_set_scratch_module(hsw, scratch);

	return 0;
}

static irqreturn_t hsw_irq(int irq, void *context)
{
	struct sst_dsp *sst = (struct sst_dsp *) context;
	u32 isr;
	int ret = IRQ_NONE;

	spin_lock(&sst->spinlock);

	/* Interrupt arrived, check src */
	isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
	if (isr & SST_ISRX_DONE) {
		trace_sst_irq_done(isr,
			sst_dsp_shim_read_unlocked(sst, SST_IMRX));

		/* Mask Done interrupt before return */
		sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
			SST_IMRX_DONE, SST_IMRX_DONE);
		ret = IRQ_WAKE_THREAD;
	}

	if (isr & SST_ISRX_BUSY) {
		trace_sst_irq_busy(isr,
			sst_dsp_shim_read_unlocked(sst, SST_IMRX));

		/* Mask Busy interrupt before return */
		sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
			SST_IMRX_BUSY, SST_IMRX_BUSY);
		ret = IRQ_WAKE_THREAD;
	}

	spin_unlock(&sst->spinlock);
	return ret;
}

static void hsw_boot(struct sst_dsp *sst)
{
	/* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
		SST_CSR_S1IOCS | SST_CSR_SBCS1 | SST_CSR_LPCS, 0x0);

	/* stall DSP core, set clk to 192/96Mhz */
	sst_dsp_shim_update_bits_unlocked(sst,
		SST_CSR, SST_CSR_STALL | SST_CSR_DCS_MASK,
		SST_CSR_STALL | SST_CSR_DCS(4));

	/* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
		SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0,
		SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0);

	/* disable DMA finish function for SSP0 & SSP1 */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,
		SST_CSR2_SDFD_SSP1);

	/* enable DMA engine 0,1 all channels to access host memory */
	sst_dsp_shim_update_bits_unlocked(sst, SST_HDMC,
		SST_HDMC_HDDA1(0xff)  | SST_HDMC_HDDA0(0xff),
		SST_HDMC_HDDA1(0xff) | SST_HDMC_HDDA0(0xff));

	/* disable all clock gating */
	writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2);

	/* set DSP to RUN */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_STALL, 0x0);
}

static void hsw_reset(struct sst_dsp *sst)
{
	/* put DSP into reset and stall */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
		SST_CSR_RST | SST_CSR_STALL, SST_CSR_RST | SST_CSR_STALL);

	/* keep in reset for 10ms */
	mdelay(10);

	/* take DSP out of reset and keep stalled for FW loading */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
		SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL);
}

struct sst_adsp_memregion {
	u32 start;
	u32 end;
	int blocks;
	enum sst_mem_type type;
};

/* lynx point ADSP mem regions */
static const struct sst_adsp_memregion lp_region[] = {
	{0x00000, 0x40000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
	{0x40000, 0x80000, 8, SST_MEM_DRAM}, /* D-SRAM1 - 8 * 32kB */
	{0x80000, 0xE0000, 12, SST_MEM_IRAM}, /* I-SRAM - 12 * 32kB */
};

/* wild cat point ADSP mem regions */
static const struct sst_adsp_memregion wpt_region[] = {
	{0x00000, 0xA0000, 20, SST_MEM_DRAM}, /* D-SRAM0,D-SRAM1,D-SRAM2 - 20 * 32kB */
	{0xA0000, 0xF0000, 10, SST_MEM_IRAM}, /* I-SRAM - 10 * 32kB */
};

static int hsw_acpi_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)
{
	/* ADSP DRAM & IRAM */
	sst->addr.lpe_base = pdata->lpe_base;
	sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
	if (!sst->addr.lpe)
		return -ENODEV;

	/* ADSP PCI MMIO config space */
	sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
	if (!sst->addr.pci_cfg) {
		iounmap(sst->addr.lpe);
		return -ENODEV;
	}

	/* SST Shim */
	sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
	return 0;
}

struct sst_sram_shift {
	u32 dev_id;	/* SST Device IDs  */
	u32 iram_shift;
	u32 dram_shift;
};

static const struct sst_sram_shift sram_shift[] = {
	{SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */
	{SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */
};
static u32 hsw_block_get_bit(struct sst_mem_block *block)
{
	u32 bit = 0, shift = 0, index;
	struct sst_dsp *sst = block->dsp;

	for (index = 0; index < ARRAY_SIZE(sram_shift); index++) {
		if (sram_shift[index].dev_id == sst->id)
			break;
	}

	if (index < ARRAY_SIZE(sram_shift)) {
		switch (block->type) {
		case SST_MEM_DRAM:
			shift = sram_shift[index].dram_shift;
			break;
		case SST_MEM_IRAM:
			shift = sram_shift[index].iram_shift;
			break;
		default:
			shift = 0;
		}
	} else
		shift = 0;

	bit = 1 << (block->index + shift);

	return bit;
}

/* enable 32kB memory block - locks held by caller */
static int hsw_block_enable(struct sst_mem_block *block)
{
	struct sst_dsp *sst = block->dsp;
	u32 bit, val;

	if (block->users++ > 0)
		return 0;

	dev_dbg(block->dsp->dev, " enabled block %d:%d at offset 0x%x\n",
		block->type, block->index, block->offset);

	val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
	bit = hsw_block_get_bit(block);
	writel(val & ~bit, sst->addr.pci_cfg + SST_VDRTCTL0);

	/* wait 18 DSP clock ticks */
	udelay(10);

	return 0;
}

/* disable 32kB memory block - locks held by caller */
static int hsw_block_disable(struct sst_mem_block *block)
{
	struct sst_dsp *sst = block->dsp;
	u32 bit, val;

	if (--block->users > 0)
		return 0;

	dev_dbg(block->dsp->dev, " disabled block %d:%d at offset 0x%x\n",
		block->type, block->index, block->offset);

	val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
	bit = hsw_block_get_bit(block);
	writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0);

	return 0;
}

static struct sst_block_ops sst_hsw_ops = {
	.enable = hsw_block_enable,
	.disable = hsw_block_disable,
};

static int hsw_enable_shim(struct sst_dsp *sst)
{
	int tries = 10;
	u32 reg;

	/* enable shim */
	reg = readl(sst->addr.pci_cfg + SST_SHIM_PM_REG);
	writel(reg & ~0x3, sst->addr.pci_cfg + SST_SHIM_PM_REG);

	/* check that ADSP shim is enabled */
	while (tries--) {
		reg = sst_dsp_shim_read_unlocked(sst, SST_CSR);
		if (reg != 0xffffffff)
			return 0;

		msleep(1);
	}

	return -ENODEV;
}

static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)
{
	const struct sst_adsp_memregion *region;
	struct device *dev;
	int ret = -ENODEV, i, j, region_count;
	u32 offset, size;

	dev = sst->dma_dev;

	switch (sst->id) {
	case SST_DEV_ID_LYNX_POINT:
		region = lp_region;
		region_count = ARRAY_SIZE(lp_region);
		sst->addr.iram_offset = SST_LP_IRAM_OFFSET;
		sst->addr.shim_offset = SST_LP_SHIM_OFFSET;
		break;
	case SST_DEV_ID_WILDCAT_POINT:
		region = wpt_region;
		region_count = ARRAY_SIZE(wpt_region);
		sst->addr.iram_offset = SST_WPT_IRAM_OFFSET;
		sst->addr.shim_offset = SST_WPT_SHIM_OFFSET;
		break;
	default:
		dev_err(dev, "error: failed to get mem resources\n");
		return ret;
	}

	ret = hsw_acpi_resource_map(sst, pdata);
	if (ret < 0) {
		dev_err(dev, "error: failed to map resources\n");
		return ret;
	}

	/* enable the DSP SHIM */
	ret = hsw_enable_shim(sst);
	if (ret < 0) {
		dev_err(dev, "error: failed to set DSP D0 and reset SHIM\n");
		return ret;
	}

	ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(31));
	if (ret)
		return ret;

	/* Enable Interrupt from both sides */
	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX, 0x3, 0x0);
	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRD,
		(0x3 | 0x1 << 16 | 0x3 << 21), 0x0);

	/* register DSP memory blocks - ideally we should get this from ACPI */
	for (i = 0; i < region_count; i++) {
		offset = region[i].start;
		size = (region[i].end - region[i].start) / region[i].blocks;

		/* register individual memory blocks */
		for (j = 0; j < region[i].blocks; j++) {
			sst_mem_block_register(sst, offset, size,
				region[i].type, &sst_hsw_ops, j, sst);
			offset += size;
		}
	}

	/* set default power gating control, enable power gating control for all blocks. that is,
	can't be accessed, please enable each block before accessing. */
	writel(0xffffffff, sst->addr.pci_cfg + SST_VDRTCTL0);

	return 0;
}

static void hsw_free(struct sst_dsp *sst)
{
	sst_mem_block_unregister_all(sst);
	iounmap(sst->addr.lpe);
	iounmap(sst->addr.pci_cfg);
}

struct sst_ops haswell_ops = {
	.reset = hsw_reset,
	.boot = hsw_boot,
	.write = sst_shim32_write,
	.read = sst_shim32_read,
	.write64 = sst_shim32_write64,
	.read64 = sst_shim32_read64,
	.ram_read = sst_memcpy_fromio_32,
	.ram_write = sst_memcpy_toio_32,
	.irq_handler = hsw_irq,
	.init = hsw_init,
	.free = hsw_free,
	.parse_fw = hsw_parse_fw_image,
};
Commit	Line	Data
a4b12990 MB	1	/*
	2	* Intel Haswell SST DSP driver
	3	*
	4	* Copyright (C) 2013, Intel Corporation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License version
	8	* 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
	17	#include <linux/delay.h>
	18	#include <linux/fs.h>
	19	#include <linux/slab.h>
	20	#include <linux/device.h>
	21	#include <linux/sched.h>
	22	#include <linux/export.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/module.h>
	25	#include <linux/dma-mapping.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/pci.h>
	28	#include <linux/firmware.h>
	29	#include <linux/pm_runtime.h>
	30
a4b12990 MB	31	#include "sst-dsp.h"
	32	#include "sst-dsp-priv.h"
	33	#include "sst-haswell-ipc.h"
	34
	35	#include <trace/events/hswadsp.h>
	36
	37	#define SST_HSW_FW_SIGNATURE_SIZE 4
	38	#define SST_HSW_FW_SIGN "$SST"
	39	#define SST_HSW_FW_LIB_SIGN "$LIB"
	40
	41	#define SST_WPT_SHIM_OFFSET 0xFB000
	42	#define SST_LP_SHIM_OFFSET 0xE7000
	43	#define SST_WPT_IRAM_OFFSET 0xA0000
	44	#define SST_LP_IRAM_OFFSET 0x80000
	45
	46	#define SST_SHIM_PM_REG 0x84
	47
	48	#define SST_HSW_IRAM 1
	49	#define SST_HSW_DRAM 2
	50	#define SST_HSW_REGS 3
	51
	52	struct dma_block_info {
	53	__le32 type; /* IRAM/DRAM */
	54	__le32 size; /* Bytes */
	55	__le32 ram_offset; /* Offset in I/DRAM */
	56	__le32 rsvd; /* Reserved field */
	57	} __attribute__((packed));
	58
	59	struct fw_module_info {
	60	__le32 persistent_size;
	61	__le32 scratch_size;
	62	} __attribute__((packed));
	63
	64	struct fw_header {
	65	unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* FW signature */
	66	__le32 file_size; /* size of fw minus this header */
	67	__le32 modules; /* # of modules */
	68	__le32 file_format; /* version of header format */
	69	__le32 reserved[4];
	70	} __attribute__((packed));
	71
	72	struct fw_module_header {
	73	unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* module signature */
	74	__le32 mod_size; /* size of module */
	75	__le32 blocks; /* # of blocks */
	76	__le16 padding;
	77	__le16 type; /* codec type, pp lib */
	78	__le32 entry_point;
	79	struct fw_module_info info;
	80	} __attribute__((packed));
	81
	82	static void hsw_free(struct sst_dsp *sst);
	83
	84	static int hsw_parse_module(struct sst_dsp dsp, struct sst_fw fw,
	85	struct fw_module_header *module)
	86	{
	87	struct dma_block_info *block;
	88	struct sst_module *mod;
	89	struct sst_module_data block_data;
	90	struct sst_module_template template;
	91	int count;
	92	void __iomem *ram;
	93
	94	/* TODO: allowed module types need to be configurable */
95	if (module->type != SST_HSW_MODULE_BASE_FW
96	&& module->type != SST_HSW_MODULE_PCM_SYSTEM
97	&& module->type != SST_HSW_MODULE_PCM
98	&& module->type != SST_HSW_MODULE_PCM_REFERENCE
99	&& module->type != SST_HSW_MODULE_PCM_CAPTURE
100	&& module->type != SST_HSW_MODULE_LPAL)
101	return 0;
102
103	dev_dbg(dsp->dev, "new module sign 0x%s size 0x%x blocks 0x%x type 0x%x\n",
104	module->signature, module->mod_size,
105	module->blocks, module->type);
106	dev_dbg(dsp->dev, " entrypoint 0x%x\n", module->entry_point);
107	dev_dbg(dsp->dev, " persistent 0x%x scratch 0x%x\n",
108	module->info.persistent_size, module->info.scratch_size);
109
110	memset(&template, 0, sizeof(template));
111	template.id = module->type;
112	template.entry = module->entry_point;
113	template.p.size = module->info.persistent_size;
114	template.p.type = SST_MEM_DRAM;
115	template.p.data_type = SST_DATA_P;
116	template.s.size = module->info.scratch_size;
117	template.s.type = SST_MEM_DRAM;
118	template.s.data_type = SST_DATA_S;
119
120	mod = sst_module_new(fw, &template, NULL);
121	if (mod == NULL)
122	return -ENOMEM;
123
124	block = (void )module + sizeof(module);
125
126	for (count = 0; count < module->blocks; count++) {
127
128	if (block->size <= 0) {
129	dev_err(dsp->dev,
130	"error: block %d size invalid\n", count);
131	sst_module_free(mod);
132	return -EINVAL;
133	}
134
135	switch (block->type) {
136	case SST_HSW_IRAM:
137	ram = dsp->addr.lpe;
138	block_data.offset =
139	block->ram_offset + dsp->addr.iram_offset;
140	block_data.type = SST_MEM_IRAM;
141	break;
142	case SST_HSW_DRAM:
143	ram = dsp->addr.lpe;
144	block_data.offset = block->ram_offset;
145	block_data.type = SST_MEM_DRAM;
146	break;
147	default:
148	dev_err(dsp->dev, "error: bad type 0x%x for block 0x%x\n",
149	block->type, count);
150	sst_module_free(mod);
151	return -EINVAL;
152	}
153
154	block_data.size = block->size;
155	block_data.data_type = SST_DATA_M;
156	block_data.data = (void )block + sizeof(block);
157	block_data.data_offset = block_data.data - fw->dma_buf;
158
159	dev_dbg(dsp->dev, "copy firmware block %d type 0x%x "
160	"size 0x%x ==> ram %p offset 0x%x\n",
161	count, block->type, block->size, ram,
162	block->ram_offset);
163
164	sst_module_insert_fixed_block(mod, &block_data);
165
166	block = (void )block + sizeof(block) + block->size;
167	}
168	return 0;
169	}
170
171	static int hsw_parse_fw_image(struct sst_fw *sst_fw)
172	{
173	struct fw_header *header;
174	struct sst_module *scratch;
175	struct fw_module_header *module;
176	struct sst_dsp *dsp = sst_fw->dsp;
177	struct sst_hsw *hsw = sst_fw->private;
178	int ret, count;
179
180	/* Read the header information from the data pointer */
181	header = (struct fw_header *)sst_fw->dma_buf;
182
183	/* verify FW */
184	if ((strncmp(header->signature, SST_HSW_FW_SIGN, 4) != 0) \|\|
185	(sst_fw->size != header->file_size + sizeof(*header))) {
186	dev_err(dsp->dev, "error: invalid fw sign/filesize mismatch\n");
187	return -EINVAL;
188	}
189
190	dev_dbg(dsp->dev, "header size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
191	header->file_size, header->modules,
192	header->file_format, sizeof(*header));
193
194	/* parse each module */
195	module = (void )sst_fw->dma_buf + sizeof(header);
196	for (count = 0; count < header->modules; count++) {
197
198	/* module */
199	ret = hsw_parse_module(dsp, sst_fw, module);
200	if (ret < 0) {
201	dev_err(dsp->dev, "error: invalid module %d\n", count);
202	return ret;
203	}
204	module = (void )module + sizeof(module) + module->mod_size;
205	}
206
207	/* allocate persistent/scratch mem regions */
208	scratch = sst_mem_block_alloc_scratch(dsp);
209	if (scratch == NULL)
210	return -ENOMEM;
211
212	sst_hsw_set_scratch_module(hsw, scratch);
213
214	return 0;
215	}
216
217	static irqreturn_t hsw_irq(int irq, void *context)
218	{
219	struct sst_dsp sst = (struct sst_dsp ) context;
220	u32 isr;
221	int ret = IRQ_NONE;
222
223	spin_lock(&sst->spinlock);
224
225	/* Interrupt arrived, check src */
226	isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
227	if (isr & SST_ISRX_DONE) {
228	trace_sst_irq_done(isr,
229	sst_dsp_shim_read_unlocked(sst, SST_IMRX));
230
231	/* Mask Done interrupt before return */
232	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
233	SST_IMRX_DONE, SST_IMRX_DONE);
234	ret = IRQ_WAKE_THREAD;
235	}
236
237	if (isr & SST_ISRX_BUSY) {
238	trace_sst_irq_busy(isr,
239	sst_dsp_shim_read_unlocked(sst, SST_IMRX));
240
241	/* Mask Busy interrupt before return */
242	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
243	SST_IMRX_BUSY, SST_IMRX_BUSY);
244	ret = IRQ_WAKE_THREAD;
245	}
246
247	spin_unlock(&sst->spinlock);
248	return ret;
249	}
250
251	static void hsw_boot(struct sst_dsp *sst)
252	{
253	/* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */
254	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
255	SST_CSR_S1IOCS \| SST_CSR_SBCS1 \| SST_CSR_LPCS, 0x0);
256
257	/* stall DSP core, set clk to 192/96Mhz */
258	sst_dsp_shim_update_bits_unlocked(sst,
259	SST_CSR, SST_CSR_STALL \| SST_CSR_DCS_MASK,
260	SST_CSR_STALL \| SST_CSR_DCS(4));
261
262	/* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
263	sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
264	SST_CLKCTL_MASK \| SST_CLKCTL_DCPLCG \| SST_CLKCTL_SCOE0,
265	SST_CLKCTL_MASK \| SST_CLKCTL_DCPLCG \| SST_CLKCTL_SCOE0);
266
267	/* disable DMA finish function for SSP0 & SSP1 */
268	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,
269	SST_CSR2_SDFD_SSP1);
270
271	/* enable DMA engine 0,1 all channels to access host memory */
272	sst_dsp_shim_update_bits_unlocked(sst, SST_HDMC,
273	SST_HDMC_HDDA1(0xff) \| SST_HDMC_HDDA0(0xff),
274	SST_HDMC_HDDA1(0xff) \| SST_HDMC_HDDA0(0xff));
275
276	/* disable all clock gating */
277	writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2);
278
279	/* set DSP to RUN */
280	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_STALL, 0x0);
281	}
282
283	static void hsw_reset(struct sst_dsp *sst)
284	{
285	/* put DSP into reset and stall */
286	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
287	SST_CSR_RST \| SST_CSR_STALL, SST_CSR_RST \| SST_CSR_STALL);
288
289	/* keep in reset for 10ms */
290	mdelay(10);
291
292	/* take DSP out of reset and keep stalled for FW loading */
293	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
294	SST_CSR_RST \| SST_CSR_STALL, SST_CSR_STALL);
295	}
296
297	struct sst_adsp_memregion {
298	u32 start;
299	u32 end;
300	int blocks;
301	enum sst_mem_type type;
302	};
303
304	/* lynx point ADSP mem regions */
305	static const struct sst_adsp_memregion lp_region[] = {
306	{0x00000, 0x40000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
307	{0x40000, 0x80000, 8, SST_MEM_DRAM}, /* D-SRAM1 - 8 * 32kB */
308	{0x80000, 0xE0000, 12, SST_MEM_IRAM}, /* I-SRAM - 12 * 32kB */
309	};
310
311	/* wild cat point ADSP mem regions */
312	static const struct sst_adsp_memregion wpt_region[] = {
15446c0b	313	{0x00000, 0xA0000, 20, SST_MEM_DRAM}, /* D-SRAM0,D-SRAM1,D-SRAM2 - 20 * 32kB */
a4b12990 MB	314	{0xA0000, 0xF0000, 10, SST_MEM_IRAM}, /* I-SRAM - 10 * 32kB */
	315	};
	316
	317	static int hsw_acpi_resource_map(struct sst_dsp sst, struct sst_pdata pdata)
	318	{
	319	/* ADSP DRAM & IRAM */
	320	sst->addr.lpe_base = pdata->lpe_base;
	321	sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
	322	if (!sst->addr.lpe)
	323	return -ENODEV;
	324
	325	/* ADSP PCI MMIO config space */
	326	sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
	327	if (!sst->addr.pci_cfg) {
	328	iounmap(sst->addr.lpe);
	329	return -ENODEV;
	330	}
	331
	332	/* SST Shim */
	333	sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
	334	return 0;
	335	}
	336
54879323 JY	337	struct sst_sram_shift {
	338	u32 dev_id; /* SST Device IDs */
	339	u32 iram_shift;
	340	u32 dram_shift;
	341	};
	342
	343	static const struct sst_sram_shift sram_shift[] = {
	344	{SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */
	345	{SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */
	346	};
a4b12990 MB	347	static u32 hsw_block_get_bit(struct sst_mem_block *block)
a4b12990 MB	348	{
54879323 JY	349	u32 bit = 0, shift = 0, index;
	350	struct sst_dsp *sst = block->dsp;
	351
	352	for (index = 0; index < ARRAY_SIZE(sram_shift); index++) {
	353	if (sram_shift[index].dev_id == sst->id)
	354	break;
a4b12990 MB	355	}
a4b12990 MB	356
54879323 JY	357	if (index < ARRAY_SIZE(sram_shift)) {
	358	switch (block->type) {
	359	case SST_MEM_DRAM:
	360	shift = sram_shift[index].dram_shift;
	361	break;
	362	case SST_MEM_IRAM:
	363	shift = sram_shift[index].iram_shift;
	364	break;
	365	default:
	366	shift = 0;
	367	}
	368	} else
	369	shift = 0;
	370
a4b12990 MB	371	bit = 1 << (block->index + shift);
	372
	373	return bit;
	374	}
	375
	376	/* enable 32kB memory block - locks held by caller */
	377	static int hsw_block_enable(struct sst_mem_block *block)
	378	{
	379	struct sst_dsp *sst = block->dsp;
	380	u32 bit, val;
	381
	382	if (block->users++ > 0)
	383	return 0;
	384
	385	dev_dbg(block->dsp->dev, " enabled block %d:%d at offset 0x%x\n",
	386	block->type, block->index, block->offset);
	387
	388	val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
	389	bit = hsw_block_get_bit(block);
	390	writel(val & ~bit, sst->addr.pci_cfg + SST_VDRTCTL0);
	391
	392	/* wait 18 DSP clock ticks */
	393	udelay(10);
	394
	395	return 0;
	396	}
	397
	398	/* disable 32kB memory block - locks held by caller */
	399	static int hsw_block_disable(struct sst_mem_block *block)
	400	{
	401	struct sst_dsp *sst = block->dsp;
	402	u32 bit, val;
	403
	404	if (--block->users > 0)
	405	return 0;
	406
	407	dev_dbg(block->dsp->dev, " disabled block %d:%d at offset 0x%x\n",
	408	block->type, block->index, block->offset);
	409
	410	val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
	411	bit = hsw_block_get_bit(block);
	412	writel(val \| bit, sst->addr.pci_cfg + SST_VDRTCTL0);
	413
	414	return 0;
	415	}
	416
	417	static struct sst_block_ops sst_hsw_ops = {
	418	.enable = hsw_block_enable,
	419	.disable = hsw_block_disable,
	420	};
	421
	422	static int hsw_enable_shim(struct sst_dsp *sst)
	423	{
	424	int tries = 10;
	425	u32 reg;
	426
	427	/* enable shim */
	428	reg = readl(sst->addr.pci_cfg + SST_SHIM_PM_REG);
	429	writel(reg & ~0x3, sst->addr.pci_cfg + SST_SHIM_PM_REG);
	430
	431	/* check that ADSP shim is enabled */
	432	while (tries--) {
	433	reg = sst_dsp_shim_read_unlocked(sst, SST_CSR);
	434	if (reg != 0xffffffff)
435	return 0;
436
437	msleep(1);
438	}
439
440	return -ENODEV;
441	}
442
443	static int hsw_init(struct sst_dsp sst, struct sst_pdata pdata)
444	{
445	const struct sst_adsp_memregion *region;
446	struct device *dev;
447	int ret = -ENODEV, i, j, region_count;
448	u32 offset, size;
449
10df3509	450	dev = sst->dma_dev;
a4b12990 MB	451
	452	switch (sst->id) {
	453	case SST_DEV_ID_LYNX_POINT:
	454	region = lp_region;
	455	region_count = ARRAY_SIZE(lp_region);
	456	sst->addr.iram_offset = SST_LP_IRAM_OFFSET;
	457	sst->addr.shim_offset = SST_LP_SHIM_OFFSET;
	458	break;
	459	case SST_DEV_ID_WILDCAT_POINT:
	460	region = wpt_region;
	461	region_count = ARRAY_SIZE(wpt_region);
	462	sst->addr.iram_offset = SST_WPT_IRAM_OFFSET;
	463	sst->addr.shim_offset = SST_WPT_SHIM_OFFSET;
	464	break;
	465	default:
	466	dev_err(dev, "error: failed to get mem resources\n");
	467	return ret;
	468	}
	469
	470	ret = hsw_acpi_resource_map(sst, pdata);
	471	if (ret < 0) {
	472	dev_err(dev, "error: failed to map resources\n");
	473	return ret;
	474	}
	475
	476	/* enable the DSP SHIM */
	477	ret = hsw_enable_shim(sst);
	478	if (ret < 0) {
	479	dev_err(dev, "error: failed to set DSP D0 and reset SHIM\n");
	480	return ret;
	481	}
	482
10df3509	483	ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(31));
a4b12990 MB	484	if (ret)
	485	return ret;
	486
	487	/* Enable Interrupt from both sides */
	488	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX, 0x3, 0x0);
	489	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRD,
	490	(0x3 \| 0x1 << 16 \| 0x3 << 21), 0x0);
	491
	492	/* register DSP memory blocks - ideally we should get this from ACPI */
	493	for (i = 0; i < region_count; i++) {
	494	offset = region[i].start;
	495	size = (region[i].end - region[i].start) / region[i].blocks;
	496
	497	/* register individual memory blocks */
	498	for (j = 0; j < region[i].blocks; j++) {
	499	sst_mem_block_register(sst, offset, size,
	500	region[i].type, &sst_hsw_ops, j, sst);
	501	offset += size;
	502	}
	503	}
	504
85e63007 JY	505	/* set default power gating control, enable power gating control for all blocks. that is,
	506	can't be accessed, please enable each block before accessing. */
	507	writel(0xffffffff, sst->addr.pci_cfg + SST_VDRTCTL0);
a4b12990 MB	508
	509	return 0;
	510	}
	511
	512	static void hsw_free(struct sst_dsp *sst)
	513	{
	514	sst_mem_block_unregister_all(sst);
	515	iounmap(sst->addr.lpe);
	516	iounmap(sst->addr.pci_cfg);
	517	}
	518
	519	struct sst_ops haswell_ops = {
	520	.reset = hsw_reset,
	521	.boot = hsw_boot,
	522	.write = sst_shim32_write,
	523	.read = sst_shim32_read,
	524	.write64 = sst_shim32_write64,
	525	.read64 = sst_shim32_read64,
	526	.ram_read = sst_memcpy_fromio_32,
	527	.ram_write = sst_memcpy_toio_32,
	528	.irq_handler = hsw_irq,
	529	.init = hsw_init,
	530	.free = hsw_free,
	531	.parse_fw = hsw_parse_fw_image,
	532	};