[deliverable/linux.git] / sound / soc / intel / sst-haswell-dsp.c

/*
 * Intel Haswell SST DSP driver
 *
 * Copyright (C) 2013, Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/sched.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/firmware.h>
#include <linux/pm_runtime.h>

#include "sst-dsp.h"
#include "sst-dsp-priv.h"
#include "sst-haswell-ipc.h"

#include <trace/events/hswadsp.h>

#define SST_HSW_FW_SIGNATURE_SIZE	4
#define SST_HSW_FW_SIGN			"$SST"
#define SST_HSW_FW_LIB_SIGN		"$LIB"

#define SST_WPT_SHIM_OFFSET	0xFB000
#define SST_LP_SHIM_OFFSET	0xE7000
#define SST_WPT_IRAM_OFFSET	0xA0000
#define SST_LP_IRAM_OFFSET	0x80000
#define SST_WPT_DSP_DRAM_OFFSET	0x400000
#define SST_WPT_DSP_IRAM_OFFSET	0x00000
#define SST_LPT_DSP_DRAM_OFFSET	0x400000
#define SST_LPT_DSP_IRAM_OFFSET	0x00000

#define SST_SHIM_PM_REG		0x84

#define SST_HSW_IRAM	1
#define SST_HSW_DRAM	2
#define SST_HSW_REGS	3

struct dma_block_info {
	__le32 type;		/* IRAM/DRAM */
	__le32 size;		/* Bytes */
	__le32 ram_offset;	/* Offset in I/DRAM */
	__le32 rsvd;		/* Reserved field */
} __attribute__((packed));

struct fw_module_info {
	__le32 persistent_size;
	__le32 scratch_size;
} __attribute__((packed));

struct fw_header {
	unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* FW signature */
	__le32 file_size;		/* size of fw minus this header */
	__le32 modules;		/*  # of modules */
	__le32 file_format;	/* version of header format */
	__le32 reserved[4];
} __attribute__((packed));

struct fw_module_header {
	unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* module signature */
	__le32 mod_size;	/* size of module */
	__le32 blocks;	/* # of blocks */
	__le16 padding;
	__le16 type;	/* codec type, pp lib */
	__le32 entry_point;
	struct fw_module_info info;
} __attribute__((packed));

static void hsw_free(struct sst_dsp *sst);

static int hsw_parse_module(struct sst_dsp *dsp, struct sst_fw *fw,
	struct fw_module_header *module)
{
	struct dma_block_info *block;
	struct sst_module *mod;
	struct sst_module_template template;
	int count, ret;
	void __iomem *ram;

	/* TODO: allowed module types need to be configurable */
	if (module->type != SST_HSW_MODULE_BASE_FW
		&& module->type != SST_HSW_MODULE_PCM_SYSTEM
		&& module->type != SST_HSW_MODULE_PCM
		&& module->type != SST_HSW_MODULE_PCM_REFERENCE
		&& module->type != SST_HSW_MODULE_PCM_CAPTURE
		&& module->type != SST_HSW_MODULE_LPAL)
		return 0;

	dev_dbg(dsp->dev, "new module sign 0x%s size 0x%x blocks 0x%x type 0x%x\n",
		module->signature, module->mod_size,
		module->blocks, module->type);
	dev_dbg(dsp->dev, " entrypoint 0x%x\n", module->entry_point);
	dev_dbg(dsp->dev, " persistent 0x%x scratch 0x%x\n",
		module->info.persistent_size, module->info.scratch_size);

	memset(&template, 0, sizeof(template));
	template.id = module->type;
	template.entry = module->entry_point - 4;
	template.persistent_size = module->info.persistent_size;
	template.scratch_size = module->info.scratch_size;

	mod = sst_module_new(fw, &template, NULL);
	if (mod == NULL)
		return -ENOMEM;

	block = (void *)module + sizeof(*module);

	for (count = 0; count < module->blocks; count++) {

		if (block->size <= 0) {
			dev_err(dsp->dev,
				"error: block %d size invalid\n", count);
			sst_module_free(mod);
			return -EINVAL;
		}

		switch (block->type) {
		case SST_HSW_IRAM:
			ram = dsp->addr.lpe;
			mod->offset =
				block->ram_offset + dsp->addr.iram_offset;
			mod->type = SST_MEM_IRAM;
			break;
		case SST_HSW_DRAM:
			ram = dsp->addr.lpe;
			mod->offset = block->ram_offset;
			mod->type = SST_MEM_DRAM;
			break;
		default:
			dev_err(dsp->dev, "error: bad type 0x%x for block 0x%x\n",
				block->type, count);
			sst_module_free(mod);
			return -EINVAL;
		}

		mod->size = block->size;
		mod->data = (void *)block + sizeof(*block);
		mod->data_offset = mod->data - fw->dma_buf;

		dev_dbg(dsp->dev, "module block %d type 0x%x "
			"size 0x%x ==> ram %p offset 0x%x\n",
			count, mod->type, block->size, ram,
			block->ram_offset);

		ret = sst_module_alloc_blocks(mod);
		if (ret < 0) {
			dev_err(dsp->dev, "error: could not allocate blocks for module %d\n",
				count);
			sst_module_free(mod);
			return ret;
		}

		block = (void *)block + sizeof(*block) + block->size;
	}

	return 0;
}

static int hsw_parse_fw_image(struct sst_fw *sst_fw)
{
	struct fw_header *header;
	struct fw_module_header *module;
	struct sst_dsp *dsp = sst_fw->dsp;
	int ret, count;

	/* Read the header information from the data pointer */
	header = (struct fw_header *)sst_fw->dma_buf;

	/* verify FW */
	if ((strncmp(header->signature, SST_HSW_FW_SIGN, 4) != 0) ||
		(sst_fw->size != header->file_size + sizeof(*header))) {
		dev_err(dsp->dev, "error: invalid fw sign/filesize mismatch\n");
		return -EINVAL;
	}

	dev_dbg(dsp->dev, "header size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
		header->file_size, header->modules,
		header->file_format, sizeof(*header));

	/* parse each module */
	module = (void *)sst_fw->dma_buf + sizeof(*header);
	for (count = 0; count < header->modules; count++) {

		/* module */
		ret = hsw_parse_module(dsp, sst_fw, module);
		if (ret < 0) {
			dev_err(dsp->dev, "error: invalid module %d\n", count);
			return ret;
		}
		module = (void *)module + sizeof(*module) + module->mod_size;
	}

	/* allocate scratch mem regions */
	sst_block_alloc_scratch(dsp);

	return 0;
}

static irqreturn_t hsw_irq(int irq, void *context)
{
	struct sst_dsp *sst = (struct sst_dsp *) context;
	u32 isr;
	int ret = IRQ_NONE;

	spin_lock(&sst->spinlock);

	/* Interrupt arrived, check src */
	isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
	if (isr & SST_ISRX_DONE) {
		trace_sst_irq_done(isr,
			sst_dsp_shim_read_unlocked(sst, SST_IMRX));

		/* Mask Done interrupt before return */
		sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
			SST_IMRX_DONE, SST_IMRX_DONE);
		ret = IRQ_WAKE_THREAD;
	}

	if (isr & SST_ISRX_BUSY) {
		trace_sst_irq_busy(isr,
			sst_dsp_shim_read_unlocked(sst, SST_IMRX));

		/* Mask Busy interrupt before return */
		sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
			SST_IMRX_BUSY, SST_IMRX_BUSY);
		ret = IRQ_WAKE_THREAD;
	}

	spin_unlock(&sst->spinlock);
	return ret;
}

static void hsw_boot(struct sst_dsp *sst)
{
	/* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
		SST_CSR_S1IOCS | SST_CSR_SBCS1 | SST_CSR_LPCS, 0x0);

	/* stall DSP core, set clk to 192/96Mhz */
	sst_dsp_shim_update_bits_unlocked(sst,
		SST_CSR, SST_CSR_STALL | SST_CSR_DCS_MASK,
		SST_CSR_STALL | SST_CSR_DCS(4));

	/* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
		SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0,
		SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0);

	/* disable DMA finish function for SSP0 & SSP1 */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,
		SST_CSR2_SDFD_SSP1);

	/* enable DMA engine 0,1 all channels to access host memory */
	sst_dsp_shim_update_bits_unlocked(sst, SST_HMDC,
		SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff),
		SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff));

	/* disable all clock gating */
	writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2);

	/* set DSP to RUN */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_STALL, 0x0);
}

static void hsw_reset(struct sst_dsp *sst)
{
	/* put DSP into reset and stall */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
		SST_CSR_RST | SST_CSR_STALL, SST_CSR_RST | SST_CSR_STALL);

	/* keep in reset for 10ms */
	mdelay(10);

	/* take DSP out of reset and keep stalled for FW loading */
	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
		SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL);
}

struct sst_adsp_memregion {
	u32 start;
	u32 end;
	int blocks;
	enum sst_mem_type type;
};

/* lynx point ADSP mem regions */
static const struct sst_adsp_memregion lp_region[] = {
	{0x00000, 0x40000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
	{0x40000, 0x80000, 8, SST_MEM_DRAM}, /* D-SRAM1 - 8 * 32kB */
	{0x80000, 0xE0000, 12, SST_MEM_IRAM}, /* I-SRAM - 12 * 32kB */
};

/* wild cat point ADSP mem regions */
static const struct sst_adsp_memregion wpt_region[] = {
	{0x00000, 0xA0000, 20, SST_MEM_DRAM}, /* D-SRAM0,D-SRAM1,D-SRAM2 - 20 * 32kB */
	{0xA0000, 0xF0000, 10, SST_MEM_IRAM}, /* I-SRAM - 10 * 32kB */
};

static int hsw_acpi_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)
{
	/* ADSP DRAM & IRAM */
	sst->addr.lpe_base = pdata->lpe_base;
	sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
	if (!sst->addr.lpe)
		return -ENODEV;

	/* ADSP PCI MMIO config space */
	sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
	if (!sst->addr.pci_cfg) {
		iounmap(sst->addr.lpe);
		return -ENODEV;
	}

	/* SST Shim */
	sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
	return 0;
}

struct sst_sram_shift {
	u32 dev_id;	/* SST Device IDs  */
	u32 iram_shift;
	u32 dram_shift;
};

static const struct sst_sram_shift sram_shift[] = {
	{SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */
	{SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */
};
static u32 hsw_block_get_bit(struct sst_mem_block *block)
{
	u32 bit = 0, shift = 0, index;
	struct sst_dsp *sst = block->dsp;

	for (index = 0; index < ARRAY_SIZE(sram_shift); index++) {
		if (sram_shift[index].dev_id == sst->id)
			break;
	}

	if (index < ARRAY_SIZE(sram_shift)) {
		switch (block->type) {
		case SST_MEM_DRAM:
			shift = sram_shift[index].dram_shift;
			break;
		case SST_MEM_IRAM:
			shift = sram_shift[index].iram_shift;
			break;
		default:
			shift = 0;
		}
	} else
		shift = 0;

	bit = 1 << (block->index + shift);

	return bit;
}

/*dummy read a SRAM block.*/
static void sst_mem_block_dummy_read(struct sst_mem_block *block)
{
	u32 size;
	u8 tmp_buf[4];
	struct sst_dsp *sst = block->dsp;

	size = block->size > 4 ? 4 : block->size;
	memcpy_fromio(tmp_buf, sst->addr.lpe + block->offset, size);
}

/* enable 32kB memory block - locks held by caller */
static int hsw_block_enable(struct sst_mem_block *block)
{
	struct sst_dsp *sst = block->dsp;
	u32 bit, val;

	if (block->users++ > 0)
		return 0;

	dev_dbg(block->dsp->dev, " enabled block %d:%d at offset 0x%x\n",
		block->type, block->index, block->offset);

	val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
	bit = hsw_block_get_bit(block);
	writel(val & ~bit, sst->addr.pci_cfg + SST_VDRTCTL0);

	/* wait 18 DSP clock ticks */
	udelay(10);

	/*add a dummy read before the SRAM block is written, otherwise the writing may miss bytes sometimes.*/
	sst_mem_block_dummy_read(block);
	return 0;
}

/* disable 32kB memory block - locks held by caller */
static int hsw_block_disable(struct sst_mem_block *block)
{
	struct sst_dsp *sst = block->dsp;
	u32 bit, val;

	if (--block->users > 0)
		return 0;

	dev_dbg(block->dsp->dev, " disabled block %d:%d at offset 0x%x\n",
		block->type, block->index, block->offset);

	val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
	bit = hsw_block_get_bit(block);
	writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0);

	return 0;
}

static struct sst_block_ops sst_hsw_ops = {
	.enable = hsw_block_enable,
	.disable = hsw_block_disable,
};

static int hsw_enable_shim(struct sst_dsp *sst)
{
	int tries = 10;
	u32 reg;

	/* enable shim */
	reg = readl(sst->addr.pci_cfg + SST_SHIM_PM_REG);
	writel(reg & ~0x3, sst->addr.pci_cfg + SST_SHIM_PM_REG);

	/* check that ADSP shim is enabled */
	while (tries--) {
		reg = sst_dsp_shim_read_unlocked(sst, SST_CSR);
		if (reg != 0xffffffff)
			return 0;

		msleep(1);
	}

	return -ENODEV;
}

static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)
{
	const struct sst_adsp_memregion *region;
	struct device *dev;
	int ret = -ENODEV, i, j, region_count;
	u32 offset, size;

	dev = sst->dma_dev;

	switch (sst->id) {
	case SST_DEV_ID_LYNX_POINT:
		region = lp_region;
		region_count = ARRAY_SIZE(lp_region);
		sst->addr.iram_offset = SST_LP_IRAM_OFFSET;
		sst->addr.dsp_iram_offset = SST_LPT_DSP_IRAM_OFFSET;
		sst->addr.dsp_dram_offset = SST_LPT_DSP_DRAM_OFFSET;
		sst->addr.shim_offset = SST_LP_SHIM_OFFSET;
		break;
	case SST_DEV_ID_WILDCAT_POINT:
		region = wpt_region;
		region_count = ARRAY_SIZE(wpt_region);
		sst->addr.iram_offset = SST_WPT_IRAM_OFFSET;
		sst->addr.dsp_iram_offset = SST_WPT_DSP_IRAM_OFFSET;
		sst->addr.dsp_dram_offset = SST_WPT_DSP_DRAM_OFFSET;
		sst->addr.shim_offset = SST_WPT_SHIM_OFFSET;
		break;
	default:
		dev_err(dev, "error: failed to get mem resources\n");
		return ret;
	}

	ret = hsw_acpi_resource_map(sst, pdata);
	if (ret < 0) {
		dev_err(dev, "error: failed to map resources\n");
		return ret;
	}

	/* enable the DSP SHIM */
	ret = hsw_enable_shim(sst);
	if (ret < 0) {
		dev_err(dev, "error: failed to set DSP D0 and reset SHIM\n");
		return ret;
	}

	ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(31));
	if (ret)
		return ret;

	/* Enable Interrupt from both sides */
	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX, 0x3, 0x0);
	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRD,
		(0x3 | 0x1 << 16 | 0x3 << 21), 0x0);

	/* register DSP memory blocks - ideally we should get this from ACPI */
	for (i = 0; i < region_count; i++) {
		offset = region[i].start;
		size = (region[i].end - region[i].start) / region[i].blocks;

		/* register individual memory blocks */
		for (j = 0; j < region[i].blocks; j++) {
			sst_mem_block_register(sst, offset, size,
				region[i].type, &sst_hsw_ops, j, sst);
			offset += size;
		}
	}

	/* set default power gating control, enable power gating control for all blocks. that is,
	can't be accessed, please enable each block before accessing. */
	writel(0xffffffff, sst->addr.pci_cfg + SST_VDRTCTL0);

	return 0;
}

static void hsw_free(struct sst_dsp *sst)
{
	sst_mem_block_unregister_all(sst);
	iounmap(sst->addr.lpe);
	iounmap(sst->addr.pci_cfg);
}

struct sst_ops haswell_ops = {
	.reset = hsw_reset,
	.boot = hsw_boot,
	.write = sst_shim32_write,
	.read = sst_shim32_read,
	.write64 = sst_shim32_write64,
	.read64 = sst_shim32_read64,
	.ram_read = sst_memcpy_fromio_32,
	.ram_write = sst_memcpy_toio_32,
	.irq_handler = hsw_irq,
	.init = hsw_init,
	.free = hsw_free,
	.parse_fw = hsw_parse_fw_image,
};
Commit	Line	Data
a4b12990 MB	1	/*
	2	* Intel Haswell SST DSP driver
	3	*
	4	* Copyright (C) 2013, Intel Corporation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License version
	8	* 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
	17	#include <linux/delay.h>
	18	#include <linux/fs.h>
	19	#include <linux/slab.h>
	20	#include <linux/device.h>
	21	#include <linux/sched.h>
	22	#include <linux/export.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/module.h>
	25	#include <linux/dma-mapping.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/pci.h>
	28	#include <linux/firmware.h>
	29	#include <linux/pm_runtime.h>
	30
a4b12990 MB	31	#include "sst-dsp.h"
	32	#include "sst-dsp-priv.h"
	33	#include "sst-haswell-ipc.h"
	34
	35	#include <trace/events/hswadsp.h>
	36
	37	#define SST_HSW_FW_SIGNATURE_SIZE 4
	38	#define SST_HSW_FW_SIGN "$SST"
	39	#define SST_HSW_FW_LIB_SIGN "$LIB"
	40
	41	#define SST_WPT_SHIM_OFFSET 0xFB000
	42	#define SST_LP_SHIM_OFFSET 0xE7000
	43	#define SST_WPT_IRAM_OFFSET 0xA0000
	44	#define SST_LP_IRAM_OFFSET 0x80000
e9600bc1 LG	45	#define SST_WPT_DSP_DRAM_OFFSET 0x400000
	46	#define SST_WPT_DSP_IRAM_OFFSET 0x00000
	47	#define SST_LPT_DSP_DRAM_OFFSET 0x400000
	48	#define SST_LPT_DSP_IRAM_OFFSET 0x00000
a4b12990 MB	49
	50	#define SST_SHIM_PM_REG 0x84
	51
	52	#define SST_HSW_IRAM 1
	53	#define SST_HSW_DRAM 2
	54	#define SST_HSW_REGS 3
	55
	56	struct dma_block_info {
	57	__le32 type; /* IRAM/DRAM */
	58	__le32 size; /* Bytes */
	59	__le32 ram_offset; /* Offset in I/DRAM */
	60	__le32 rsvd; /* Reserved field */
	61	} __attribute__((packed));
	62
	63	struct fw_module_info {
	64	__le32 persistent_size;
	65	__le32 scratch_size;
	66	} __attribute__((packed));
	67
	68	struct fw_header {
	69	unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* FW signature */
	70	__le32 file_size; /* size of fw minus this header */
	71	__le32 modules; /* # of modules */
	72	__le32 file_format; /* version of header format */
	73	__le32 reserved[4];
	74	} __attribute__((packed));
	75
	76	struct fw_module_header {
	77	unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* module signature */
	78	__le32 mod_size; /* size of module */
	79	__le32 blocks; /* # of blocks */
	80	__le16 padding;
	81	__le16 type; /* codec type, pp lib */
	82	__le32 entry_point;
	83	struct fw_module_info info;
	84	} __attribute__((packed));
	85
	86	static void hsw_free(struct sst_dsp *sst);
	87
	88	static int hsw_parse_module(struct sst_dsp dsp, struct sst_fw fw,
	89	struct fw_module_header *module)
	90	{
	91	struct dma_block_info *block;
	92	struct sst_module *mod;
a4b12990	93	struct sst_module_template template;
e9600bc1	94	int count, ret;
a4b12990 MB	95	void __iomem *ram;
	96
	97	/* TODO: allowed module types need to be configurable */
	98	if (module->type != SST_HSW_MODULE_BASE_FW
	99	&& module->type != SST_HSW_MODULE_PCM_SYSTEM
	100	&& module->type != SST_HSW_MODULE_PCM
	101	&& module->type != SST_HSW_MODULE_PCM_REFERENCE
	102	&& module->type != SST_HSW_MODULE_PCM_CAPTURE
	103	&& module->type != SST_HSW_MODULE_LPAL)
	104	return 0;
	105
	106	dev_dbg(dsp->dev, "new module sign 0x%s size 0x%x blocks 0x%x type 0x%x\n",
	107	module->signature, module->mod_size,
	108	module->blocks, module->type);
	109	dev_dbg(dsp->dev, " entrypoint 0x%x\n", module->entry_point);
	110	dev_dbg(dsp->dev, " persistent 0x%x scratch 0x%x\n",
	111	module->info.persistent_size, module->info.scratch_size);
	112
	113	memset(&template, 0, sizeof(template));
	114	template.id = module->type;
e9600bc1 LG	115	template.entry = module->entry_point - 4;
	116	template.persistent_size = module->info.persistent_size;
	117	template.scratch_size = module->info.scratch_size;
a4b12990 MB	118
	119	mod = sst_module_new(fw, &template, NULL);
	120	if (mod == NULL)
	121	return -ENOMEM;
	122
	123	block = (void )module + sizeof(module);
	124
	125	for (count = 0; count < module->blocks; count++) {
	126
	127	if (block->size <= 0) {
	128	dev_err(dsp->dev,
	129	"error: block %d size invalid\n", count);
	130	sst_module_free(mod);
	131	return -EINVAL;
	132	}
	133
	134	switch (block->type) {
	135	case SST_HSW_IRAM:
	136	ram = dsp->addr.lpe;
e9600bc1	137	mod->offset =
a4b12990	138	block->ram_offset + dsp->addr.iram_offset;
e9600bc1	139	mod->type = SST_MEM_IRAM;
a4b12990 MB	140	break;
	141	case SST_HSW_DRAM:
	142	ram = dsp->addr.lpe;
e9600bc1 LG	143	mod->offset = block->ram_offset;
e9600bc1 LG	144	mod->type = SST_MEM_DRAM;
a4b12990 MB	145	break;
	146	default:
	147	dev_err(dsp->dev, "error: bad type 0x%x for block 0x%x\n",
	148	block->type, count);
	149	sst_module_free(mod);
	150	return -EINVAL;
	151	}
	152
e9600bc1 LG	153	mod->size = block->size;
	154	mod->data = (void )block + sizeof(block);
	155	mod->data_offset = mod->data - fw->dma_buf;
a4b12990	156
e9600bc1	157	dev_dbg(dsp->dev, "module block %d type 0x%x "
a4b12990	158	"size 0x%x ==> ram %p offset 0x%x\n",
e9600bc1	159	count, mod->type, block->size, ram,
a4b12990 MB	160	block->ram_offset);
a4b12990 MB	161
e9600bc1 LG	162	ret = sst_module_alloc_blocks(mod);
	163	if (ret < 0) {
	164	dev_err(dsp->dev, "error: could not allocate blocks for module %d\n",
	165	count);
	166	sst_module_free(mod);
	167	return ret;
	168	}
a4b12990 MB	169
	170	block = (void )block + sizeof(block) + block->size;
	171	}
e9600bc1	172
a4b12990 MB	173	return 0;
	174	}
	175
	176	static int hsw_parse_fw_image(struct sst_fw *sst_fw)
	177	{
	178	struct fw_header *header;
a4b12990 MB	179	struct fw_module_header *module;
a4b12990 MB	180	struct sst_dsp *dsp = sst_fw->dsp;
a4b12990 MB	181	int ret, count;
	182
	183	/* Read the header information from the data pointer */
	184	header = (struct fw_header *)sst_fw->dma_buf;
	185
	186	/* verify FW */
	187	if ((strncmp(header->signature, SST_HSW_FW_SIGN, 4) != 0) \|\|
	188	(sst_fw->size != header->file_size + sizeof(*header))) {
	189	dev_err(dsp->dev, "error: invalid fw sign/filesize mismatch\n");
	190	return -EINVAL;
	191	}
	192
	193	dev_dbg(dsp->dev, "header size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
	194	header->file_size, header->modules,
	195	header->file_format, sizeof(*header));
	196
	197	/* parse each module */
	198	module = (void )sst_fw->dma_buf + sizeof(header);
	199	for (count = 0; count < header->modules; count++) {
	200
	201	/* module */
	202	ret = hsw_parse_module(dsp, sst_fw, module);
	203	if (ret < 0) {
	204	dev_err(dsp->dev, "error: invalid module %d\n", count);
	205	return ret;
	206	}
	207	module = (void )module + sizeof(module) + module->mod_size;
	208	}
	209
e9600bc1 LG	210	/* allocate scratch mem regions */
e9600bc1 LG	211	sst_block_alloc_scratch(dsp);
a4b12990 MB	212
	213	return 0;
	214	}
	215
	216	static irqreturn_t hsw_irq(int irq, void *context)
	217	{
	218	struct sst_dsp sst = (struct sst_dsp ) context;
	219	u32 isr;
	220	int ret = IRQ_NONE;
	221
	222	spin_lock(&sst->spinlock);
	223
	224	/* Interrupt arrived, check src */
	225	isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
	226	if (isr & SST_ISRX_DONE) {
	227	trace_sst_irq_done(isr,
	228	sst_dsp_shim_read_unlocked(sst, SST_IMRX));
	229
	230	/* Mask Done interrupt before return */
	231	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
	232	SST_IMRX_DONE, SST_IMRX_DONE);
	233	ret = IRQ_WAKE_THREAD;
	234	}
	235
	236	if (isr & SST_ISRX_BUSY) {
	237	trace_sst_irq_busy(isr,
	238	sst_dsp_shim_read_unlocked(sst, SST_IMRX));
	239
	240	/* Mask Busy interrupt before return */
	241	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
	242	SST_IMRX_BUSY, SST_IMRX_BUSY);
	243	ret = IRQ_WAKE_THREAD;
	244	}
	245
	246	spin_unlock(&sst->spinlock);
	247	return ret;
	248	}
	249
	250	static void hsw_boot(struct sst_dsp *sst)
	251	{
	252	/* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */
	253	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
	254	SST_CSR_S1IOCS \| SST_CSR_SBCS1 \| SST_CSR_LPCS, 0x0);
	255
	256	/* stall DSP core, set clk to 192/96Mhz */
	257	sst_dsp_shim_update_bits_unlocked(sst,
	258	SST_CSR, SST_CSR_STALL \| SST_CSR_DCS_MASK,
	259	SST_CSR_STALL \| SST_CSR_DCS(4));
	260
	261	/* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
	262	sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
	263	SST_CLKCTL_MASK \| SST_CLKCTL_DCPLCG \| SST_CLKCTL_SCOE0,
	264	SST_CLKCTL_MASK \| SST_CLKCTL_DCPLCG \| SST_CLKCTL_SCOE0);
	265
	266	/* disable DMA finish function for SSP0 & SSP1 */
	267	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,
	268	SST_CSR2_SDFD_SSP1);
	269
	270	/* enable DMA engine 0,1 all channels to access host memory */
ee4a6ce6 LG	271	sst_dsp_shim_update_bits_unlocked(sst, SST_HMDC,
	272	SST_HMDC_HDDA1(0xff) \| SST_HMDC_HDDA0(0xff),
	273	SST_HMDC_HDDA1(0xff) \| SST_HMDC_HDDA0(0xff));
a4b12990 MB	274
	275	/* disable all clock gating */
	276	writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2);
	277
	278	/* set DSP to RUN */
	279	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_STALL, 0x0);
	280	}
	281
	282	static void hsw_reset(struct sst_dsp *sst)
	283	{
	284	/* put DSP into reset and stall */
	285	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
	286	SST_CSR_RST \| SST_CSR_STALL, SST_CSR_RST \| SST_CSR_STALL);
	287
	288	/* keep in reset for 10ms */
	289	mdelay(10);
	290
	291	/* take DSP out of reset and keep stalled for FW loading */
	292	sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
	293	SST_CSR_RST \| SST_CSR_STALL, SST_CSR_STALL);
	294	}
	295
	296	struct sst_adsp_memregion {
	297	u32 start;
	298	u32 end;
	299	int blocks;
	300	enum sst_mem_type type;
	301	};
	302
	303	/* lynx point ADSP mem regions */
	304	static const struct sst_adsp_memregion lp_region[] = {
	305	{0x00000, 0x40000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
	306	{0x40000, 0x80000, 8, SST_MEM_DRAM}, /* D-SRAM1 - 8 * 32kB */
	307	{0x80000, 0xE0000, 12, SST_MEM_IRAM}, /* I-SRAM - 12 * 32kB */
	308	};
	309
	310	/* wild cat point ADSP mem regions */
	311	static const struct sst_adsp_memregion wpt_region[] = {
15446c0b	312	{0x00000, 0xA0000, 20, SST_MEM_DRAM}, /* D-SRAM0,D-SRAM1,D-SRAM2 - 20 * 32kB */
a4b12990 MB	313	{0xA0000, 0xF0000, 10, SST_MEM_IRAM}, /* I-SRAM - 10 * 32kB */
	314	};
	315
	316	static int hsw_acpi_resource_map(struct sst_dsp sst, struct sst_pdata pdata)
	317	{
	318	/* ADSP DRAM & IRAM */
	319	sst->addr.lpe_base = pdata->lpe_base;
	320	sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
	321	if (!sst->addr.lpe)
	322	return -ENODEV;
	323
	324	/* ADSP PCI MMIO config space */
	325	sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
	326	if (!sst->addr.pci_cfg) {
	327	iounmap(sst->addr.lpe);
	328	return -ENODEV;
	329	}
	330
	331	/* SST Shim */
	332	sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
	333	return 0;
	334	}
	335
54879323 JY	336	struct sst_sram_shift {
	337	u32 dev_id; /* SST Device IDs */
	338	u32 iram_shift;
	339	u32 dram_shift;
	340	};
	341
	342	static const struct sst_sram_shift sram_shift[] = {
	343	{SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */
	344	{SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */
	345	};
a4b12990 MB	346	static u32 hsw_block_get_bit(struct sst_mem_block *block)
a4b12990 MB	347	{
54879323 JY	348	u32 bit = 0, shift = 0, index;
54879323 JY	349	struct sst_dsp *sst = block->dsp;
a4b12990	350
54879323 JY	351	for (index = 0; index < ARRAY_SIZE(sram_shift); index++) {
	352	if (sram_shift[index].dev_id == sst->id)
	353	break;
a4b12990 MB	354	}
a4b12990 MB	355
54879323 JY	356	if (index < ARRAY_SIZE(sram_shift)) {
	357	switch (block->type) {
	358	case SST_MEM_DRAM:
	359	shift = sram_shift[index].dram_shift;
	360	break;
	361	case SST_MEM_IRAM:
	362	shift = sram_shift[index].iram_shift;
	363	break;
	364	default:
	365	shift = 0;
	366	}
	367	} else
	368	shift = 0;
	369
a4b12990 MB	370	bit = 1 << (block->index + shift);
	371
	372	return bit;
	373	}
	374
c761b583 JY	375	/dummy read a SRAM block./
	376	static void sst_mem_block_dummy_read(struct sst_mem_block *block)
	377	{
	378	u32 size;
	379	u8 tmp_buf[4];
	380	struct sst_dsp *sst = block->dsp;
	381
	382	size = block->size > 4 ? 4 : block->size;
	383	memcpy_fromio(tmp_buf, sst->addr.lpe + block->offset, size);
	384	}
	385
a4b12990 MB	386	/* enable 32kB memory block - locks held by caller */
	387	static int hsw_block_enable(struct sst_mem_block *block)
	388	{
	389	struct sst_dsp *sst = block->dsp;
	390	u32 bit, val;
	391
	392	if (block->users++ > 0)
	393	return 0;
	394
	395	dev_dbg(block->dsp->dev, " enabled block %d:%d at offset 0x%x\n",
	396	block->type, block->index, block->offset);
	397
	398	val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
	399	bit = hsw_block_get_bit(block);
	400	writel(val & ~bit, sst->addr.pci_cfg + SST_VDRTCTL0);
	401
	402	/* wait 18 DSP clock ticks */
	403	udelay(10);
	404
c761b583 JY	405	/add a dummy read before the SRAM block is written, otherwise the writing may miss bytes sometimes./
c761b583 JY	406	sst_mem_block_dummy_read(block);
a4b12990 MB	407	return 0;
	408	}
	409
	410	/* disable 32kB memory block - locks held by caller */
	411	static int hsw_block_disable(struct sst_mem_block *block)
	412	{
	413	struct sst_dsp *sst = block->dsp;
	414	u32 bit, val;
	415
	416	if (--block->users > 0)
	417	return 0;
	418
	419	dev_dbg(block->dsp->dev, " disabled block %d:%d at offset 0x%x\n",
	420	block->type, block->index, block->offset);
	421
	422	val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
	423	bit = hsw_block_get_bit(block);
	424	writel(val \| bit, sst->addr.pci_cfg + SST_VDRTCTL0);
	425
	426	return 0;
	427	}
	428
	429	static struct sst_block_ops sst_hsw_ops = {
	430	.enable = hsw_block_enable,
	431	.disable = hsw_block_disable,
	432	};
	433
	434	static int hsw_enable_shim(struct sst_dsp *sst)
	435	{
	436	int tries = 10;
	437	u32 reg;
	438
	439	/* enable shim */
	440	reg = readl(sst->addr.pci_cfg + SST_SHIM_PM_REG);
	441	writel(reg & ~0x3, sst->addr.pci_cfg + SST_SHIM_PM_REG);
	442
	443	/* check that ADSP shim is enabled */
	444	while (tries--) {
	445	reg = sst_dsp_shim_read_unlocked(sst, SST_CSR);
	446	if (reg != 0xffffffff)
	447	return 0;
	448
	449	msleep(1);
	450	}
	451
	452	return -ENODEV;
	453	}
	454
	455	static int hsw_init(struct sst_dsp sst, struct sst_pdata pdata)
	456	{
	457	const struct sst_adsp_memregion *region;
	458	struct device *dev;
	459	int ret = -ENODEV, i, j, region_count;
	460	u32 offset, size;
	461
10df3509	462	dev = sst->dma_dev;
a4b12990 MB	463
	464	switch (sst->id) {
	465	case SST_DEV_ID_LYNX_POINT:
	466	region = lp_region;
	467	region_count = ARRAY_SIZE(lp_region);
	468	sst->addr.iram_offset = SST_LP_IRAM_OFFSET;
e9600bc1 LG	469	sst->addr.dsp_iram_offset = SST_LPT_DSP_IRAM_OFFSET;
e9600bc1 LG	470	sst->addr.dsp_dram_offset = SST_LPT_DSP_DRAM_OFFSET;
a4b12990 MB	471	sst->addr.shim_offset = SST_LP_SHIM_OFFSET;
	472	break;
	473	case SST_DEV_ID_WILDCAT_POINT:
	474	region = wpt_region;
	475	region_count = ARRAY_SIZE(wpt_region);
	476	sst->addr.iram_offset = SST_WPT_IRAM_OFFSET;
e9600bc1 LG	477	sst->addr.dsp_iram_offset = SST_WPT_DSP_IRAM_OFFSET;
e9600bc1 LG	478	sst->addr.dsp_dram_offset = SST_WPT_DSP_DRAM_OFFSET;
a4b12990 MB	479	sst->addr.shim_offset = SST_WPT_SHIM_OFFSET;
	480	break;
	481	default:
	482	dev_err(dev, "error: failed to get mem resources\n");
	483	return ret;
	484	}
	485
	486	ret = hsw_acpi_resource_map(sst, pdata);
	487	if (ret < 0) {
	488	dev_err(dev, "error: failed to map resources\n");
	489	return ret;
	490	}
	491
	492	/* enable the DSP SHIM */
	493	ret = hsw_enable_shim(sst);
	494	if (ret < 0) {
	495	dev_err(dev, "error: failed to set DSP D0 and reset SHIM\n");
	496	return ret;
	497	}
	498
10df3509	499	ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(31));
a4b12990 MB	500	if (ret)
	501	return ret;
	502
	503	/* Enable Interrupt from both sides */
	504	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX, 0x3, 0x0);
	505	sst_dsp_shim_update_bits_unlocked(sst, SST_IMRD,
	506	(0x3 \| 0x1 << 16 \| 0x3 << 21), 0x0);
	507
	508	/* register DSP memory blocks - ideally we should get this from ACPI */
	509	for (i = 0; i < region_count; i++) {
	510	offset = region[i].start;
	511	size = (region[i].end - region[i].start) / region[i].blocks;
	512
	513	/* register individual memory blocks */
	514	for (j = 0; j < region[i].blocks; j++) {
	515	sst_mem_block_register(sst, offset, size,
	516	region[i].type, &sst_hsw_ops, j, sst);
	517	offset += size;
	518	}
	519	}
	520
85e63007 JY	521	/* set default power gating control, enable power gating control for all blocks. that is,
	522	can't be accessed, please enable each block before accessing. */
	523	writel(0xffffffff, sst->addr.pci_cfg + SST_VDRTCTL0);
a4b12990 MB	524
	525	return 0;
	526	}
	527
	528	static void hsw_free(struct sst_dsp *sst)
	529	{
	530	sst_mem_block_unregister_all(sst);
	531	iounmap(sst->addr.lpe);
	532	iounmap(sst->addr.pci_cfg);
	533	}
	534
	535	struct sst_ops haswell_ops = {
	536	.reset = hsw_reset,
	537	.boot = hsw_boot,
	538	.write = sst_shim32_write,
	539	.read = sst_shim32_read,
	540	.write64 = sst_shim32_write64,
	541	.read64 = sst_shim32_read64,
	542	.ram_read = sst_memcpy_fromio_32,
	543	.ram_write = sst_memcpy_toio_32,
	544	.irq_handler = hsw_irq,
	545	.init = hsw_init,
	546	.free = hsw_free,
	547	.parse_fw = hsw_parse_fw_image,
	548	};